A power factor correction circuit and bus voltage adjustment circuit thereof

Abstract

The utility model discloses a kind of power factor correction circuit and its bus voltage adjusting circuit including drive chip, multiplication branch and adjustment component. Drive chip is connected with the bus of power factor correction circuit through multiplication branch, and also connected with power switch tube in power factor correction circuit, drive chip is configured as according to the deviation of voltage sampling signal and preset reference signal to bus, adjustment control parameter to power switch tube. Adjustment component is connected with multiplication branch, and is configured as by adjusting resistance accessed multiplication branch, change multiplication relationship between voltage sampling signal and bus voltage, realize the hardware adjustment of bus voltage, reduce adjustment difficulty and shorten adjustment time consumption.

Description

Technical Field

[0001] This utility model relates to the field of voltage control, and in particular to a power factor correction circuit and its bus voltage adjustment circuit. Background Technology

[0002] Power factor correction (PFC) technology was developed to address the problems of low power factor and harmonic pollution in AC / DC power supplies. Today, with the maturity of high-frequency switching devices and pulse-width modulation (PWM) driver chips, active PFC circuits have become the mainstream solution.

[0003] For power factor correction circuits, the bus voltage is generally set to a fixed range. The bus voltage for power factor correction is determined by the hardware circuit. Once the hardware parameters are designed, the bus voltage cannot be changed according to the requirements. Therefore, the output voltage of the circuit can only be a fixed value within a fixed range.

[0004] In the existing technology, if the circuit needs to output a voltage outside the range, it needs to be adjusted by DSP software. This software adjustment method requires changing the internal reference voltage of the software, and the adjustment process is both complicated and time-consuming. Utility Model Content

[0005] This invention provides a power factor correction circuit and its bus voltage adjustment circuit to reduce adjustment difficulty and shorten adjustment time.

[0006] According to one aspect of the present invention, a bus voltage adjustment circuit for a power factor correction circuit is provided, the bus voltage adjustment comprising: a driver chip, a multiplier branch, and an adjustment component;

[0007] The driver chip is connected to the bus of the power factor correction circuit via the multiplication branch, and is also connected to the power switch in the power factor correction circuit. The driver chip is configured to adjust the control parameters of the power switch according to the deviation between the voltage sampling signal of the bus and the preset reference signal.

[0008] The adjustment component is connected to the multiplier branch and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage by adjusting the resistor connected to the multiplier branch.

[0009] Optionally, the multiplication branch includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a first adjustment resistor and a boost control component.

[0010] The first sampling resistor and the second sampling resistor are connected in series between the bus and the ground terminal, and the connection point of the two is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor;

[0011] The first end of the first adjusting resistor is connected to the connection point, and the second end is grounded through the boost control component. The boost control component is configured to switch the connection between the second end of the first adjusting resistor and the grounded end.

[0012] Optionally, the boost control assembly includes a first controllable switch, a first optocoupler, and a boost control terminal;

[0013] The first controllable switch is disposed between the second end of the first adjusting resistor and the grounding end; the input side of the first optocoupler is connected to the boost control terminal, and its output side is connected to the control terminal of the first controllable switch. The first optocoupler is configured to control the on / off state of the first controllable switch according to the boost control signal input to the boost control terminal.

[0014] Optionally, the first adjusting resistor includes a controllable resistor.

[0015] Optionally, the multiplication branch includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a buck control component;

[0016] The first sampling resistor and the second sampling resistor are connected in series between the bus and the ground terminal, and the connection point of the two is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor;

[0017] The step-down control component is disposed between the third sampling resistor and the connection point, and is configured to switch the on / off state between the third sampling resistor and the connection point.

[0018] Optionally, the step-down control component includes a second controllable switch, a second optocoupler, and a step-down control terminal;

[0019] The second controllable switch is disposed between the third sampling resistor and the connection point; the input side of the second optocoupler is connected to the step-down control terminal, and its output side is connected to the control terminal of the second controllable switch. The second optocoupler is configured to control the on / off state of the second controllable switch according to the step-down control signal input to the step-down control terminal.

[0020] Optionally, the third sampling resistor may include a controllable resistor.

[0021] Optionally, the controllable switch includes an N-channel power MOSFET.

[0022] Optionally, the driver chip includes a power factor correction controller chip.

[0023] According to another aspect of the present invention, a power factor correction circuit is provided, which includes a power meter switching transistor, a bus, and a bus voltage adjustment circuit of any of the power factor correction circuits described in the first aspect.

[0024] The power factor correction circuit and its bus voltage adjustment circuit provided in this embodiment include a driver chip, a multiplier branch, and an adjustment component. The driver chip is connected to the bus of the power factor correction circuit via the multiplier branch and is also connected to the power switch in the power factor correction circuit. The driver chip is configured to adjust the control parameters of the power switch based on the deviation between the voltage sampling signal of the bus and a preset reference signal. The adjustment component is connected to the multiplier branch and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage by adjusting the resistor connected to the multiplier branch, thereby realizing hardware adjustment of the bus voltage, reducing the adjustment difficulty and shortening the adjustment time.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the bus voltage adjustment circuit of a power factor correction circuit provided in this embodiment of the present invention;

[0028] Figure 2 A schematic diagram of the bus voltage adjustment circuit of another power factor correction circuit provided in this embodiment of the present utility model;

[0029] Figure 3 A schematic diagram of the bus voltage adjustment circuit of another power factor correction circuit provided in this embodiment of the present utility model;

[0030] Figure 4 This is a schematic diagram of a power factor correction circuit provided in an embodiment of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] To address the problems mentioned in the background art, this utility model proposes a bus voltage adjustment circuit for a power factor correction circuit. Figure 1 A schematic diagram of the bus voltage adjustment circuit of a power factor correction circuit provided in this embodiment of the present invention is shown below. Figure 1 The bus voltage adjustment circuit 100 of the power factor correction circuit includes a driver chip 101, a multiplier branch 102, and an adjustment component 103. The driver chip 101 is connected to the bus BUS of the power factor correction circuit via the multiplier branch 102, and is also connected to the power switch Q in the power factor correction circuit. The driver chip 101 is configured to adjust the control parameters of the power switch Q based on the deviation between the voltage sampling signal of the bus BUS and a preset reference signal. The adjustment component 103 is connected to the multiplier branch 102 and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage VBUS by adjusting the resistor connected to the multiplier branch 102.

[0034] Specifically, the driver chip 101 refers to a functional chip that drives the power switch Q in the power factor correction circuit. Its error sampling terminal a can sample the bus voltage VBUS in the power factor correction circuit via the multiplier branch 102, compare the voltage sampling signal with a preset reference signal to determine the error of the bus voltage VBUS, and adjust the drive signal to the power switch Q accordingly based on the error. The preset reference signal is determined based on the initial set value of the bus voltage VBUS and the initial structure of the multiplier branch 102. For example, the driver chip 101 can adjust the bus voltage VBUS by adjusting the duty cycle of the pulse width modulation signal supplied to the control terminal of the power switch Q. The driver chip 101 may include a power factor correction controller chip of model EG1654.

[0035] The multiplier branch 102 refers to a circuit that provides a multiplicative relationship (also known as a voltage calculation relationship) between the sampling point on the bus and the error sampling terminal a. For example, the multiplier branch 102 may include multiple resistors connected in series between the sampling point and the ground terminal on the bus BUS. The connection point between any two adjacent resistors can serve as the feedback terminal of the multiplier branch 102, connected to the error sampling terminal a of the driver chip 101. The multiplier branch 102 can use resistors to divide the bus voltage VBUS, and the voltage sampling signal obtained after voltage division is fed back to the driver chip 101 via the error sampling terminal a. The initial structure of the multiplication branch 102 is determined, so the initial multiplication relationship between the bus voltage VBUS and the voltage value V0 of the voltage sampling signal is also determined. For example, when the initial setting value of the bus voltage VBUS is 400V and the initial multiplication relationship between the bus voltage VBUS provided by the multiplication branch 102 and the voltage value V0 of the voltage sampling signal is expressed as 159*V0+V0=VBUS, the voltage value of the initial reference signal of the driver chip 101 can be set to 2.5V.

[0036] Adjustment component 103 refers to a functional component that adjusts the multiplication relationship provided by multiplication branch 102. For example, adjustment component 103 may include a controllable switch, which may be disposed in a parallel resistor branch of multiplication branch 102. By adjusting the on / off state of the controllable switch, the initial structure of multiplication branch 102 is changed, thereby changing the multiplication relationship. Adjustment component 103 may also include an adjustment resistor, which may be connected to multiplication branch 102 via the controllable switch. By adjusting the on / off state of the controllable switch, the initial structure of multiplication branch 102 is changed, thereby changing the multiplication relationship.

[0037] The bus voltage adjustment circuit of the power factor correction circuit provided in this embodiment includes a driver chip, a multiplier branch, and an adjustment component. The driver chip is connected to the bus of the power factor correction circuit via the multiplier branch and is also connected to the power switch in the power factor correction circuit. The driver chip is configured to adjust the control parameters of the power switch based on the deviation between the voltage sampling signal of the bus and a preset reference signal. The adjustment component is connected to the multiplier branch and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage by adjusting the resistor connected to the multiplier branch, thereby realizing hardware adjustment of the bus voltage, reducing the adjustment difficulty and shortening the adjustment time.

[0038] Optionally, Figure 2 This is a schematic diagram of the bus voltage adjustment circuit for another power factor correction circuit provided in this embodiment of the present invention. Based on the foregoing embodiment, refer to... Figure 2 The multiplier branch 102 includes a first sampling resistor R1, a second sampling resistor R2, and a third sampling resistor R3; the adjustment component 103 includes a first adjustment resistor R4 and a boost control component 201. The first sampling resistor R1 and the second sampling resistor R2 are connected in series between the bus BUS and the ground terminal PGND, and their connection point K is connected to the error sampling terminal a of the driver chip 101; the third sampling resistor R3 is connected in parallel with the second sampling resistor R2. The first end of the first adjustment resistor R4 is connected to the connection point K, and the second end is grounded through the boost control component 201. The boost control component 201 is configured to switch the connection between the second end of the first adjustment resistor R4 and the ground terminal PGND.

[0039] Specifically, the first adjusting resistor R4 is a functional resistor used to assist in adjusting the electrical structure of the multiplier branch 102. In the initial state, the second terminal of the first adjusting resistor R4 is disconnected from the ground terminal PGND. The boost control component 201 is a functional component that controls whether the first adjusting resistor R4 is grounded. When it is necessary to adjust the set value of the bus voltage VBUS, the adjusting component 103 can use the boost control component 201 to connect the second terminal of the first adjusting resistor R4 to the ground terminal PGND, so that the first adjusting resistor R4 is connected to the multiplier branch 102, thereby changing the multiplication relationship provided by the multiplier branch 102. In some embodiments, the first adjusting resistor R4 can be a resistor with a fixed resistance value, so the adjustable value of the bus voltage VBUS above the initial set value is a single value; in other embodiments, the first adjusting resistor R4 can also be a controllable resistor with a variable resistance value. By adjusting the resistance value of the controllable resistor connected to the circuit, a linear setting of the adjustable value of the bus voltage VBUS above the initial set value can be achieved.

[0040] For example, the boost control component 201 may include a first controllable switch Q1, a first optocoupler 202, and a boost control terminal b. The first controllable switch Q1 is disposed between the second terminal of the first adjusting resistor R4 and the ground terminal PGND; the input side of the first optocoupler 202 is connected to the boost control terminal b, and its output side is connected to the control terminal of the first controllable switch Q1. The first optocoupler 202 is configured to control the on / off state of the first controllable switch Q1 according to the boost control signal connected to the boost control terminal b. The first controllable switch Q1 may be an N-channel power MOSFET or an IGBT, and the boost control terminal b may be externally connected to a control device such as an MCU.

[0041] When the bus voltage VBUS needs to be higher than the initial set value, the control signal connected to the boost control terminal b changes from high level to low level, so that a positive voltage difference is formed between the first driving voltage source S3V3 and the low level, and the light-emitting device on the input side of the first optocoupler 202 emits light, so that the output side of the first optocoupler 202 is also turned on, and the second driving voltage source P3V3 is applied to the gate of the first controllable switch Q1, so that the first controllable switch Q1 is turned on. From this point on, the first adjustment resistor R4 is connected in parallel to the two ends of the parallel branch formed by the second resistor and the third resistor in the multiplication branch 102, so as to reduce the lower bias resistance of the error sampling terminal a, which is equivalent to changing the multiplication relationship between the voltage sampling signal and the bus voltage VBUS, thereby increasing the set value of the bus voltage VBUS.

[0042] The following example uses specific settings. Assume the first sampling resistor R1 has a resistance of 1996KΩ, the second sampling resistor R2 has a resistance of 13.7KΩ, the third sampling resistor R3 has a resistance of 150KΩ, and the initial reference signal voltage of the driver chip 101 is set to 2.5V. The product relationship between the voltage value V0 of the voltage sampling signal before adjustment and the bus voltage VBUS can be expressed as V0 =

[0043] R2 / / R3*VBUS / (R1+R2 / / R3). The driver chip 101 adjusts the bus voltage VBUS by changing the on / off state of the power switch Q, ensuring that the voltage value V0 of the voltage sampling signal is equal to the initial reference signal voltage value Vref, which is 2.5V. Combining the multiplication relationship before adjustment, the bus voltage VBUS can be calculated by using the value of Vref (2.5V). In other words, before adjustment, the driver chip 101 will keep the bus voltage VBUS at 398.1V.

[0044] When the bus voltage (BUS) needs to be boosted, the first adjusting resistor R4 is connected in parallel across the parallel branch formed by the second and third resistors in the multiplication branch 102. At this time, the new multiplicative relationship between the voltage value V0 of the voltage sampling signal and the bus voltage VBUS can be expressed as V0 = R2 / / R3 / / R4*VBUS / (R1+R2 / / R3 / / R4). However, the initial reference signal voltage value Vref of the driver chip 101 remains unchanged. The driver chip 101 will still adjust the bus voltage VBUS by adjusting the on / off state of the power switch Q to keep the voltage value V0 of the voltage sampling signal equal to the initial reference signal voltage value Vref, which is 2.5V. Combining the new multiplicative relationship, the adjusted bus voltage VBUS can be calculated using the value of Vref (2.5V). In other words, after adjustment, the driver chip 101 will continuously maintain the bus voltage VBUS at 450V, thereby making the bus voltage VBUS range of the power factor correction circuit wider.

[0045] The bus voltage adjustment circuit of the power factor correction circuit provided in this embodiment includes a multiplication branch comprising a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a first adjustment resistor and a boost control component. The first and second sampling resistors are connected in series between the bus and the ground terminal, and their connection point is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor. The first end of the first adjustment resistor is connected to the connection point, and the second end is grounded through the boost control component. The boost control component is configured to switch the connection between the second end of the first adjustment resistor and the ground terminal, thereby increasing the bus voltage and widening the adjustable range of the bus voltage of the power factor correction circuit through hardware settings.

[0046] Optionally, Figure 3 This is a schematic diagram of the bus voltage adjustment circuit of another power factor correction circuit provided in this embodiment of the present invention. Figure 3 The reference numerals x and y in the attached figures are used to illustrate the specific connection relationships between the step-down control component 301, the third sampling resistor R3, and the connection point K, respectively. Both x's indicate the same point, and both y's also indicate the same point. Based on the aforementioned embodiment, refer to... Figure 3 The multiplier branch 102 includes a first sampling resistor R1, a second sampling resistor R2, and a third sampling resistor R3; the adjustment component 103 includes a step-down control component 301. The first sampling resistor R1 and the second sampling resistor R2 are connected in series between the bus BUS and the ground terminal PGND, and their connection point K is connected to the error sampling terminal a of the driver chip 101; the third sampling resistor R3 is connected in parallel with the second sampling resistor R2. The step-down control component 301 is disposed between the third sampling resistor R3 and the connection point K, and is configured to switch the on / off state between the third sampling resistor R3 and the connection point K.

[0047] Specifically, the third sampling resistor R3 is also used to assist in adjusting the electrical structure of the multiplier branch 102. In the initial state, the first terminal of the third sampling resistor R3 remains conductive with connection point K. The buck control component 301 is a functional component that controls whether the third sampling resistor R3 is connected to connection point K. When it is necessary to adjust the set value of the bus voltage VBUS, the adjustment component 103 can use the buck control component 301 to disconnect the first terminal of the third sampling resistor R3 from connection point K, thereby achieving electrical disconnection of the third sampling resistor R3 and changing the multiplication relationship provided by the multiplier branch 102. In some embodiments, the third sampling resistor R3 can be a resistor with a fixed resistance value, so the bus voltage VBUS can be adjusted to a value lower than the initial set value; in other embodiments, the third sampling resistor R3 can also be a controllable resistor with a variable resistance value, and by adjusting the resistance value of the controllable resistor connected to the circuit, a linear setting of the bus voltage VBUS below the initial set value can be achieved.

[0048] For example, the buck control component 301 includes a second controllable switch Q2, a second optocoupler 302, and a buck control terminal c. The second controllable switch Q2 is disposed between the third sampling resistor R3 and the connection point K; the input side of the second optocoupler 302 is connected to the buck control terminal c, and its output side is connected to the control terminal of the second controllable switch Q2. The second optocoupler 302 is configured to control the on / off state of the second controllable switch Q2 according to the buck control signal input to the buck control terminal c. The first controllable switch Q1 can be an N-channel power MOSFET or an IGBT.

[0049] When the bus voltage VBUS needs to be lower than the initial set value, the control signal connected to the step-down control terminal c changes from low level to high level. The first driving voltage source S3V3 cannot form a positive voltage difference with the high level, causing the light-emitting device on the input side of the second optocoupler 302 to turn off. As a result, the output side of the second optocoupler 302 is also turned off, cutting off the driving voltage source P3V3 applied to the gate of the second controllable switch Q2, thereby turning off the second controllable switch Q2. This removes the third sampling resistor R3 from the multiplication branch 102, thereby increasing the downward bias resistance of the error sampling terminal a. This is equivalent to changing the multiplication relationship between the voltage value V0 of the voltage sampling signal and the bus voltage VBUS, thereby reducing the set value of the bus voltage VBUS.

[0050] The following example uses specific settings. Assume the first sampling resistor R1 has a resistance of 1996KΩ, the second sampling resistor R2 has a resistance of 13.7KΩ, the third sampling resistor R3 has a resistance of 150KΩ, and the initial reference signal voltage of the driver chip 101 is set to 2.5V. The product relationship between the voltage value V0 of the voltage sampling signal before adjustment and the bus voltage VBUS can be expressed as V0 =

[0051] R2 / / R3*VBUS / (R1+R2 / / R3). The driver chip 101 adjusts the bus voltage VBUS by changing the on / off state of the power switch Q, ensuring that the voltage value V0 of the voltage sampling signal is equal to the initial reference signal voltage value Vref, which is 2.5V. Based on the multiplication relationship before adjustment, the bus voltage VBUS can be calculated by using the value of Vref (2.5V). In other words, before adjustment, the driver chip 101 will keep the bus voltage VBUS at 398.1V.

[0052] When the bus voltage (BUS) needs to be stepped down, the third sampling resistor R3 is removed and no longer connected in parallel with the second sampling resistor R2. At this time, the new multiplicative relationship between the voltage sampling signal and the bus voltage VBUS can be expressed as Vref = R2 * VBUS / (R1 + R2). However, the initial reference signal voltage value of the driver chip 101 remains unchanged. The driver chip 101 will still adjust the bus voltage VBUS by adjusting the on / off state of the power switch Q to keep the voltage value of the voltage sampling signal equal to the initial reference signal voltage value, which is 2.5V. Based on the new multiplicative relationship, the adjusted bus voltage VBUS can be calculated using the value of Vref (2.5V). In other words, after adjustment, the driver chip 101 will continuously maintain the bus voltage VBUS at 366V, thereby making the bus voltage VBUS range of the power factor correction circuit wider.

[0053] The bus voltage adjustment circuit of the power factor correction circuit provided in this embodiment includes a multiplication branch comprising a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a buck control component. The first and second sampling resistors are connected in series between the bus and the ground terminal, and their connection point is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor. The buck control component is located between the third sampling resistor and the connection point and is configured to switch the on / off state between the third sampling resistor and the connection point, thereby reducing the bus voltage and further widening the adjustable range of the bus voltage of the power factor correction circuit through hardware settings.

[0054] This utility model also provides a power factor correction circuit. Figure 4 This is a schematic diagram of a power factor correction circuit provided in an embodiment of the present invention. Based on the foregoing embodiments, refer to... Figure 4 The power factor correction circuit 400 includes a power switch Q, a bus BUS, and a bus voltage adjustment circuit 100 of any of the aforementioned power factor correction circuits.

[0055] The power factor correction circuit and its bus voltage adjustment circuit provided in this embodiment include a driver chip, a multiplier branch, and an adjustment component. The driver chip is connected to the bus of the power factor correction circuit via the multiplier branch and is also connected to the power switch in the power factor correction circuit. The driver chip is configured to adjust the control parameters of the power switch based on the deviation between the voltage sampling signal of the bus and a preset reference signal. The adjustment component is connected to the multiplier branch and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage by adjusting the resistor connected to the multiplier branch, thereby realizing hardware adjustment of the bus voltage, reducing the adjustment difficulty and shortening the adjustment time.

[0056] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A bus voltage adjustment circuit of a power factor correction circuit, characterized by, include: Driver chip, multiplier branch and adjustment component; The driver chip is connected to the bus of the power factor correction circuit via the multiplication branch, and is also connected to the power switch in the power factor correction circuit. The driver chip is configured to adjust the control parameters of the power switch according to the deviation between the voltage sampling signal of the bus and the preset reference signal. The adjustment component is connected to the multiplier branch and is configured to change the multiplicative relationship between the voltage sampling signal and the bus voltage by adjusting the resistor connected to the multiplier branch.

2. The bus voltage adjustment circuit of the power factor correction circuit according to claim 1, characterized in that, The multiplication branch includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a first adjustment resistor and a boost control component; The first sampling resistor and the second sampling resistor are connected in series between the bus and the ground terminal, and the connection point of the two is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor; The first end of the first adjusting resistor is connected to the connection point, and the second end is grounded through the boost control component. The boost control component is configured to switch the connection between the second end of the first adjusting resistor and the grounded end.

3. The bus voltage regulating circuit of a power factor correcting circuit according to claim 2, characterized by The boost control component includes a first controllable switch, a first optocoupler, and a boost control terminal; The first controllable switch is disposed between the second end of the first adjusting resistor and the grounding end; the input side of the first optocoupler is connected to the boost control terminal, and its output side is connected to the control terminal of the first controllable switch. The first optocoupler is configured to control the on / off state of the first controllable switch according to the boost control signal input to the boost control terminal.

4. The bus voltage adjustment circuit of the power factor correction circuit according to claim 2, characterized by The first adjusting resistor includes a controllable resistor.

5. The bus voltage regulating circuit of a power factor correcting circuit according to claim 1, characterized by, The multiplication branch includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the adjustment component includes a buck control component; The first sampling resistor and the second sampling resistor are connected in series between the bus and the ground terminal, and the connection point of the two is connected to the error sampling terminal of the driver chip; the third sampling resistor is connected in parallel with the second sampling resistor; The step-down control component is disposed between the third sampling resistor and the connection point, and is configured to switch the on / off state between the third sampling resistor and the connection point.

6. The bus voltage regulating circuit of a power factor correcting circuit according to claim 5, characterized by The step-down control component includes a second controllable switch, a second optocoupler, and a step-down control terminal; The second controllable switch is disposed between the third sampling resistor and the connection point; the input side of the second optocoupler is connected to the step-down control terminal, and its output side is connected to the control terminal of the second controllable switch. The second optocoupler is configured to control the on / off state of the second controllable switch according to the step-down control signal input to the step-down control terminal.

7. The bus voltage regulating circuit of a power factor correcting circuit according to any one of claims 2-6, characterized in that, The third sampling resistor includes a controllable resistor.

8. The bus voltage regulating circuit of a power factor correcting circuit according to claim 3 or 6, characterized by, The controllable switch includes an N-channel power MOSFET.

9. The bus voltage regulating circuit of a power factor correcting circuit according to any one of claims 1 to 6, characterized by, The driver chip includes a power factor correction controller chip.

10. A power factor correction circuit, characterized by, The bus voltage adjustment circuit includes a power meter switching transistor, a bus, and a power factor correction circuit as described in any one of claims 1-9.

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