Capacitor regulation circuit and RF front-end module

Abstract

This application relates to the field of radio frequency (RF) technology and discloses a capacitor adjustment circuit and an RF front-end module. The capacitor adjustment circuit includes: a signal input terminal; a signal output terminal; and an adjustable capacitor unit, including at least two switching transistors. The switching transistors include a first switching transistor and a second switching transistor connected in series between the signal input terminal and the signal output terminal. Each switching transistor also includes a controlled terminal. Each switching transistor receives a control signal through the controlled terminal and controls the switching transistor to be turned on or off, so that the adjustable capacitor unit has different capacitance values. This application controls the on or off state of each switching transistor to give the adjustable capacitor unit different capacitance values, thereby finely adjusting the overall capacitance value presented by the capacitor adjustment circuit. Furthermore, when both the first and second switching transistors are turned off, the capacitance value of the adjustable capacitor unit can reach a very small state, adapting to application scenarios with high sensitivity to capacitance values ​​and requiring fine-tuning.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a capacitor regulation circuit and a radio frequency front-end module. Background Technology

[0002] The radio frequency (RF) front-end module is a crucial component of a wireless transceiver system. Its primary function is to output or receive RF signals from external sources. The RF front-end module includes a receiving circuit configured to receive externally input RF signals. This receiving circuit requires a matching circuit to provide the necessary capacitance value for normal operation, thereby improving its performance. The capacitance value provided by the matching circuit varies depending on the specific operating scenario and signal reception requirements of the receiving circuit.

[0003] However, the capacitance values ​​provided by the matching circuits in current technologies are not precise enough to reduce the capacitance value to 0, and the range of capacitance values ​​provided is usually greater than 100fF, which is not compatible with the working scenarios of some receiving circuits and cannot better meet the usage requirements.

[0004] Therefore, how to improve the adjustment accuracy of the capacitor value in the receiving circuit and configure the optimal capacitor value for the application scenario of the receiving circuit is an urgent problem to be solved. Utility Model Content

[0005] This application provides a capacitor adjustment circuit and an RF front-end module, which aim to configure a better capacitor value adjustment range for the application scenarios of the receiving circuit and improve the adjustment accuracy of the capacitor value.

[0006] In a first aspect, embodiments of this application provide a capacitor regulation circuit, including:

[0007] Signal input terminal;

[0008] Signal output terminal;

[0009] An adjustable capacitor unit includes at least two switching transistors, the at least two switching transistors including at least a first switching transistor and a second switching transistor, the input terminal of the first switching transistor is connected to a signal input terminal, the input terminal of the second switching transistor is connected to the output terminal of the first switching transistor, and the output terminal of the second switching transistor is connected to a signal output terminal;

[0010] The switching transistor also includes a controlled terminal, which is configured to receive a control signal and control the switching transistor to turn on or off. Each switching transistor can be selectively turned on or off so that the adjustable capacitor unit has different capacitance values.

[0011] In some implementations, the minimum adjustable capacitance value of the adjustable capacitor unit is less than or equal to 50 fF.

[0012] In some implementations, the capacitor regulation circuit further includes at least one third switching transistor;

[0013] The first switch, at least one third switch, and the second switch are connected in series between the signal input terminal and the signal output terminal. When the first switch, at least one third switch, and the second switch are all turned off, the adjustable capacitor unit has a capacitance value of less than or equal to 50fF.

[0014] In some implementations, the capacitance value is 25fF-100fF when the first switch is turned off;

[0015] And / or, the capacitance value when the second switch is turned off is 25fF-100fF;

[0016] And / or, the capacitance value when the first switch is turned off is the same as the capacitance value when the second switch is turned off.

[0017] In some embodiments, the capacitor adjustment circuit further includes a first parallel unit, one end of which is connected to the input terminal of the first switching transistor and the other end of which is connected to the output terminal of the second switching transistor, wherein the capacitance value of the first parallel unit is adjustable.

[0018] In some implementations, the first parallel unit includes at least one fourth switch, and the at least one fourth switch is connected between the input terminal of the first switch and the output terminal of the second switch.

[0019] The fourth switch is configured to be turned on or off based on a control signal input from the controlled terminal of the fourth switch, so that the first parallel unit has different capacitance values.

[0020] Furthermore, the number of fourth switching transistors is less than or equal to the number of switching transistors in the adjustable capacitor unit.

[0021] In some embodiments, the capacitance of the fourth switch in the off state is less than the capacitance of the first switch in the off state and the capacitance of the second switch in the off state; and / or,

[0022] The capacitance of the fourth switch in the off state is 25fF-100fF; and / or,

[0023] The first parallel unit includes at least two fourth switching transistors, which are connected in series between the signal input terminal and the signal output terminal, and the capacitance values ​​of the at least two fourth switching transistors are the same in the off state.

[0024] In some embodiments, the capacitor regulation circuit further includes a second parallel unit, which includes at least one first capacitor element, and the at least one first capacitor element is connected between the input terminal of the first switching transistor and the output terminal of the second switching transistor.

[0025] In some implementations, the capacitance of the first capacitor element is greater than or equal to the capacitance when the switch is turned off.

[0026] In some implementations, the capacitance of the first capacitor element is greater than or equal to 110fF.

[0027] In some embodiments, the capacitor adjustment circuit further includes a preamplifier circuit connected between the signal input terminal and the input terminal of the first switching transistor. The capacitor value of the preamplifier circuit is adjustable or has a first preset capacitor value, and the first preset capacitor value differs from the capacitor value when the first switching transistor is off and the capacitor value when the second switching transistor is off; and / or,

[0028] The capacitor adjustment circuit also includes a post-circuit, which is connected between the output terminal of the second switch and the signal output terminal. The capacitor value of the post-circuit is adjustable or has a second preset capacitor value, which is different from the capacitor value when the first switch is turned off and the capacitor value when the second switch is turned off.

[0029] In some embodiments, the preamplifier circuit includes at least one fifth switch connected between the signal input terminal and the input terminal of the first switch. The fifth switch is configured to turn on or off based on a control signal input from its controlled terminal, such that the preamplifier circuit has different capacitance values; and / or,

[0030] The post-amplifier circuit includes at least one sixth switch connected between the output terminal of the second switch and the signal output terminal. The sixth switch is configured to turn on or off based on a control signal input from its controlled terminal, such that the pre-amplifier circuit has different capacitance values; and / or,

[0031] The preamplifier circuit includes at least one second capacitor element, and the at least one second capacitor element is connected between the signal input terminal and the input terminal of the first switching transistor; and / or,

[0032] The post-amplifier circuit includes at least one third capacitor element, and the at least one third capacitor element is connected between the signal input terminal and the input terminal of the first switching transistor.

[0033] In some embodiments, the capacitor regulation circuit further includes at least two fourth switching transistors connected in series, and the input terminals of the at least two fourth switching transistors are located at the output terminal of the nth switching transistor of the adjustable capacitor unit, and the output terminals of the at least two fourth switching transistors are located at the output terminal of the (n+x)th switching transistor of the adjustable capacitor unit, where n and x are greater than or equal to 1 and are integers.

[0034] In some implementations, the capacitor regulation circuit also includes a switching transistor control circuit;

[0035] The switching transistor control circuit is connected to the controlled terminal of the target switching transistor in the capacitor regulation circuit, and is used to output a control signal to the controlled terminal of the target switching transistor to control the target switching transistor to switch between the on and off states.

[0036] The target switching transistor includes at least a portion of the switching transistors in the capacitor regulation circuit.

[0037] In some implementations, the target switch is a field-effect transistor, with the input terminal being the source, the output terminal being the drain, and the controlled terminal being the gate.

[0038] Secondly, embodiments of this application also provide a radio frequency front-end module, including any of the capacitor adjustment circuits provided in embodiments of this application.

[0039] In summary, this application provides a capacitor adjustment circuit and an RF front-end module. The capacitor adjustment circuit includes: a signal input terminal; a signal output terminal; and an adjustable capacitor unit, including at least two switching transistors, each including at least a first switching transistor and a second switching transistor. The input terminal of the first switching transistor is connected to the signal input terminal, the input terminal of the second switching transistor is connected to the output terminal of the first switching transistor, and the output terminal of the second switching transistor is connected to the signal output terminal. Each switching transistor also includes a controlled terminal configured to receive a control signal and control the switching transistors to turn on or off. Each switching transistor can be selectively turned on or off, so that the adjustable capacitor unit has different capacitance values.

[0040] This capacitor adjustment circuit utilizes the characteristic of adjusting the capacitance value when the switching transistors are off. By controlling each switching transistor to be on or off, the adjustable capacitor unit has different capacitance values, thereby finely adjusting the overall capacitance value presented by the capacitor adjustment circuit. Furthermore, when both the first and second switching transistors are off, the capacitance value of the adjustable capacitor unit can reach a very small state, which is suitable for applications with high sensitivity to capacitance values ​​and requiring fine adjustment, such as the matching circuit in the low noise amplifier (LNA) of the RF front-end module. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a module structure of a capacitor regulation circuit provided in an embodiment of this application;

[0043] Figure 2A schematic diagram of a capacitor regulation circuit provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0045] Figure 4 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0046] Figure 5 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0047] Figure 6 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0048] Figure 7 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0049] Figure 8 This is a schematic diagram of another circuit structure of the capacitor regulation circuit provided in one embodiment of this application;

[0050] Figure 9 Another circuit structure for the capacitor regulation circuit provided in one embodiment of this application;

[0051] Figure 10 Another circuit structure for the capacitor regulation circuit provided in one embodiment of this application;

[0052] Figure 11 This is a schematic block diagram of a radio frequency front-end module provided in an embodiment of this application.

[0053] Figure label:

[0054] 1. Capacitor adjustment circuit; 10. Signal input terminal; 20. Signal output terminal; 30. Adjustable capacitor unit; 40. Switching transistor; 41. First switching transistor; 42. Second switching transistor; 43. Third switching transistor; 44. Sixth switching transistor; 50. First parallel unit; 51. Fourth switching transistor; 60. Second parallel unit; 61. First capacitor element; 70. Preamplifier circuit; 71. Second capacitor element; 72. Fifth switching transistor; 80. Postamplifier circuit; 81. Third capacitor element; 82. Sixth switching transistor; 90. Switching transistor control circuit;

[0055] 2. Radio frequency front-end module;

[0056] G. Controlled end. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged; therefore, the actual execution order may change according to the actual situation.

[0058] The radio frequency (RF) front-end module is a crucial component of a wireless transceiver system. Its primary function is to output or receive RF signals from external sources. The RF front-end module includes a receiving circuit configured to receive externally input RF signals. This receiving circuit requires a matching circuit to provide the necessary capacitance value for normal operation, thereby improving its performance. The capacitance value provided by the matching circuit varies depending on the specific operating scenario and signal reception requirements of the receiving circuit.

[0059] However, the matching circuits in current technologies do not provide sufficient precision in adjusting the capacitance value to zero, and the range of capacitance value variation or adjustment is often too large, such as 100fF-200fF, which is inconsistent with the working scenarios of some receiving circuits.

[0060] Therefore, how to improve the adjustment accuracy of the capacitor value in the receiving circuit and configure an appropriate capacitor range for the application scenario of the receiving circuit is an urgent problem to be solved.

[0061] To address the aforementioned problems, this application provides a capacitor regulation circuit and an RF front-end module. The technical solution of this application will be described below with reference to the accompanying drawings.

[0062] Please see Figures 1 to 2 , Figure 1 This is a schematic diagram of a module structure of a capacitor regulation circuit 1 provided in an embodiment of this application. Figure 2 This is a schematic diagram of a capacitor regulation circuit 1 provided in an embodiment of this application.

[0063] like Figures 1 to 2 As shown, this application provides a capacitor adjustment circuit 1, which includes at least a signal input terminal 10, a signal output terminal 20, and an adjustable capacitor unit 30, wherein the adjustable capacitor unit 30 is connected between the signal input terminal 10 and the signal output terminal 20.

[0064] It should be noted that the signal input terminal 10 is configured to receive the signal to be processed (e.g., an RF signal), and the target signal is obtained by the adjustable capacitor unit 30 through corresponding processing of the signal to be processed. The signal output terminal 20 is configured to output the target signal to the subsequent circuit.

[0065] The structure and function of the adjustable capacitor unit 30 are described in detail below.

[0066] Specifically, the adjustable capacitor unit 30 includes at least two switching transistors 40, which can be arranged in series, parallel, or a combination of series and parallel connections between the signal input terminal 10 and the signal output terminal 20. Each switching transistor 40 has both an input terminal and an output terminal. As one embodiment, the switching transistors 40 in the adjustable capacitor unit 30 include at least a first switching transistor 41 and a second switching transistor 42. The input terminal of the first switching transistor 41 is connected to the signal input terminal 10, the input terminal of the second switching transistor 42 is connected to the output terminal of the first switching transistor 41, and the output terminal of the second switching transistor 42 is connected to the signal output terminal 20. It should be understood that the first switching transistor 41 and the second switching transistor 42 can be considered as being connected in series between the signal input terminal 10 and the signal output terminal 20.

[0067] For example, the input terminal of the first switch transistor 41 can be directly connected to the signal input terminal 10, or it can be indirectly connected to the signal input terminal 10 through other circuit structures. Similarly, the output terminal of the first switch transistor 41 can be directly connected to the input terminal of the second switch transistor 42, or it can be indirectly connected to the input terminal of the second switch transistor 42 through other circuit structures, such as connecting a switch transistor 40 between the first switch transistor 41 and the second switch transistor 42. Similarly, the output terminal of the second switch transistor 42 can be directly connected to the signal output terminal 20, or it can be indirectly connected to the signal output terminal 20 through other circuit structures. In this embodiment, the relative positions of the first switch transistor 41 and the second switch transistor 42 are not specifically limited.

[0068] The switching transistor 40 also includes a controlled terminal G, which is configured to receive a control signal and control the switching transistor 40 to turn on or off. For example, the switching transistor control circuit 90 inputs a control signal to the controlled terminal G of the switching transistor 40 to control the switching transistor 40 to switch between on and off states. Furthermore, each switching transistor 40 can be selectively turned on or off, so that the adjustable capacitor unit 30 has different capacitance values. It should be noted that the on / off control of each switching transistor 40 is independent and does not affect each other.

[0069] The principle of providing different capacitance values ​​in the adjustable capacitor unit 30 is explained as follows: When all the switching transistors 40 are turned on, the switching transistors 40 can be regarded as a closed circuit and the capacitance value provided by them in the adjustable capacitor unit 30 is 0. When the switching transistors 40 are turned off, the switching transistors 40 are capacitive in the adjustable capacitor unit 30 and the capacitance value provided matches the parasitic capacitance of the switching transistors 40.

[0070] Taking an adjustable capacitor unit 30 consisting only of a first switching transistor 41 and a second switching transistor 42, with the first switching transistor 41 providing a capacitance value of C1 and the second switching transistor 42 providing a capacitance value of C2 as an example: Based on the capacitance calculation formula, when the first switching transistor 41 and the second switching transistor 42 are on, the adjustable capacitor unit 30 is not capacitive (this can be understood as having a capacitance value of 0); when the first switching transistor 41 is on and the second switching transistor 42 is off, the adjustable capacitor unit 30 has a capacitance value of C2; when the first switching transistor 41 is off and the second switching transistor 42 is on, the adjustable capacitor unit 30 has a capacitance value of C1; when the first switching transistor 41 and the second switching transistor 42 are off, the adjustable capacitor unit 30 is at its minimum capacitance value level, and its capacitance value is (C1*C2) / (C1+C2). That is, in this embodiment, the switching of the four capacitance value levels in the adjustable capacitor unit 30 can be achieved by adjusting the on / off state of the first switching transistor 41 and the second switching transistor 42.

[0071] Therefore, this capacitor adjustment circuit 1 utilizes the characteristic of the switching transistor 40 to adjust the capacitance value in the off state. By controlling each switching transistor 40 to switch on or off, the adjustable capacitor unit 30 has different capacitance values, thereby finely adjusting the overall capacitance value presented by the capacitor adjustment circuit 1. Furthermore, when both the first switching transistor 41 and the second switching transistor 42 are off, the capacitance value of the adjustable capacitor unit 30 can reach a very small state, which is suitable for application scenarios with high sensitivity to capacitance value and requiring fine adjustment, such as the matching circuit in the low noise amplifier (LNA) of the RF front-end module 2.

[0072] Moreover, in the embodiment where the adjustable capacitor unit 30 only includes the first switch 41 and the second switch 42, when both the first switch 41 and the second switch 42 are turned on, the capacitor adjustment circuit 1 can also make the adjustable capacitor unit 30 as a whole non-capacitive, so as to cope with a variety of different application scenarios.

[0073] For example, the switching transistor 40 may be a MOSFET or other circuit structure that can be selectively turned on or off based on the control signal received by the controlled terminal G. This application embodiment does not specifically limit this.

[0074] In some embodiments, the minimum adjustable capacitance value of the adjustable capacitor unit 30 is less than or equal to 50 fF. By controlling the number of switching transistors turned on or off within the adjustable capacitor unit 30, the corresponding minimum capacitance value is made less than or equal to 50 fF. This allows for precise adjustment of the capacitance value within a small range. Specifically, the minimum adjustable capacitance value of the capacitor adjustment circuit 1 is, for example, 20 fF, 30 fF, 40 fF, 50 fF, or other selectable values ​​within this range.

[0075] As explained above, in the embodiment where the adjustable capacitor unit 30 includes only the first switch 41 and the second switch 42, when both the first switch 41 and the second switch 42 are turned off, the adjustable capacitor unit 30 obtains the minimum capacitance value, which is less than or equal to 50fF.

[0076] It should be understood that in the actual application scenario of this capacitor adjustment circuit 1 (for example, the matching circuit in the low-noise amplifier in the RF front-end module 2), the capacitor adjustment circuit 1 needs to provide a small capacitance value. Taking the matching circuit in the low-noise amplifier as an example, providing a capacitance value of less than or equal to 50fF by the capacitor adjustment circuit 1 can effectively improve the circuit performance of the low-noise amplifier.

[0077] like Figure 2 As shown, in some embodiments, the capacitor regulation circuit 1 further includes at least one third switching transistor 43. When the capacitor regulation circuit 1 includes at least two third switching transistors 43, the at least two third switching transistors 43 may be arranged in series, parallel, or a combination of series and parallel connections between the first switching transistor 41 and the second switching transistor 42. For example... Figure 2 In the middle, two third switching transistors 43 are connected in series between the first switching transistor 41 and the second switching transistor 42.

[0078] In one embodiment, the first switch 41, at least one third switch 43 and the second switch 42 are connected in series between the signal input terminal 10 and the signal output terminal 20. When the first switch 41, at least one third switch 43 and the second switch 42 are all turned off, the adjustable capacitor unit 30 is at the minimum capacitance value setting, and the capacitance value of the adjustable capacitor unit 30 is less than or equal to 50fF.

[0079] In some implementations, the capacitance value when the first switch 41 is turned off is 25fF-100fF. Specifically, the capacitance value when the first switch 41 is turned off is, for example, 25fF, 40fF, 60fF, 80fF, 100fF, or other selectable values ​​within the range.

[0080] In some implementations, the capacitance value when the second switch 42 is off is 25fF-100fF. Specifically, the capacitance value when the second switch 42 is off is, for example, 25fF, 40fF, 60fF, 80fF, 100fF, or other selectable values ​​within the range.

[0081] It should be understood that by selecting a first switching transistor 41 and / or a second switching transistor 42 with lower parasitic capacitance, the capacitance value exhibited by the first switching transistor 41 and / or the second switching transistor 42 when disconnected will also be lower. Furthermore, based on the capacitance value limitation of the first switching transistor 41 and the second switching transistor 42, the adjustable capacitor unit 30 can achieve some lower capacitance value levels to meet the needs of scenarios requiring smaller capacitance values.

[0082] It should be further explained that when the aforementioned switch 40 is turned on, the switch 40 can be equivalent to a resistor. At this time, the switch is not capacitive. For example, this is the case for the first switch 41 and the second switch 42.

[0083] Taking a capacitance of 60fF when both the first switch transistor 41 and the second switch transistor 42 are off as an example, when both the first switch transistor 41 and the second switch transistor 42 are on, since both the first switch transistor 41 and the second switch transistor 42 can be considered as resistors, the adjustable capacitor unit 30 is not capacitive at this time; when the first switch transistor 41 is on and the second switch transistor 42 is off, the first switch transistor 41 can be considered as a resistor, and the adjustable capacitor unit 30 has a capacitance of 60fF; when the first switch transistor 41 is off and the second switch transistor 42 is on, the second switch transistor 42 can be considered as a resistor, and the adjustable capacitor unit 30 has a capacitance of 60fF; when both the first switch transistor 41 and the second switch transistor 42 are off, the adjustable capacitor unit 30 is at the minimum capacitance value setting, and has a capacitance of 30.

[0084] In some implementations, the capacitance value when the first switch 41 is turned off is the same as the capacitance value when the second switch 42 is turned off.

[0085] It should be noted that the fact that the first switch transistor 41 and the second switch transistor 42 have the same capacitance value when they are off makes it easier and faster to calculate the overall capacitance value of the adjustable capacitor unit 30, so that the overall capacitance value of the adjustable capacitor unit 30 can be adjusted to the required value when using the adjustable capacitor unit 30. For example, in the scenario where the adjustable capacitor unit 30 only includes the first switch transistor 41 and the second switch transistor 42, the adjustable capacitor unit 30 has the same capacitance value in both cases: the first switch transistor 41 is on and the second switch transistor 42 is off, and the first switch transistor 41 is off and the second switch transistor 42 is on. However, in the case where both the first switch transistor 41 and the second switch transistor 42 are off, the adjustable capacitor unit 30 has exactly half the parasitic capacitance value of the first switch transistor 41 and half the parasitic capacitance value of the second switch transistor 42.

[0086] It should be understood that in some other embodiments, the capacitance values ​​when the first switch 41 is off, the second switch 42, and the third switch 43 are the same, which also makes it easier and faster to calculate the overall capacitance value of the adjustable capacitor unit 30. For example, in some embodiments, the capacitance value when the third switch 43 is off is 25fF-100fF.

[0087] like Figure 2 As shown, in one embodiment, the adjustable capacitor unit 30 also includes two third switches 43 connected in series between the first switch 41 and the second switch 42. When the first switch 41, the second switch 42 and the two third switches 43 are all turned off, the capacitance value of the adjustable capacitor unit 30 is exactly one-quarter of the parasitic capacitance value of the first switch 41 / the second switch 42 / the third switch 43.

[0088] As can be seen, by setting the capacitance value of each switch transistor 40 in the adjustable capacitor unit 30 to the same value when it is turned off, it is easier and faster to calculate the overall capacitance value of the adjustable capacitor unit 30, so that the overall capacitance value of the adjustable capacitor unit 30 can be adjusted to the required value when using the adjustable capacitor unit 30.

[0089] like Figure 3 As shown, in some embodiments, the capacitor adjustment circuit 1 further includes a first parallel unit 50, one end of which is connected to the input terminal of the first switching transistor 41 and the other end is connected to the output terminal of the second switching transistor 42. The capacitance value of the first parallel unit 50 is adjustable.

[0090] Specifically, based on the formula for calculating capacitance, in Figure 3In the capacitor adjustment circuit 1 shown, the overall capacitance value of the capacitor adjustment circuit 1 is the sum of the capacitance value of the adjustable capacitor unit 30 and the capacitance value of the first parallel unit 50. Since the capacitance value of the first parallel unit 50 is adjustable, different capacitance values ​​can be added based on the adjustable capacitor unit 30 by adjusting the capacitance value of the first parallel unit 50, so that the overall capacitance value of the capacitor adjustment circuit 1 can adapt to various capacitance value requirements.

[0091] In some embodiments, the first parallel unit 50 includes at least one fourth switch 51, and the at least one fourth switch 51 is connected between the input terminal of the first switch 41 and the output terminal of the second switch 42; wherein the fourth switch 51 is configured to be turned on or off based on a control signal input from the controlled terminal G of the fourth switch 51, so that the first parallel unit 50 has different capacitance values; and the number of fourth switches 51 is less than or equal to the number of switches 40 in the adjustable capacitor unit 30.

[0092] It should be understood that the principle by which the fourth switch 51 provides different capacitance values ​​by turning on or off is the same as the principle by which the switch 40 in the adjustable capacitor unit 30 provides different capacitance values ​​by turning on or off, and will not be elaborated here.

[0093] It should be noted that, depending on the requirements of the actual application scenario, the capacitance value of the fourth switch 51 in the off state can be greater than, less than or equal to the capacitance value of the first switch 41 in the off state and the capacitance value of the second switch 42 in the off state.

[0094] As one embodiment, the capacitance value of the fourth switch 51 in the off state is smaller than the capacitance value of the first switch 41 in the off state and the capacitance value of the second switch 42 in the off state. It should be understood that since the capacitance value of the capacitor adjustment circuit 1 as a whole is the sum of the capacitance values ​​of the first parallel unit 50 and the adjustable capacitor unit 30 when the first parallel unit 50 is connected in parallel, the capacitance value of the fourth switch 51 in the off state is smaller, which facilitates finer adjustments to the capacitance value provided by the adjustable capacitor unit 30, thereby improving the capacitance adjustment accuracy of the capacitor adjustment circuit 1.

[0095] In some implementations, the capacitance of the fourth switch 51 in the off state is 25fF-100fF. Specifically, the capacitance of the fourth switch 51 when it is off is, for example, 25fF, 40fF, 60fF, 80fF, 100fF, or other selectable values ​​within the range.

[0096] It should be understood that a fourth switch 51 with a lower parasitic capacitance can be selected, resulting in a lower capacitance value when the fourth switch 51 is turned off. Based on the capacitance value limitation of the fourth switch 51, the adjustable capacitor unit 30 can achieve some lower capacitance value levels to meet the needs of scenarios requiring smaller capacitance values.

[0097] In some embodiments, the first parallel unit 50 includes at least two fourth switching transistors 51 connected in series between the signal input terminal 10 and the signal output terminal 20, and the capacitance values ​​of the at least two fourth switching transistors 51 are the same in the off state. It should be noted that having the same capacitance value for the at least two fourth switching transistors 51 in the off state makes it easier and faster to calculate the overall capacitance value of the adjustable capacitor unit 30, so that the overall capacitance value of the adjustable capacitor unit 30 can be adjusted to the required value when using the adjustable capacitor unit 30.

[0098] like Figure 4 As shown, in some embodiments, the capacitor adjustment circuit 1 further includes a second parallel unit 60, which includes at least one first capacitor element 61, and the at least one first capacitor element 61 is connected between the input terminal of the first switching transistor 41 and the output terminal of the second switching transistor 42. In this embodiment, the first capacitor element 61 is directly connected in parallel in the capacitor adjustment circuit 1. The capacitance value in the capacitor adjustment circuit 1 is adjusted by the combined action of the first capacitor element 61 and the adjustable capacitor unit 30, thereby further simplifying the circuit and achieving the purpose of precise adjustment of a smaller capacitance value.

[0099] Specifically, based on the formula for calculating capacitance, in Figure 4 In the capacitor adjustment circuit 1 shown, the overall capacitance value of the capacitor adjustment circuit 1 is the sum of the capacitance value of the adjustable capacitor unit 30 and the capacitance value of the second parallel unit 60. Therefore, a set capacitance value can be added based on the adjustable capacitor unit 30 so that the capacitance value provided by the capacitor adjustment circuit 1 can adapt to different capacitance value requirements.

[0100] In some embodiments, the capacitance value of the first capacitor element 61 is greater than or equal to the capacitance value when the switch transistor 40 is off. It should be understood that setting the capacitance value of the first capacitor element 61 to be higher can be considered as making fine adjustments to the overall capacitance value presented by the capacitor adjustment circuit 1 based on the capacitance value provided by the first capacitor element 61, by controlling the switching of the switch transistor 40 in the adjustable capacitor unit 30, thereby adapting to different ranges of capacitance value requirements.

[0101] In some embodiments, the capacitance of the first capacitor element 61 is greater than or equal to 110 fF. Preferably, the capacitance of the first capacitor element 61 is 400-800 fF. Specifically, the capacitance of the first capacitor element 61 is, for example, 400 fF, 600 fF, 800 fF, or other selectable values ​​within this range.

[0102] For example, in an embodiment where the second parallel unit 60 includes a first capacitor element 61 with a capacitance value of 600fF, and the first switch 41 and the second switch 42 (which may also include a third switch 43) in the adjustable capacitor unit 30 have a capacitance value of 50fF when turned off, the capacitance value provided by the capacitor adjustment circuit 1 is (600+50 / s)fF, where s is the number of switch 40s turned off in the adjustable capacitor unit 30.

[0103] like Figure 5 and Figure 6 As shown, in some embodiments, the capacitor adjustment circuit 1 further includes a preamplifier circuit 70, which is connected between the signal input terminal 10 and the input terminal of the first switch transistor 41. The capacitor value of the preamplifier circuit 70 is adjustable or has a first preset capacitor value, and the first preset capacitor value is different from the capacitor value when the first switch transistor 41 is turned off and the capacitor value when the second switch transistor 42 is turned off.

[0104] like Figure 7 and Figure 8 As shown, in some embodiments, the capacitor adjustment circuit 1 further includes a post-circuit 80, which is connected between the output terminal of the second switch 42 and the signal output terminal 20. The capacitance value of the post-circuit 80 is adjustable or has a second preset capacitance value, which is different from the capacitance value when the first switch 41 is turned off and the capacitance value when the second switch 42 is turned off.

[0105] Specifically, the preamplifier circuit 70 is used to provide the capacitance value and, together with the adjustable capacitor unit 30, adjusts the overall capacitance value of the capacitor adjustment circuit 1. The capacitance value provided by the preamplifier circuit 70 can be a fixed value or an adjustable value, and the same applies to the postamplifier circuit 80.

[0106] like Figure 5 As shown, in some embodiments, the preamplifier circuit 70 includes at least one second capacitor element 71, and the at least one second capacitor element 71 is connected between the signal input terminal 10 and the input terminal of the first switching transistor 41. It should be understood that the second capacitor element 71 is used to provide a fixed capacitance value.

[0107] like Figure 6As shown, in some embodiments, the preamplifier circuit 70 includes at least one fifth switch 72 connected between the signal input terminal 10 and the input terminal of the first switch 41. The fifth switch 72 is configured to be turned on or off based on a control signal input from its controlled terminal G, so that the preamplifier circuit 70 has different capacitance values. It should be understood that the fifth switch 72 is used to provide a capacitance value matching its parasitic capacitance when off, and not to provide a capacitance value when on. Therefore, the overall capacitance value provided by the preamplifier circuit 70 can be adjusted by controlling the on and off states of at least one fifth switch 72 in the preamplifier circuit 70.

[0108] like Figure 7 As shown, in some embodiments, the post-circuit 80 includes at least one third capacitor element 81, and the at least one third capacitor element 81 is connected between the signal input terminal 10 and the input terminal of the first switching transistor 41. It should be understood that the third capacitor element 81 is used to provide a fixed capacitance value.

[0109] like Figure 8 As shown, in some embodiments, the post-amplifier circuit 80 includes at least one sixth switch 82 connected between the output terminal of the second switch 42 and the signal output terminal 20. The sixth switch 82 is configured to be turned on or off based on a control signal input from the controlled terminal G of the sixth switch 82, so that the pre-amplifier circuit 70 has different capacitance values. It should be understood that the sixth switch 82 is used to provide a capacitance value matching its parasitic capacitance when it is off, and to provide no capacitance value when it is on, at which time the capacitance value of the sixth switch 82 is equivalent to 0. Therefore, the overall capacitance value provided by the post-amplifier circuit 80 can be adjusted by controlling the on and off states of at least one sixth switch 82 in the pre-amplifier circuit 70.

[0110] like Figure 9 As shown, in some embodiments, the capacitor adjustment circuit 1 further includes at least two fourth switching transistors 51 connected in series, and the input terminals of the at least two fourth switching transistors 51 are located at the output terminal of the nth switching transistor 40 of the adjustable capacitor unit 30, and the output terminals of the at least two fourth switching transistors 51 are located at the output terminal of the (n+x)th switching transistor 40 of the adjustable capacitor unit 30, where n and x are greater than or equal to 1 and are integers.

[0111] It should be noted that the nth switch 40 in the adjustable capacitor unit 30 refers to the nth switch 40 connected in series in the adjustable capacitor unit 30 along the direction from the side closer to the signal input terminal 10 to the side closer to the signal output terminal 20. The definition of the (n+x)th switch 40 in the adjustable capacitor unit 30 is similar.

[0112] It should also be noted that the input terminals of at least two fourth switching transistors 51 refer to the first input terminal of the first fourth switching transistor 51, moving from the side closest to the signal input terminal 10 towards the side closest to the signal output terminal 20. The output terminals of at least two fourth switching transistors 51 refer to the last output terminal of the last fourth switching transistor 51, moving from the side closest to the signal input terminal 10 towards the side closest to the signal output terminal 20.

[0113] Based on the setting of the fourth switch 51, the capacitance value provided by the capacitor adjustment circuit 1 can be adjusted by controlling the fourth switch 51 and each switch 40 in the adjustable capacitor unit 30 to be turned on and off.

[0114] like Figure 9 As shown, the adjustable capacitor unit 30 includes four series-connected switching transistors 40, and the capacitor adjustment circuit 1 includes two series-connected fourth switching transistors 51. Taking n=2 and x=2 as an example, the input terminals of at least two fourth switching transistors 51 are connected to the output terminal of the second switching transistor 40, and the input terminals of at least two fourth switching transistors 51 are connected to the output terminal of the fourth switching transistor 40. It can also be regarded as: at least two fourth switching transistors 51 are connected in parallel with the third and fourth switching transistors 40 in the adjustable capacitor unit 30.

[0115] For example, in the capacitor adjustment circuit 1 described above, when all the switches 40 in the adjustable capacitor unit 30 are turned on, and all the fourth switches 51 are turned on, the capacitor adjustment circuit 1 as a whole is not capacitive. When the first switch 40 and the second switch 42 are turned on, the larger of the parasitic capacitances of the third switch 40 and the fourth switch 40 is turned off, and the other is turned on, and at least one of the larger of the parasitic capacitances of the two fourth switches 51 is turned off, and the other is turned on, the capacitor adjustment circuit 1 as a whole obtains the maximum capacitance value.

[0116] like Figure 10 As shown, in some embodiments, the capacitor regulation circuit 1 further includes a switching transistor control circuit 90; the switching transistor control circuit 90 is connected to the controlled terminal G of the target switching transistor 40 in the capacitor regulation circuit 1, and is used to output a control signal to the controlled terminal G of the target switching transistor 40 to control the target switching transistor 40 to switch between being on and off, wherein the target switching transistor 40 includes at least a portion of the switching transistors 40 in the capacitor regulation circuit 1.

[0117] For example, the target switch 40 includes a first switch 41 and a second switch 42. Further, the target switch 40 also includes a third switch 43. Even further, the target switch 40 also includes at least one of a fourth switch 51, a fifth switch 72 and a sixth switch 82.

[0118] Specifically, the switching transistor control circuit 90 can control the target switching transistor 40 to switch between on and off states via the output control signal. As one embodiment, the control signal output by the switching transistor control circuit 90 includes an on signal and an off signal. The on signal is used to control the target switching transistor 40 to switch on, and the off signal is used to control the target switching transistor 40 to switch off.

[0119] The specific way in which the capacitor adjustment circuit 1 presents different capacitance values ​​when the target switch 40 is turned on and off can be referred to the aforementioned description of each switch 40, and will not be repeated here.

[0120] In some implementations, the target switch 40 is a field-effect transistor, with its input terminal being the source, its output terminal being the drain, and its controlled terminal G being the gate.

[0121] Specifically, a field-effect transistor, also known as a MOSFET, can be either an N-channel MOSFET or a P-channel MOSFET. When the MOSFET is an N-channel MOSFET, the switching control circuit 90 outputs a high-level signal for the turn-on signal and a low-level signal for the turn-off signal. When the MOSFET is a P-channel MOSFET, the switching control circuit 90 outputs a low-level signal for the turn-on signal and a high-level signal for the turn-off signal.

[0122] In one embodiment, the first switch 41 and the second switch 42 are connected in series between the signal input terminal 10 and the signal output terminal 20. The first switch 41 and the second switch 42 are N-channel field-effect transistors. The source of the first switch 41 is connected to the signal input terminal 10, and the drain of the first switch 41 is connected to the source of the second switch 42. The drain of the second switch 40 is connected to the signal output terminal 20. The switch control circuit 90 is connected to the gate of the first switch 41 and the gate of the second switch 42, respectively, to output control signals to the gate of the first switch 41 and the gate of the second switch 42, respectively.

[0123] like Figure 11 As shown, in a second aspect, embodiments of this application also provide a radio frequency front-end module 2, including a capacitor adjustment circuit 1 as provided in any of the embodiments of this application.

[0124] As one embodiment, the RF front-end module 2 is a component that integrates one or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers into a single module, thereby improving integration and hardware performance, and miniaturizing the size. Specifically, the RF front-end module 2 can be applied to communication devices, which may include electronic devices such as smartphones, tablets, and smartwatches, as well as communication devices such as base stations and NFC (Near Field Communication) devices. The RF front-end module 2 can receive or transmit RF signals through the antenna in the communication device, and the low-noise amplifier is used to amplify the received RF signals. In some implementations, the RF front-end module 2 can support carrier aggregation, dual connectivity, and multiple-input multiple-output (MIMO). As one embodiment, the RF front-end module 2 can be used to transmit and receive 5G signals or millimeter-wave signals.

[0125] Furthermore, the RF front-end module 2 may also include at least one other device such as a control chip, a switching chip, a filter, a duplexer, a surface mount inductor, and a surface mount capacitor. Of course, it may also exclude other discrete devices other than the low-noise amplifier, and this application does not limit this.

[0126] As one embodiment, the RF front-end module 2 includes a receiving circuit, which includes a low-noise amplifier. The low-noise amplifier is equipped with a matching circuit, which provides the capacitance value required for the low-noise amplifier to operate normally, thereby improving the circuit performance of the low-noise amplifier, the receiving circuit, and the RF front-end module 2.

[0127] The capacitor adjustment circuit 1 is set in the matching circuit of the RF front-end module 2 to provide the capacitance value, thereby enabling the matching circuit to provide a sufficiently low capacitance value and improving the adjustment accuracy of the capacitance value provided by the matching circuit. Moreover, the capacitor adjustment circuit 1 can also be non-capacitive as a whole to cope with a variety of different application scenarios.

[0128] In summary, this application provides a capacitor adjustment circuit 1 and an RF front-end module 2. The capacitor adjustment circuit 1 includes: a signal input terminal 10; a signal output terminal 20; and an adjustable capacitor unit 30, including at least two switching transistors 40. The at least two switching transistors 40 include at least a first switching transistor 41 and a second switching transistor 42. The input terminal of the first switching transistor 41 is connected to the signal input terminal 10, the input terminal of the second switching transistor 42 is connected to the output terminal of the first switching transistor 41, and the output terminal of the second switching transistor 42 is connected to the signal output terminal 20. The switching transistors 40 also include a controlled terminal G, which is configured to receive a control signal and control the switching transistors 40 to turn on or off. Each switching transistor 40 can be selectively turned on or off, so that the adjustable capacitor unit 30 has different capacitance values.

[0129] This capacitor adjustment circuit 1 utilizes the characteristic of the switching transistor 40 to adjust the capacitance value when it is off. By controlling each switching transistor 40 to switch on or off, the adjustable capacitor unit 30 has different capacitance values, thereby finely adjusting the overall capacitance value presented by the capacitor adjustment circuit 1. Furthermore, when both the first switching transistor 41 and the second switching transistor 42 are off, the capacitance value of the adjustable capacitor unit 30 can reach a very small state, which is suitable for applications with high sensitivity to capacitance values ​​and requiring fine adjustment, such as the matching circuit in the low noise amplifier (LNA) of the RF front-end module. Moreover, in embodiments where the adjustable capacitor unit 30 only includes the first switching transistor 41 and the second switching transistor 42, when both the first switching transistor 41 and the second switching transistor 42 are on, this capacitor adjustment circuit 1 can also make the adjustable capacitor unit 30 as a whole non-capacitive, in order to cope with a variety of different application scenarios.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in this application. These modifications or substitutions should all be covered within the scope of protection of this application, and the scope of protection of this application should be determined by the scope of the claims.

[0131] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate medium; or a connection within two elements. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances. As used in this specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms. It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system.

Claims

1. A capacitor regulation circuit, characterized in that, The capacitor regulation circuit includes at least: Signal input terminal; Signal output terminal; An adjustable capacitor unit includes at least two switching transistors, wherein the at least two switching transistors include at least a first switching transistor and a second switching transistor, the input terminal of the first switching transistor is connected to the signal input terminal, the input terminal of the second switching transistor is connected to the output terminal of the first switching transistor, and the output terminal of the second switching transistor is connected to the signal output terminal. The switching transistor also includes a controlled terminal, which is configured to receive a control signal and control the switching transistor to turn on or off. Each switching transistor can be selectively turned on or off so that the adjustable capacitor unit has different capacitance values.

2. The capacitor regulation circuit as described in claim 1, characterized in that, The adjustable capacitor unit can adjust to a minimum capacitance value of less than or equal to 50fF.

3. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitor regulation circuit also includes at least one third switching transistor; The first switch, the at least one third switch, and the second switch are connected in series between the signal input terminal and the signal output terminal, and when the first switch, the at least one third switch, and the second switch are all turned off, the capacitance value of the adjustable capacitor unit is less than or equal to 50fF.

4. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitance of the first switch in the off state is 25fF-100fF; And / or, the capacitance value when the second switch is turned off is 25fF-100fF; And / or, the capacitance value when the first switch is turned off is the same as the capacitance value when the second switch is turned off.

5. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitor adjustment circuit further includes a first parallel unit, one end of which is connected to the input terminal of the first switching transistor and the other end of which is connected to the output terminal of the second switching transistor. The capacitance value of the first parallel unit is adjustable.

6. The capacitor regulation circuit as described in claim 5, characterized in that, The first parallel unit includes at least one fourth switch, and the at least one fourth switch is connected between the input terminal of the first switch and the output terminal of the second switch. The fourth switch is configured to be turned on or off based on a control signal input from the controlled terminal of the fourth switch, so that the first parallel unit has different capacitance values. Furthermore, the number of the fourth switching transistors is less than or equal to the number of switching transistors within the adjustable capacitor unit.

7. The capacitor regulation circuit as described in claim 6, characterized in that, The capacitance value of the fourth switch in the off state is less than the capacitance value of the first switch in the off state and the capacitance value of the second switch in the off state; and / or, The capacitance of the fourth switch in the off state is 25fF-100fF; and / or, The first parallel unit includes at least two of the fourth switching transistors, which are connected in series between the signal input terminal and the signal output terminal, and the capacitance values ​​of the at least two fourth switching transistors are the same in the off state.

8. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitor regulation circuit further includes a second parallel unit, which includes at least one first capacitor element, and the at least one first capacitor element is connected between the input terminal of the first switch and the output terminal of the second switch.

9. The capacitor regulation circuit as described in claim 8, characterized in that, The capacitance value of the first capacitor element is greater than or equal to the capacitance value when the switch is turned off.

10. The capacitor regulation circuit as described in claim 8, characterized in that, The capacitance of the first capacitor element is greater than or equal to 110fF.

11. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitor adjustment circuit further includes a preamplifier circuit connected between the signal input terminal and the input terminal of the first switching transistor. The capacitor value of the preamplifier circuit is adjustable or has a first preset capacitor value, and this first preset capacitor value differs from the capacitor value when the first switching transistor is off and the capacitor value when the second switching transistor is off; and / or, The capacitor adjustment circuit further includes a post-circuit circuit, which is connected between the output terminal of the second switch and the signal output terminal. The capacitor value of the post-circuit circuit is adjustable or has a second preset capacitor value, and the second preset capacitor value is different from the capacitor value when the first switch is turned off and the capacitor value when the second switch is turned off.

12. The capacitor regulation circuit as described in claim 11, characterized in that, The preamplifier circuit includes at least one fifth switch connected between the signal input terminal and the input terminal of the first switch. The fifth switch is configured to turn on or off based on a control signal input from its controlled terminal, such that the preamplifier circuit has different capacitance values; and / or, The post-amplifier circuit includes at least one sixth switch connected between the output terminal of the second switch and the signal output terminal. The sixth switch is configured to be turned on or off based on a control signal input from the controlled terminal of the sixth switch, so that the pre-amplifier circuit has different capacitance values. And / or, The preamplifier circuit includes at least one second capacitor element, and the at least one second capacitor element is connected between the signal input terminal and the input terminal of the first switching transistor; and / or, The post-processor circuit includes at least one third capacitor element, and the at least one third capacitor element is connected between the signal input terminal and the input terminal of the first switching transistor.

13. The capacitor regulation circuit as described in claim 1, characterized in that, The capacitor adjustment circuit further includes at least two sixth switching transistors connected in series, and the input terminals of the at least two sixth switching transistors are set at the output terminal of the nth switching transistor of the adjustable capacitor unit, and the output terminals of the at least two sixth switching transistors are set at the output terminal of the (n+x)th switching transistor of the adjustable capacitor unit, where n and x are greater than or equal to 1 and are integers.

14. The capacitor regulation circuit according to any one of claims 1-13, characterized in that, The capacitor adjustment circuit also includes a switching transistor control circuit; The switching transistor control circuit is connected to the controlled terminal of the target switching transistor in the capacitor adjustment circuit, and is used to output a control signal to the controlled terminal of the target switching transistor to control the target switching transistor to switch between being on and off. The target switching transistor includes at least a portion of the switching transistors in the capacitor regulation circuit.

15. The capacitor regulation circuit as described in claim 14, characterized in that, The target switch is a field-effect transistor, with its input terminal being the source, its output terminal being the drain, and its controlled terminal being the gate.

16. A radio frequency front-end module, characterized in that, Includes the capacitor regulation circuit as described in any one of claims 1-15.

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