Communication circuit and safety barrier

Abstract

The present disclosure provides a communication circuit and a safety barrier, and relates to the technical field of circuits. The communication circuit comprises a first voltage control signal generation circuit, a first switch circuit and a shutdown circuit. The first voltage control signal generation circuit is configured to generate and output a first voltage control signal; the first input end and the second input end of the first switch circuit are configured to receive a first voltage signal and the first voltage control signal respectively, and the output end of the first switch circuit is connected to the input end of an external circuit. The first end and the second end of the shutdown circuit are configured to receive the first voltage signal, and the third end of the shutdown circuit is connected to the control end of the first switch circuit.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and more specifically, to a communication circuit and a safety barrier. Background Technology

[0002] In real-world scenarios, when manufacturers launch their own fire alarm systems, they utilize power line carrier communication as the primary communication method to share communication and power supply lines, thereby reducing construction costs. The application layer protocol, however, employs a special proprietary protocol for communication. Therefore, how to better parse this communication protocol becomes a technical problem that needs to be solved. Summary of the Invention

[0003] This disclosure provides a communication circuit, including: a first voltage control signal generation circuit for generating and outputting a first voltage control signal; a first switching circuit, wherein a first input terminal and a second input terminal of the first switching circuit are respectively used to receive the first voltage signal and the first voltage control signal, and the output terminal of the first switching circuit is connected to the input terminal of a peripheral circuit; and a shutdown circuit, wherein a first terminal and a second terminal of the shutdown circuit are used to receive the first voltage signal, and a third terminal of the shutdown circuit is connected to the control terminal of the first switching circuit.

[0004] This disclosure provides a safety barrier, comprising: a non-intrinsically safe side circuit; an intrinsically safe side circuit, the intrinsically safe side circuit including a communication circuit as described in any embodiment of this disclosure; and an isolation circuit located between the non-intrinsically safe side circuit and the intrinsically safe side circuit. Attached Figure Description

[0005] Figure 1 A schematic diagram of the structure of a communication circuit according to an embodiment of the present disclosure is shown.

[0006] Figure 2 A schematic diagram of a second switching circuit and a discharge circuit according to an embodiment of this disclosure is shown.

[0007] Figure 3 A schematic diagram of another discharge circuit in an embodiment of this disclosure is shown.

[0008] Figure 4 A schematic diagram of another discharge circuit in an embodiment of this disclosure is shown.

[0009] Figure 5 A schematic diagram of another discharge circuit in an embodiment of this disclosure is shown.

[0010] Figure 6 A schematic diagram of another discharge circuit in an embodiment of this disclosure is shown.

[0011] Figure 7A schematic diagram of another discharge circuit in an embodiment of this disclosure is shown.

[0012] Figure 8 The diagram shows a structural schematic of a third switching circuit and an on / off control circuit according to an embodiment of the present disclosure.

[0013] Figure 9 A schematic diagram of another communication circuit in an embodiment of this disclosure is shown.

[0014] Figure 10 A schematic diagram of a current delay detection circuit according to an embodiment of this disclosure is shown.

[0015] Figure 11 A schematic diagram of the structure of another communication circuit in an embodiment of this disclosure is shown.

[0016] Figure 12 A schematic diagram of a current threshold detection circuit according to an embodiment of this disclosure is shown.

[0017] Figure 13 A schematic diagram of a short-circuit detection circuit according to an embodiment of this disclosure is shown.

[0018] Figure 14 A schematic diagram of the structure of a safety barrier according to an embodiment of the present disclosure is shown.

[0019] Figure 15 A schematic diagram of a power supply circuit according to an embodiment of this disclosure is shown.

[0020] Figure 16 The diagram shows a waveform of a communication protocol signal according to an embodiment of this disclosure.

[0021] Figure 17 A schematic diagram of a fire alarm system according to an embodiment of this disclosure is shown. Detailed Implementation

[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0023] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. Otherwise, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail.

[0024] like Figure 1 As shown, the communication circuit 100 provided in this embodiment includes a first switching circuit 110 and a shutdown circuit 120.

[0025] The first input terminal and the second input terminal of the first switching circuit 110 are respectively used to receive a first voltage signal (e.g., VEE = 20V) and a first voltage control signal Control 1. The output terminal of the first switching circuit 110 is connected to the input terminal N1 of the peripheral circuit. Exemplarily, in this embodiment of the present disclosure, a 20V first voltage signal is provided to the peripheral circuit through Control 1.

[0026] The first and second terminals of the shutdown circuit 120 are used to receive a first voltage signal (e.g., VEE = 20V), and the third terminal of the shutdown circuit 120 is connected to the control terminal of the first switching circuit 110.

[0027] For example, when the communication circuit 100 provided in this embodiment of the present disclosure is applied to an intrinsic safety barrier, the communication circuit 100 may be located on the intrinsically safe side of the safety barrier.

[0028] For example, such as Figure 1 As shown, the first switching circuit 110 includes: a first transistor Q112, the base of which is used to receive a first voltage control signal Control 1, the emitter of which is used to receive a ground voltage GND (e.g., 0V), and the collector of which is connected to the first and third terminals of the turn-off circuit 120; and a first PMOS transistor Q11, the control terminal (e.g., gate) of which is connected to the collector of the first transistor Q112, the first terminal (e.g., source or drain) of which is connected to the second terminal of the turn-off circuit 120, and the second terminal (e.g., drain or source) of which is connected to the output terminal of the first switching circuit 110. Figure 1 Node N1 shown in the diagram.

[0029] For example, the first transistor Q112 includes an NPN transistor.

[0030] For example, the first switching circuit 110 further includes one or more of the following: a resistor R141, the first end of which is used to receive a first voltage control signal Control 1, and the second end of which is connected to the base of the first transistor Q12; a resistor R146, the first end of which is connected to the base of the first transistor Q112, and the second end of which is used to receive the ground voltage GND.

[0031] For example, when the first voltage control signal Control 1 is at a first level (e.g., high level), the first switching circuit 110 is turned on, for example, Q112 and Q11 are turned on to output the first voltage signal VEE; when the first voltage control signal Control 1 is at a second level (e.g., low level), the first switching circuit 110 is turned off, for example, Q112 and Q11 are turned off to prevent the first voltage signal VEE from being output. By controlling the duration of the high and low levels of the first voltage control signal Control 1, the first voltage signal VEE of the required duration can be output for use in parsing the communication protocol.

[0032] The embodiments disclosed herein achieve a slow turn-on of the first voltage signal VEE, for example, 20V, through the cooperation of Q112 and Q11.

[0033] It is understandable that the circuit structure of the first switching circuit 110 is not limited to... Figure 1 As illustrated in the example, it only needs to be able to output the first voltage signal VEE of the required duration according to the high and low levels of the first voltage control signal Control 1.

[0034] For example, such as Figure 1 As shown, the shutdown circuit 120 includes a second transistor Q12, the base and collector of which are used to receive the first voltage signal, and the emitter of the second transistor Q12 is connected to the control terminal of the first PMOS transistor Q11.

[0035] For example, the second transistor Q12 includes an NPN transistor.

[0036] For example, the shutdown circuit 120 further includes: a first resistor R124, the first end of which is connected to the collector of the second transistor Q12, and the second end of which is connected to the base of the second transistor Q12; and / or, a second resistor R136, the first end of which is connected to the base of the second transistor Q12, and the second end of which is connected to the collector of the first transistor Q112.

[0037] For example, the first terminal of the first resistor R124 and the collector of the second transistor Q12 are both connected to node N5, and the first voltage signal VEE is received through node N5.

[0038] For example, the shutdown circuit 120 further includes one or more of the following: a resistor R140, the first end of which is connected to the emitter of the second transistor Q12, and the second end of which is connected to the collector of the first transistor Q112; a Zener diode Z115, the cathode of which is connected to the collector of the second transistor Q12, and the anode of which is connected to the emitter of the second transistor Q12, for the purpose of protecting the second transistor Q12; and a resistor R133, the first end of which is connected to the collector of the second transistor Q12, and the second end of which is connected to the emitter of the second transistor Q12.

[0039] In this embodiment, Q11 uses a PMOS transistor to achieve slow turn-on of the first voltage signal VEE. Considering the large integrated capacitance of the PMOS transistor and its slow turn-off, the falling edge of the first voltage signal VEE (e.g., 20V) is not steep enough. Therefore, a turn-off circuit 120 is introduced to achieve fast turn-off of the first voltage signal VEE. When a low level is applied to the first voltage control signal Control 1, Q112 turns off and Q12 turns on, causing Q11 to turn off quickly, thereby quickly pulling the first voltage signal VEE low at node N1. Exemplarily, the fast turn-off of Q11 is achieved through R124, R136, and Q12.

[0040] The embodiments disclosed herein achieve the function of slow opening and fast closing of the first voltage signal through the first switching circuit and the turn-off circuit, ensuring reasonable timing in the protocol level and avoiding hardware conflicts.

[0041] For example, in the above Figure 1 On the basis of, such as Figure 2 As shown, the communication circuit 100 further includes: a second switching circuit 130, the first input terminal and the second input terminal of the second switching circuit 130 being used to receive a second voltage signal (the magnitude of which can be set according to actual needs, but this disclosure is not limited thereto) and a second voltage control signal Control 2, respectively; the output terminal of the second switching circuit 130 being connected to the input terminal (node ​​N1) of the peripheral circuit; and a bleeder circuit 140, the first terminal of the bleeder circuit 140 being used to receive the second voltage signal, and the second terminal of the bleeder circuit 140 being connected to the output terminal (node ​​N1) of the first switching circuit 110.

[0042] For example, the second switching circuit 130 includes: a second transistor Q114, the base of which is used to receive a second voltage control signal Control 2, the collector of which is used to receive a second voltage signal, and the emitter of which is used to receive a ground voltage GND; and a second PMOS transistor Q113, the control terminal (e.g., gate) of which is connected to the collector of the second transistor Q114 and the first terminal of the discharge circuit 140, the first terminal (e.g., source or drain) of which is used to receive the second voltage signal, and the second terminal (e.g., drain or source) of which is connected to the output terminal (node ​​N1) of the first switching circuit 110.

[0043] For example, the second transistor Q114 includes an NPN transistor.

[0044] For example, the second switching circuit 130 further includes at least one of the following: a resistor R156, the first terminal of which is used to receive a second voltage control signal Control. 2. The second terminal of resistor R156 is connected to the base of the second transistor Q114; the first terminal of resistor R159 is connected to the base of the second transistor Q114, and the second terminal of resistor R159 is used to receive the ground voltage; the cathode of diode D111 is connected to the collector of the second transistor Q114, and the anode of diode D111 is connected to the control terminal of the second PMOS transistor Q113; the anode of Zener diode Z116 is connected to the control terminal of the second PMOS transistor Q113, and the cathode of Zener diode Z116 is connected to the first terminal of the second PMOS transistor Q113; the anode of diode D18 is used to receive the second voltage signal, and the cathode of diode D18 is connected to the first terminal of the second PMOS transistor Q113; the anode of diode D115 is connected to the second terminal of the second PMOS transistor Q113, and the cathode of diode D115 is connected to node N1.

[0045] For example, the collector of the second transistor Q114 and the cathode of the diode D111 are both connected to node N4.

[0046] For example, when the second voltage control signal Control 2 is at a first level (e.g., high level), the second switching circuit 130 is turned on, for example, Q114 and Q113 are turned on to output a third voltage signal (e.g., 6V); when the second voltage control signal Control 2 is at a second level (e.g., low level), the second switching circuit 130 is turned off, for example, Q114 and Q113 are turned off to prevent the third voltage signal from being output. By controlling the duration of the high and low levels of the second voltage control signal Control 2, a third voltage signal of the required duration, such as 6V, can be output for use in parsing the communication protocol.

[0047] This embodiment of the disclosure achieves slow activation of a third voltage signal, such as 6V, through the cooperation of Q114 and Q113.

[0048] It is understandable that the circuit structure of the second switching circuit 130 is not limited to... Figure 2 As illustrated in the example, it only needs to be able to output a third voltage signal of the required duration according to the high or low level control of the second voltage control signal Control 2.

[0049] For example, the discharge circuit 140 includes: a first Zener diode Z110, the anode of the first Zener diode Z110 is connected to the first terminal of the discharge circuit 140 (connected to the aforementioned node N4), and the cathode of the first Zener diode Z110 is connected to the second terminal of the discharge circuit 140 (connected to the aforementioned node N1); a third resistor R155, the first terminal of the third resistor R155 is connected to either the cathode or anode of the first Zener diode Z110, and the second terminal of the third resistor R155 is connected to either the second terminal or the first terminal of the discharge circuit 140; and a first diode D113, the cathode of the first diode D113 is connected to the first terminal of the discharge circuit 140, and the anode of the first diode D113 is connected to the second terminal of the discharge circuit 140.

[0050] For example, the discharge circuit 140 further includes a resistor R157, the first end of which is connected to node N1, and the second end of which is connected to node N2.

[0051] For example, rapid discharge is achieved by Z110, R155, D113 and R157 when the first voltage signal, for example 20V, is switched to the third voltage signal, for example 6V, and / or when the first voltage signal, for example 20V, is switched to the fourth voltage signal, for example 0V.

[0052] For example, such as Figure 2As shown, the communication circuit 100 further includes: a first sampling resistor R149, the first terminal Vi+ of the first sampling resistor R149 is connected to the second terminal of the second PMOS transistor Q113, and the second terminal Vi- of the first sampling resistor R149 is connected to the input terminal of the peripheral circuit (connected to node N1).

[0053] For example, the second terminal Vi- of the first sampling resistor R149 is connected to the positive terminal of the diode D115.

[0054] In this embodiment of the present disclosure, the first sampling resistor R149 is used to detect the pull code current returned by the peripheral circuit when the second switching circuit 130 outputs a third voltage signal, such as 6V, to the peripheral circuit.

[0055] For example, such as Figure 2 As shown, the discharge circuit 140 includes: a first Zener diode Z110, the anode of which is connected to the collector of a second transistor Q114; a third resistor R155, the first terminal of which is connected to the cathode of the first Zener diode Z110; and a first diode D113, the cathode of which is connected to the second terminal of the third resistor R155, and the anode of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0056] For example, such as Figure 3 As shown, the discharge circuit 140 includes: a first diode D113, the cathode of which is connected to the collector of a second transistor Q114; a first Zener diode Z110, the anode of which is connected to the anode of the first diode D113; and a third resistor R155, the first terminal of which is connected to the cathode of the first Zener diode Z110, and the second terminal of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0057] For example, such as Figure 4 As shown, the discharge circuit 140 includes: a first diode D113, the cathode of which is connected to the collector of a second transistor Q114; a third resistor R155, the first terminal of which is connected to the anode of the first diode D113; and a first Zener diode Z110, the anode of which is connected to the second terminal of the third resistor R155, and the cathode of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0058] For example, such as Figure 5As shown, the discharge circuit 140 includes: a third resistor R155, the first end of which is connected to the collector of the second transistor Q114; a first diode D113, the cathode of which is connected to the second end of the third resistor R155; and a first Zener diode Z110, the anode of which is connected to the anode of the first diode D113, and the cathode of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0059] For example, such as Figure 6 As shown, the discharge circuit 140 includes: a third resistor R155, the first end of which is connected to the collector of the second transistor Q114; a first Zener diode Z110, the anode of which is connected to the second end of the third resistor R155; and a first diode D113, the cathode of which is connected to the cathode of the first Zener diode Z110, and the anode of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0060] For example, such as Figure 7 As shown, the discharge circuit 140 includes: a first Zener diode Z110, the anode of which is connected to the collector of the second transistor Q114; a first diode D113, the cathode of which is connected to the cathode of the first Zener diode Z110; and a third resistor R155, the first terminal of which is connected to the anode of the first diode D113, and the second terminal of which is connected to the output terminal of the first switching circuit 110 (connected to node N1).

[0061] The structure of the discharge circuit in the embodiments of this disclosure is not limited to the examples above. Other suitable circuit structures that can quickly pull down the output of 20V to the peripheral circuit to 6V can also be used.

[0062] For example, such as Figure 8 As shown, the communication circuit 100 further includes: a third switching circuit 150, the input terminal of which is used to receive a third voltage control signal Control 3, and the output terminal of the third switching circuit 150 is connected to the output terminal of the first switching circuit 110 (connected to node N1); and an on / off control circuit 160, which is connected to the third switching circuit 150.

[0063] For example, the third switching circuit 150 includes: an eleventh resistor R177, the first end of which is used to receive a third voltage control signal Control 3, and the second end of which is connected to the on / off control circuit 160; a second NMOS transistor Q115, the control terminal (e.g., gate) of which is connected to the on / off control circuit 160, the first end (e.g., source or drain) of which is connected to the output terminal of the first switching circuit 110 (connected to node N1), and the second end (e.g., drain or source) of which is used to receive the ground voltage GND.

[0064] For example, when the third voltage control signal Control 3 is at a first level (e.g., high level), the third switching circuit 150 is turned on, for example, Q115 is turned on, to output a fourth voltage signal (e.g., 0V); when the third voltage control signal Control 3 is at a second level (e.g., low level), the third switching circuit 150 is turned off, for example, Q115 is turned off, to prevent the fourth voltage signal from being output. By controlling the duration of the high and low levels of the third voltage control signal Control 3, a fourth voltage signal, such as 0V, of the required duration can be output for use in parsing the communication protocol.

[0065] This embodiment of the disclosure uses Q115 to achieve slow activation of a fourth voltage signal, such as 0V.

[0066] It is understandable that the circuit structure of the third switching circuit 150 is not limited to... Figure 8 The example illustrates that it only needs to output a fourth voltage signal of the required duration according to the high or low level control of the third voltage control signal Control 3.

[0067] For example, the second terminal of the second NMOS transistor Q115 is also connected to node N3.

[0068] For example, the turn-on / turn-off control circuit 160 includes: a third diode D114, the cathode of which is connected to the second terminal of the eleventh resistor R177, and the anode of which is connected to the control terminal of the second NMOS transistor Q115; a twelfth resistor R160, the first terminal of which is connected to the cathode of the third diode D114, and the second terminal of which is connected to the anode of the third diode D114; and a second capacitor C119, the first terminal of which is connected to the control terminal of the second NMOS transistor Q115, and the second terminal of which is connected to the second terminal of the second NMOS transistor Q115.

[0069] For example, the turn-on / turn-off control circuit 160 further includes a thirteenth resistor R161, which is connected in parallel with the second capacitor C119.

[0070] The embodiments disclosed herein utilize D114, R160, and C119 to achieve slow on and fast off of a fourth voltage signal, such as 0V.

[0071] The communication circuit provided in this embodiment achieves slow on-time and fast off-time of the parsed output first voltage signal, third voltage signal and fourth voltage signal through the above circuit structure, thereby ensuring reasonable timing in the protocol level and avoiding hardware conflicts.

[0072] like Figure 9 As shown, the communication circuit provided in this embodiment may further include: a first current detection chip IC3, wherein the positive input terminal VIN+ of the first current detection chip IC3 is connected to the first terminal Vi+ of the first sampling resistor R149, and the negative input terminal VIN- of the first current detection chip IC3 is connected to the second terminal Vi- of the first sampling resistor R149.

[0073] For example, combined Figure 2 and Figure 9 Through the first sampling resistor R149 and the first current detection chip IC3, when the pull code current of the peripheral circuit flows through the first sampling resistor R149 under the third voltage signal, such as 6V, a voltage drop will be generated across the first sampling resistor R149, which will be detected by the first current detection chip IC3, and then the voltage signal ILM will be output through the output terminal OUT of the first current detection chip IC3.

[0074] For example, such as Figure 9As shown, the communication circuit may further include at least one of the following: a resistor R166, the first terminal of which is used to receive the ground voltage GND, and the second terminal of which is connected to the first terminal Vi+ of the first sampling resistor R149; a resistor R168, the first terminal of which is used to receive the ground voltage GND, and the second terminal of which is connected to the second terminal Vi- of the first sampling resistor R149; and a capacitor C149, the first terminal of which is used to receive the ground voltage GND, and the second terminal of which is connected to the power supply terminal VC of the first current detection chip IC3. C; Resistor R147, the first end of resistor R147 is used to receive the ground voltage GND and is connected to the ground terminal GND of the first current detection chip IC3, and the second end of resistor R147 is connected to the output terminal OUT of the first current detection chip IC3; Resistor R130, the first end of resistor R130 is connected to the output terminal OUT of the first current detection chip IC3, and the second end of resistor R130 is used to output the voltage signal ILM; Diode D119, the anode of diode D119 is connected to the second end of resistor R130, and the cathode of diode D119 is used to receive the power supply voltage VCC.

[0075] For example, such as Figure 9 As shown, the second terminal of capacitor C149 and the power supply terminal VCC of the first current detection chip IC3 are both used to receive the second voltage signal. For example, the power supply voltage VCC = 3V, but this disclosure is not limited thereto.

[0076] like Figure 10 As shown, the communication circuit provided in this embodiment may further include a current delay detection circuit 180, which is used to delay the detection of the pull code current input to the peripheral circuit when outputting a third voltage signal, such as 6V, to the peripheral circuit, that is, to delay the detection of the voltage drop between the first terminal Vi+ and the second terminal Vi- of the first sampling resistor R149.

[0077] For example, the input terminal of the current delay detection circuit 180 is used to receive the second voltage control signal Control2, the first terminal of the current delay detection circuit 180 is connected to the first terminal Vi+ of the first sampling resistor R149, and the second terminal of the current delay detection circuit 180 is connected to the second terminal Vi- of the first sampling resistor R149.

[0078] For example, such as Figure 10As shown, the current delay detection circuit 180 includes: a first capacitor C1116, the first terminal of which is used to receive a second voltage control signal Control 2; a fourth transistor Q1110, the base of which is connected to the second terminal of the first capacitor C1116, and the emitter of which is used to receive a ground voltage; and a third PMOS transistor Q131, the control terminal of which is connected to the collector of the fourth transistor Q1110, the first terminal of which is connected to the first terminal Vi+ of the first sampling resistor R149, and the second terminal of which is connected to the second terminal Vi- of the first sampling resistor R149.

[0079] For example, the fourth transistor Q1110 includes an NPN transistor.

[0080] In this embodiment of the disclosure, when the communication circuit misinterprets the communication protocol, or when the communication circuit is unstable, a short-term voltage switch may occur, such as switching from a first voltage signal (e.g., 20V) to a third voltage signal (e.g., 6V), or from a fourth voltage signal (e.g., 0V) to 6V. This causes Control 2 to output a short-term high level. However, this short-term high level may not be the 6V voltage actually desired by the communication protocol. To solve this problem, this embodiment of the disclosure introduces a current delay detection circuit 180. If Control 2 briefly switches from a low level to a high level, a high level will be input through C1116, causing Q1110 and Q131 to conduct. Since the resistance of Q1110 and Q131 is very small when they are conducting, close to zero, this is equivalent to short-circuiting the first sampling resistor R149. The first current detection chip IC3 cannot detect this erroneous pull-code current, thus preventing protocol misinterpretation. If it is the required third voltage signal, after stabilization, C1116 outputs a low level, thereby turning off Q1110 and Q131, so that the pull code current returned by the peripheral circuit can flow normally through the first sampling circuit R149 and be detected normally by the first current detection chip IC3.

[0081] The current delay detection circuit in this embodiment is equivalent to connecting a switch in parallel across R149. When switching to 6V, it delays for a period of time, such as tens of μs, to close the switch so that the first current detection chip cannot detect the pull code current. After stabilization, the switch is opened, thus enabling normal detection of the pull code current.

[0082] For example, the current delay detection circuit 180 further includes at least one of the following: a second diode D1112, the cathode of which is connected to the second terminal of the first capacitor C1116; a fourth resistor R1123, the first terminal of which is connected to the anode of the second diode D1112, and the second terminal of which is used to receive ground voltage; a fifth resistor R1124, the first terminal of which is connected to the second terminal of the fourth resistor R1123; and a sixth resistor R1125, the first terminal of which is connected to the second terminal of the first capacitor C1116, and the second terminal of which is connected to the second terminal of the fifth resistor R1124 and the base of the fourth transistor Q1110.

[0083] For example, the current delay detection circuit 180 further includes at least one of the following: a seventh resistor R1122, the first end of which is connected to the collector of the fourth transistor Q1110, and the second end of which is connected to the first terminal Vi+ of the first sampling resistor R149; a second Zener diode Z1110, the anode of which is connected to the collector of the fourth transistor Q1110, and the cathode of which is connected to the second end of the seventh resistor R1122.

[0084] In some embodiments, due to safety requirements, the intrinsically safe side needs to limit power, resulting in particularly high resistance at the output, such as hundreds of ohms. When using long lines on the intrinsically safe side, coupling capacitors exist. These capacitors can cause IC3 to detect current flow when switching from 20V to 6V, even though the peripheral circuit may not actually return the pull-code current or may not even be connected at this time. This leads to an incorrect triggering of the pull-code current return to the controller. To avoid this problem, a current delay detection circuit can be used to pause the current flow to IC3 before restarting, preventing false triggering and thus improving the performance and accuracy of long lines.

[0085] For example, the communication circuit provided in this embodiment of the present disclosure implements 6V line delay current detection through C1116, D1112, R1123, R1124, R1125, R1122, Z1110, Q1110, and Q131. This achieves peripheral response stability in harsh environments such as long-distance lines.

[0086] like Figure 11 As shown, the communication circuit provided in this embodiment may further include: a first voltage control signal generation circuit 190, used to generate and output a first voltage control signal Control 1.

[0087] For example, such as Figure 11As shown, the first voltage control signal generation circuit 190 includes a second inverter U12A. The input terminal of the second inverter U12A is connected to the input terminal of the first voltage control signal generation circuit 190, and the output terminal of the second inverter U12A is connected to the output terminal of the first voltage control signal generation circuit 190. The inverter in this embodiment can also be called a NOT gate. This embodiment can use a NOT gate to implement the parsing of the communication protocol.

[0088] Continue to refer to Figure 11 The communication circuit provided in this embodiment may further include: a second voltage control signal generation circuit 210, which generates and outputs a second voltage control signal Control 2 through an output terminal.

[0089] For example, the second voltage control signal generation circuit 210 includes: a first inverter U12B, the input terminal of which is connected to the first input terminal of the second voltage control signal generation circuit 210; and a first AND gate U14A, the first input terminal of which is connected to the output terminal of the first inverter U12B, the second input terminal of which is connected to the second input terminal of the second voltage control signal generation circuit 210, and the output terminal of which is connected to the output terminal of the second voltage control signal generation circuit 210. Embodiments of this disclosure can implement communication protocol parsing using NOT gates and AND gates.

[0090] For example, such as Figure 11 As shown, the communication circuit provided in this embodiment may further include: a third voltage control signal generation circuit 220, which generates a third voltage control signal Control 3 and outputs it through an output terminal.

[0091] For example, the third voltage control signal generation circuit 220 includes: a second AND gate U14B, the first input terminal of the second AND gate U14B is connected to the first input terminal of the third voltage control signal generation circuit 220, the second input terminal of the second AND gate U14B is connected to the second input terminal of the second voltage control signal generation circuit 210, and the output terminal of the second AND gate U14B is connected to the output terminal of the third voltage control signal generation circuit 220.

[0092] For example, by alternately maintaining the high and low levels of the first voltage control signal Control 1, the second voltage control signal Control 2, and the third voltage control signal Control 3 for different durations, the output of a first voltage signal (e.g., 20V), a third voltage signal (e.g., 6V), and a fourth voltage signal (e.g., 0V) for corresponding durations can be controlled to achieve communication protocol parsing. When the communication circuit is located on the intrinsically safe side, the communication circuit provided in this embodiment can achieve communication protocol level parsing on the intrinsically safe side. For example, this embodiment uses NOT gates and AND gates to achieve communication protocol level parsing on the intrinsically safe side, that is, communication protocol parsing can be implemented purely in hardware, thereby improving the reliability and response speed of communication protocol parsing.

[0093] It should be noted that the specific circuit structures of the first to third voltage control signal generation circuits provided in the embodiments of this disclosure are not limited to those described above. Figure 11 As shown, as long as the number of voltage signals to be output to the peripheral circuit as required by the communication protocol can be achieved (here, three voltage signals, namely 20V, 6V and 0V, are taken as examples, but this disclosure is not limited to this and can be set according to the actual scenario), and the duration of the high and low levels of the voltage signals can be achieved, then they all fall within the protection scope of this disclosure.

[0094] By incorporating a first switching circuit, a turn-off circuit, a second switching circuit, a discharge circuit, a third switching circuit, and an on / off control circuit, this embodiment achieves slow on-time and rapid off-time when outputting the first, third, and fourth voltage signals to the peripheral circuit. This results in a steeper falling edge on the parsed communication protocol signal waveform, resembling a square wave, indicating a better parsed communication protocol, a more stable waveform, and the avoidance of conflicts in the hardware circuitry for parsing the communication protocol. For example, if the waveform control is unstable, 6V and 20V might be simultaneously output to the peripheral circuit, generating an abnormally large current. This situation is unacceptable for intrinsically safe circuits with high safety requirements.

[0095] For example, such as Figure 11 As shown, the communication circuit provided in this embodiment further includes a voltage sustaining circuit 240, the input terminal of which is connected to the output terminal of the current threshold detection circuit 230, and the output terminal of which is connected to the first input terminal of the second voltage control signal generation circuit 210.

[0096] For example, the output of the voltage sustaining circuit 240 is also connected to the first input of the third voltage control signal generation circuit 220.

[0097] For example, if the current threshold detection circuit 230 is not present in the communication circuit, the input terminal of the voltage maintenance circuit 240 can be connected to the output terminal of IC3, that is, to receive the aforementioned... Figure 9 The ILM shown.

[0098] The voltage sustaining circuit 240 in this embodiment is used to prevent the voltage drop caused by the line resistance (i.e., various resistors on the communication line) from pulling down the third voltage signal (e.g., below 6V) to a level below 6V when the peripheral circuit returns a response pull-code current under a third voltage signal (e.g., 6V). This would prevent the peripheral circuit from incorrectly determining that it cannot respond to the pull-code current. In other words, the voltage sustaining circuit ensures that the third voltage signal output by the communication circuit to the peripheral circuit is maintained normally, for example, at 6V, upon receiving a response pull-code current from the peripheral circuit, thus achieving normal pull-code response and avoiding communication protocol parsing errors.

[0099] In real-world scenarios, the overall communication lines are quite long, for example, the controller and the communication circuit may be separated by thousands of meters, resulting in significant line resistance. When there is pull-code current in the communication circuit, a large voltage drop occurs, which may cause the second voltage control signal Control2, which should normally be high, to become low, and the third voltage control signal Control3, which should normally be low, to become high. This makes long-distance deployment impossible, for example, only allowing connections to 100m or 200m lines, making it difficult to implement in actual wiring. The function of the voltage sustaining circuit 240 is to keep the second voltage control signal Control2 at a high level during pull-code response, preventing it from going low.

[0100] For example, such as Figure 11 As shown, the voltage sustaining circuit 240 includes: a first NMOS transistor Q111, the control terminal (e.g., gate) of the first NMOS transistor Q111 is connected to the output terminal of the current threshold detection circuit 230, the first terminal (e.g., source or drain) of the first NMOS transistor Q111 is connected to the first input terminal of the second voltage control signal generation circuit 210, and the second terminal (e.g., drain or source) of the first NMOS transistor Q111 is used to receive the ground voltage GND.

[0101] For example, if the current threshold detection circuit 230 is not present in the communication circuit, the control terminal of the first NMOS transistor Q111 can be connected to the output terminal of IC3, that is, to receive the aforementioned... Figure 9 The ILM shown.

[0102] For example, when ILM is high or the output of the current threshold detection circuit 230 is high (that is, it means that the pull code current is detected at this time), the first NMOS transistor Q111 is turned on, thereby turning one of the input terminals of U14B low, thereby keeping the third voltage control signal Control 3 at low level and the second voltage control signal Control 2 at high level.

[0103] For example, such as Figure 11 As shown, the voltage sustaining circuit 240 further includes at least one of the following: a ninth resistor R142, the first end of which is connected to the control terminal of the first NMOS transistor Q111, and the second end of which is connected to the output terminal of the current threshold detection circuit 230 or used to receive ILM; a tenth resistor R143, the first end of which is connected to the control terminal of the first NMOS transistor Q111, and the second end of which is connected to the second terminal of the first NMOS transistor Q111.

[0104] For example, in the embodiments of this disclosure, when the 6V pull code is too low (due to the influence of line resistance), the 6V level is maintained without switching by turning Q111 on and off.

[0105] The embodiments disclosed herein achieve stability during intrinsically safe peripheral code return through a voltage sustaining circuit, thereby enabling long-term deployment.

[0106] Continue to refer to Figure 11 When the communication circuit provided in this embodiment is applied to a safety barrier, it serves as the intrinsically safe side communication parsing circuit of the safety barrier, i.e., the intrinsically safe side communication circuit, and the parsing of the communication protocol is implemented purely in hardware. Exemplarily, the safety barrier includes an intrinsically safe side circuit. Exemplarily, the intrinsically safe side circuit includes an intrinsically safe side communication circuit.

[0107] For example, the safety barrier also includes intrinsically safe side circuitry. For example, the intrinsically safe side circuitry includes intrinsically safe side communication circuitry connected to a communication line of the controller.

[0108] Exemplarily, an isolation circuit is provided between the non-intrinsically safe side circuit and the intrinsically safe side circuit. Exemplarily, the isolation circuit also includes a signal isolator U3. Exemplarily, the communication circuit and the non-intrinsically safe side communication circuit are interconnected through the signal isolator U3.

[0109] Exemplarily, the intrinsically safe side circuit also includes a power supply circuit. Exemplarily, the communication circuit is also connected to the power supply circuit.

[0110] For example, the safety barrier further includes: a first signal input terminal connected to the non-intrinsically safe side communication circuit; a second signal input terminal connected to the first signal input terminal and the signal isolator U3 respectively; the signal isolator U3 is also connected to the communication circuit.

[0111] For example, such as Figure 11As shown, the second signal input terminal receives two signals, CLK (clock) and DAT (data), respectively. Then, the CLK and DAT signals are input to the V11 and V12 input terminals of the signal isolator U3, respectively, and then output through the VO1 and VO2 output terminals of the signal isolator U3. The CLK signal is input to the input terminal of U12A and one of the input terminals of U14A, and the DAT signal is input to the input terminal of U12B, one of the input terminals of U14B, and the source or drain of Q111.

[0112] For example, in this embodiment of the disclosure, the logical combination of the two signals CLK and DAT is used to represent the first voltage signal (e.g., 20V), the third voltage signal (e.g., 6V), and the fourth voltage signal (e.g., 0V) in the communication protocol, respectively. For example, suppose that when the logical combination of the two signals CLK and DAT is "00", it means that the communication protocol wants to output a 20V voltage to the peripheral circuit, that is, control Control 1 is high.

[0113] For example, the V13 input of the signal isolator U3 is connected to the output of the current threshold detection circuit 230 or used to receive the ILM. When the output of the current threshold detection circuit 230 outputs a high level or the ILM is high, this high level is input to the V13 input of the signal isolator U3, and a high-level Draw (first pull-code current control) signal is input to the second signal input through the VO3 output of the signal isolator U3 to indicate that a pull-code current returned by the peripheral circuit has been detected. Conversely, the Draw signal is low to indicate that no pull-code current has been detected.

[0114] This embodiment of the disclosure achieves signal isolation between the intrinsically safe side and the non-intrinsically safe side by connecting the first signal input terminal to the second signal input terminal and connecting the second signal input terminal to the signal isolator U3. In other words, this embodiment of the disclosure provides an intrinsically safe barrier with a built-in isolator.

[0115] For example, NOT gates and AND gates are used to transmit the CLK and DAT signals from the non-intrinsically safe side to the intrinsically safe side.

[0116] By way of example, the communication circuit provided in this disclosure embodiment further includes at least one of the following: resistor R138, the first end of resistor R138 is connected to the V13 input terminal of signal isolator U3, and the second end of resistor R138 is connected to the output terminal of current threshold detection circuit 230; resistor R162, the first end of resistor R162 is connected to the VO1 output terminal of signal isolator, and the second end of resistor R162 is connected to the input terminal of U12A, one input terminal of U14A, and one input terminal of U14B respectively; resistor R11, the first end of resistor R11 is connected to the VO2 output terminal of signal isolator U3, and the second end of resistor R11 is connected to the input terminal of U12B, one input terminal of U14B, and the source or drain of Q111 respectively.

[0117] For example, U12A and U14A also have two terminals for receiving VCC and ground voltage, respectively.

[0118] For example, the ENA and VDDA terminals of the signal isolator U3 are used to receive the power supply voltage VDD (the size of which can be set according to actual needs) and are both connected to the first terminal of capacitor C151; the GNDA terminal and the NC terminal are connected to the analog ground AGND and are both connected to the second terminal of capacitor C151; the GNDB terminal and the other NC terminal are used to receive the ground voltage GND; the ENB terminal and the VDDB terminal are used to receive VCC.

[0119] Figure 11 C148, C126, C123, C124 and C120 shown are decoupling capacitors, which are placed at the power supply pins of each chip.

[0120] For example, such as Figure 12 As shown, the communication circuit provided in this embodiment further includes a current threshold detection circuit 230. The input terminal of the current threshold detection circuit 230 is connected to the output terminal of the first current detection chip IC3 (i.e., for receiving ILM), and the output terminal of the current threshold detection circuit 230 is used to output a first pull-current control signal Draw.

[0121] When the communication circuit is located on the intrinsically safe side, for safety reasons, the pull code current on the intrinsically safe side needs to be limited and is set to be smaller than the pull code current on the non-intrinsically safe side. For example, the pull code current on the intrinsically safe side is 20mA, while the pull code current returned to the controller from the non-intrinsically safe side is 40mA. In order to accurately distinguish this smaller pull code current on the intrinsically safe side from some instantaneous, undesirable minimum currents, i.e., to avoid erroneously returning a high-level Draw signal to the controller, this disclosure introduces a current threshold detection circuit 230. That is, a high-level Draw signal will only be triggered when the detected ILM is greater than a certain threshold (the specific threshold value can be set according to actual needs, and this disclosure does not limit it).

[0122] For example, such as Figure 12 As shown, the current threshold detection circuit 230 includes: a first comparator IC112A, the non-inverting input of the first comparator IC112A is used to receive a first reference voltage and is connected to the first terminal of the eighth resistor R1119, and the inverting input of the first comparator IC112A is connected to the output terminal of the first current detection chip (i.e., used to receive ILM); a second comparator IC112B, the inverting input of the second comparator IC112B is connected to the output terminal of the first comparator IC112A and the second terminal of the eighth resistor R1119 respectively, the non-inverting input of the second comparator IC112B is used to receive a second reference voltage, and the output terminal of the second comparator IC112B is used to output a first pull-up current control signal Draw (i.e. connected to node N11, and the output terminal of the current threshold detection circuit 230 is also connected to node N11).

[0123] For example, the non-inverting input of the first comparator IC112A is connected to the first terminal of the resistor R1121, and the second terminal of the resistor R1121 is used to receive VCC. The magnitude of the first reference voltage is set by setting the magnitude of VCC and the magnitude of the resistor R1121.

[0124] For example, the non-inverting input terminal of the first comparator IC112A is also connected to the first terminal of resistor R1120 and the first terminal of capacitor C1115 respectively; the second terminal of resistor R1120 and the second terminal of capacitor C1115 are both used to receive the ground voltage GND; one terminal of the first comparator IC112A is used to receive the ground voltage, the other terminal is used to receive VCC, and is connected to the first terminal of capacitor C1114, the second terminal of capacitor C1114 is used to receive the ground voltage GND.

[0125] For example, the non-inverting input of the second comparator IC112B is connected to the first terminal of resistor R1118, and the second terminal of resistor R1118 is used to receive VCC. By setting the values ​​of resistor R1118 and VCC, the value of the second reference voltage is set.

[0126] For example, the non-inverting input of the second comparator IC112B is also connected to the first terminal of resistor R1117 and the first terminal of capacitor C1117; the second terminal of resistor R1117 and the second terminal of capacitor C1117 are both used to receive the ground voltage GND.

[0127] The embodiments disclosed herein do not limit the magnitude of the first reference voltage and the second reference voltage, which can be set according to actual needs.

[0128] In this embodiment, IC3 converts the pull-code current into a voltage ILM. The current threshold detection circuit uses two comparators (first comparator IC112A and second comparator IC112B) to determine the pull-code current threshold and parse it into a Draw signal. Based on the detected pull-code current, it is determined whether to trigger the Draw signal to pull the current. Using two comparators can improve detection accuracy, eliminate threshold ambiguity, and trigger the action only when the voltage clearly exceeds the safety window.

[0129] It should be noted that there are multiple ways to implement current threshold detection, and it is not limited to these methods. Figure 12 The example shown.

[0130] For example, such as Figure 13 As shown, the communication circuit provided in this embodiment further includes a short-circuit detection circuit 250. The first input terminal of the short-circuit detection circuit 250 is used to receive a first voltage signal VEE, the second input terminal of the short-circuit detection circuit 250 is used to connect to a first switching circuit, and the output terminal of the short-circuit detection circuit 250 is connected to the input terminal of a first voltage control signal generation circuit.

[0131] In some abnormal situations, a short circuit may occur on the intrinsically safe side, or multiple (two or more) peripheral circuits may simultaneously return pull code current, resulting in a large current. In order to avoid the propagation of such abnormal situations, the embodiments of this disclosure introduce a short circuit detection circuit 250.

[0132] For example, such as Figure 13 As shown, the short-circuit detection circuit 250 includes: a second sampling resistor R1110, the first and second ends of which are respectively connected to the first and second input terminals of the short-circuit detection circuit, for example, to receive a first voltage signal VEE and to be connected to node N5; a second current detection chip IC1110, the non-inverting input terminal VIN+ of which is connected to the first end of the second sampling resistor R1110, and the inverting input terminal VIN- of which is connected to the second end of the second sampling resistor R1110, for detecting the voltage drop caused by the current flowing through R1110; and a third comparator IC111A, the inverting input terminal of which is connected to the output terminal OUT of the second current detection chip IC1110, and the non-inverting input terminal of which is used to receive a third reference voltage; in conjunction with the above... Figure 11 It also includes a fourth diode D1110. The negative terminal of the fourth diode D1110 is connected to the output terminal of the third comparator IC111A, and the positive terminal of the fourth diode D1110 is connected to the input terminal of the first voltage control signal generation circuit, for example, to the VO1 output terminal of the signal isolator U3.

[0133] For example, the short-circuit detection circuit 250 further includes at least one of the following: a resistor R1111, the first end of which is connected to node N5, and the second end of which is used to receive a ground voltage; a capacitor C1110, the first end of which is connected to the VCC terminal of IC1110 and is used to receive a first voltage signal VEE, and the second end of which is used to receive a ground voltage; and the GND terminal of IC1110 is used to receive a ground voltage.

[0134] For example, the short-circuit detection circuit 250 further includes at least one of the following: a resistor R1116, the first end of which is connected to the output terminal OUT of the second current detection chip IC1110, and the second end of which is used to receive a ground voltage; a resistor R1115, the first end of which is connected to the output terminal OUT of the second current detection chip IC1110, and the second end of which is connected to the inverting input terminal of the third comparator IC111A; a capacitor C1111, the first end of which is connected to the inverting input terminal of the third comparator IC111A, and the second end of which is used to receive a ground voltage; and a capacitor C1112, the first end of which is used to receive a ground voltage, and the second end of which is used to receive VCC and connected to one end of the third comparator IC111A.

[0135] For example, the non-inverting input of the third comparator IC111A is connected to the first terminal of resistor R1112, and the second terminal of resistor R1112 is used to receive VCC. The magnitude of the third reference voltage is set by adjusting the values ​​of resistor R1112 and VCC. The magnitude of the third reference voltage can be set according to actual needs, and this disclosure does not limit this setting.

[0136] For example, the short-circuit detection circuit 250 further includes at least one of the following: a resistor R1113, the first end of which is connected to the non-inverting input of the third comparator IC111A, and the second end of which is used to receive a ground voltage and connected to the other end of the third comparator IC111A; a capacitor C1113, the first end of which is connected to the non-inverting input of the third comparator IC111A, and the second end of which is used to receive a ground voltage and connected to the other end of the third comparator IC111A; and a resistor R1114, the first end of which is connected to the non-inverting input of the third comparator IC111A, and the second end of which is connected to the output of the third comparator IC111A.

[0137] For example, when an abnormally large current is sampled on R1110 (e.g., a short circuit on the intrinsically safe side), the third comparator IC111A outputs a low-level control signal Lk to the negative terminal of D1110, thereby turning on D1110. This clamps the intrinsically safe side and isolates the non-intrinsically safe side, thus improving the stability of the entire system. When no abnormally large current is sampled on R1110, the control signal Lk is high, and D1110 is turned off, without affecting normal communication protocol parsing.

[0138] For example, short-circuit detection of the intrinsically safe communication line is achieved through IC1110, IC111A, D1110, and external resistors and capacitors, namely through the second current detection chip and the third comparator IC111A.

[0139] Understandably, although Figure 13 The short-circuit detection circuit 250 given is implemented using a single comparator IC111A, but this disclosure is not limited to this. In other embodiments, a fourth comparator IC111B can be used in combination with IC111A to achieve detection through two comparators.

[0140] Figure 13 The circuit shown implements communication short-circuit isolation on the intrinsically safe side, provides stability for protocol parsing during communication, ensures stability during intrinsically safe peripheral code return, and guarantees communication short-circuit isolation.

[0141] The communication circuit provided in this disclosure uses NOT and AND gates to parse received communication protocol levels (e.g., 20V, 6V, and 0V) from the intrinsically safe side. Exemplarily, on the intrinsically safe side, NOT and AND gates, under the control of two logic signals CLK and DAT, transmit 20V, 6V, and 0V voltages of corresponding durations to the peripheral circuit. This effectively resolves conflicts in pure circuit protocol parsing and is also beneficial for long-term applications.

[0142] The communication circuit provided in this embodiment can also be connected to an intrinsically safe circuit so that the safety barrier can provide an intrinsically safe protection level of ia (the highest safety level among intrinsically safe devices).

[0143] A safety barrier is a device installed between an intrinsically safe circuit (intrinsically safe side) and a non-intrinsically safe circuit (non-intrinsically safe side) to limit the voltage and current supplied to the intrinsically safe circuit within a certain safe range. A safety barrier is also called a safety retainer. It is a safety interface for intrinsically safe circuits, enabling bidirectional transmission of electrical signals between the safe area (intrinsically safe) and the hazardous area (non-intrinsically safe), and limiting the energy transfer from the hazardous area to the safe area due to a fault.

[0144] Figure 14An architectural diagram of a safety barrier provided in an embodiment of this disclosure is shown. Exemplarily, an embodiment of this disclosure provides an isolated safety barrier. Exemplarily, an embodiment of this disclosure provides an intrinsically safe barrier with a built-in isolator or signal isolator.

[0145] like Figure 14 As shown, the safety barrier 1500 provided in this embodiment includes: a non-intrinsically safe side circuit; and an intrinsically safe side circuit 1550, which includes a communication circuit as described in any embodiment of this disclosure (when the communication circuit is located on the intrinsically safe side, it is referred to as...). Figure 15 The intrinsically safe side communication circuit 1552 shown; and the isolation circuit located between the non-intrinsically safe side circuit and the intrinsically safe side circuit 1550.

[0146] For example, the non-intrinsically safe side circuitry includes a power management circuit 1510. The power management circuit 1510 can be used to generate a first voltage signal, such as a direct current (DC) voltage signal of magnitude 20V. For example, VEE = 20V as described above.

[0147] For example, the power management circuit 1510 is used to convert the input voltage into 20V DC via a transformer.

[0148] For example, the isolation circuit includes a power magnetic isolation circuit 1520. The power management circuit 1510 interacts with the intrinsically safe side circuit 1550 via the power magnetic isolation circuit 1520.

[0149] For example, the intrinsically safe side circuit 1550 also includes a power supply circuit 1551.

[0150] For example, the power supply magnetic isolation circuit 1520 is located between the power management circuit 1510 and the power supply circuit 1551.

[0151] By way of example, the intrinsically safe side circuit 1550 further includes an intrinsically safe circuit 1553. By way of example, the intrinsically safe circuit 1553 is connected to the communication circuit (e.g., the communication circuit 1552 in this case) and the intrinsically safe peripheral 1600.

[0152] For example, the non-intrinsically safe side circuitry includes a non-intrinsically safe side communication circuitry 1530. For example, the non-intrinsically safe side communication circuitry 1530 includes a decoding and forwarding circuitry 1531 and a code-based response circuitry 1532.

[0153] For example, the non-intrinsically safe side communication circuit 1530 also includes a communication isolation circuit 1533, which is connected to the controller's communication line SLC, the decoding and forwarding circuit 1531, and the code response circuit 1532, respectively.

[0154] Exemplarily, the isolation circuit also includes a signal isolation chip 1540. Exemplarily, the signal isolation chip 1540 includes a signal isolator. Exemplarily, the signal isolation chip 1540 is located between the non-safe communication circuit 1530 and the intrinsically safe communication circuit 1552.

[0155] For example, the non-intrinsically safe side communication circuit 1530 is used to decode and forward the communication protocol and perform pull code acknowledgment. The decoded protocol is forwarded to the intrinsically safe side circuit 1550 via the signal isolation chip 1540, and the circuit receives pull code information, such as pull code current, sent by the intrinsically safe side circuit 1550.

[0156] For example, the intrinsically safe side circuit 1550 is used to forward the information received from the controller (e.g., received via SLC) to the intrinsically safe peripheral 1600, and to send the response information of the intrinsically safe peripheral 1600 (e.g., pull code response current or pull code current) to the non-intrinsically safe side circuit, such as the non-intrinsically safe side communication circuit 1530, through the signal isolator or signal isolation chip 1540.

[0157] For example, the intrinsically safe peripheral 1600 may include one or more of the following: fire protection peripherals, such as detectors, modules, audible and visual alarms, etc.

[0158] Detectors are the front-end devices in a fire alarm system, used to detect fires or related hazards. They are installed in areas where fires may occur, such as rooms, corridors, and warehouses. The main function of a detector is to sense physical quantities in the environment (such as smoke, temperature, and flames) through sensors and convert these quantities into electrical signals for transmission. When a detector detects a fire or related hazard, it immediately sends an alarm signal to the controller so that the system can take appropriate measures in a timely manner. Modules are intermediate devices in a fire alarm system, used to receive, process, transmit, and amplify the signals emitted by the detectors. Modules are installed on the connection lines between the detectors and the controller.

[0159] Figure 15 The intrinsically safe power supply circuit is shown. It not only achieves DC-DC conversion but also isolates the voltage between the intrinsically safe and non-intrinsically safe sides, ensuring safety.

[0160] For example, the 20V power supply voltage from the non-intrinsically safe side is safely transmitted to the intrinsically safe power supply circuit 1551 after magnetic isolation. For example, the voltage transmitted to the intrinsically safe power supply circuit 1551 is 20V. For example, the voltage input from the intrinsically safe power supply circuit 1551 to the intrinsically safe communication circuit 1552 is 20V, thus providing the aforementioned VEE.

[0161] In this embodiment of the disclosure, GND represents general ground, the common reference point (zero potential point) of the circuit; AGND represents analog ground, which is the ground for analog circuit design; SGND represents signal ground, which refers to the ground of the interface or communication signal, used to isolate external interference or provide a signal return path.

[0162] For example, such as Figure 15 As shown, the power supply circuit 1551 includes: a fifth transistor Q118; and an undervoltage cutoff circuit.

[0163] For example, the fifth transistor Q118 is an NPN transistor. For example, the collector of the fifth transistor Q118 is connected to the intrinsically safe communication circuit 1552, providing it with a first voltage signal VEE.

[0164] This disclosure discloses an embodiment that designs an undervoltage cutoff circuit to reduce the large input current during the isolation voltage build-up period.

[0165] For example, such as Figure 15 As shown, the undervoltage cutoff circuit includes: a third Zener diode Z112; a fourth Zener diode Z113; a sixteenth resistor R113, which is connected in parallel with the fourth Zener diode Z113; a seventeenth resistor R116, the first terminal of which is connected to the positive terminal of the third Zener diode Z112; an eighteenth resistor R134, the first terminal of which is connected to the positive terminal of the fourth Zener diode Z113, and the second terminal of which is connected to the collector of the fifth transistor Q118; and a nineteenth resistor R154, the... The first terminal of resistor R154 (number 19) is connected to the second terminal of resistor R116 (number 17) and the base of transistor Q118 (number 5). The second terminal of resistor R154 is connected to the emitter of transistor Q118. Capacitor C147 (number 4) has its first terminal connected to the base of transistor Q118 and its second terminal connected to the emitter of transistor Q118. PMOS transistor Q18 has its second terminal (e.g., drain or source) connected to the anode of Zener diode Z113. Resistor R113 (number 16) has its second terminal connected to the anode of Zener diode Z113. The control terminal of PMOS transistor Q18 is connected to the second terminal of resistor R113 (number 16) and the first terminal of resistor R134 (number 18).

[0166] This disclosure embodiment designs an undervoltage cutoff circuit including Z112, Z113, R113, R116, R134, R154, C147, and Q18 to reduce the large input current during the isolation voltage build-up period.

[0167] For example, the power supply circuit 1551 includes a twentieth resistor R14. The second terminal of the twentieth resistor R14 is used to receive the ground voltage GND.

[0168] For example, the grounding voltage in the embodiments of this disclosure may be 0V, but this disclosure is not limited thereto.

[0169] The embodiments disclosed herein ensure the stability of the output under light load by using R14 (dummy load).

[0170] By way of example, the power supply circuit 1551 further includes one or more of the following: a diode D11, the anode of which is connected to voltage Vs; a capacitor C14, the first terminal of which is connected to the cathode of diode D11 and the second terminal of which is connected to GND; a capacitor C19, the first terminal of which is connected to the cathode of diode D11 and the second terminal of which is connected to GND. The first terminal of the twentieth resistor R14 is used to connect to the cathode of diode D11.

[0171] In this embodiment of the disclosure, signal connections between the intrinsically safe side and the non-intrinsically safe side can also be achieved through pins.

[0172] For example, on the non-intrinsically safe side, signal isolation between the non-intrinsically safe side and the intrinsically safe side is achieved by connecting a signal isolator (three channels, including CLK, DAT, and Draw).

[0173] For example, the decoding and forwarding circuit determines the 20V, 6V, and 0V voltage signals carried in the communication protocol encoding signal. For instance, if the outputs CLK and DAT of the two comparators are "00", it indicates that the corresponding voltage in the communication protocol encoding signal is 20V, where 20V represents the clock signal in the communication protocol encoding signal. The inverting inputs of the two comparators are connected to the controller's communication line SLC.

[0174] In an exemplary embodiment, the logic signals generated by the decoding and forwarding circuit include CLK and DAT. Different combinations of CLK and DAT are used to represent the first voltage signal, the third voltage signal, and the fourth voltage signal in the communication protocol's encoding signal, respectively.

[0175] It should be noted that the number of bits in the logic signal generated by the decoding and forwarding circuit depends on the number of voltage signals contained in the communication protocol's encoded signal. For example, in the example above, if the communication protocol's encoded signal includes three voltage signals, then a 2-bit logic signal is sufficient to distinguish these three voltage signals. As another example, if the communication protocol's encoded signal includes five or more but less than eight voltage signals, then a 3-bit logic signal can be used for differentiation.

[0176] For example, CLK and DAT can be used to control the high and low level durations of Control 1, Control 2, and Control 3, respectively, to control the duration of 20V, 6V, and 0V in the intrinsically safe side's generated communication protocol encoding signal, thereby forming the corresponding communication protocol waveform.

[0177] The controller in this embodiment can be a fire alarm control panel, which is responsible for providing a stable power supply to the fire detection equipment (including intrinsically safe peripherals), receiving fire signals from the fire detection equipment (which can be fed back through alarm events); when a fire signal is received, the controller immediately activates the fire alarm device and issues an audible and visual alarm signal; indicates the specific location of the fire and records relevant information; and activates automatic fire extinguishing equipment and fire linkage control equipment through a fire alarm sending device or an automatic fire extinguishing control device.

[0178] For example, the non-intrinsically safe side communication circuit includes: a pull code response circuit, the output of which (i.e., node N191 in the figure) is connected to the communication line of the controller.

[0179] The pull code response circuit is used to determine whether to output a pull code current to the controller based on the received first pull current control signal Draw. For example, when Draw is high, the pull code response circuit generates a 40mA signal response as the pull code current sent to the controller.

[0180] The communication circuit and safety barrier provided in this disclosure can be used to parse the proprietary communication protocols of fire-fighting equipment. Due to their proprietary nature, this disclosure is necessary. The safety barrier provided in this disclosure has a built-in communication line isolator (signal isolator) and a maximum explosion level. The intrinsically safe communication parsing circuit achieves reasonable timing in the protocol levels through pure hardware combination, avoiding hardware conflicts. The hardware circuit has no firmware crash risk, is suitable for explosion-proof scenarios, and can achieve nanosecond-level response, real-time parsing of high-speed proprietary protocols.

[0181] Safety barriers are used to safely isolate and limit the energy output of field devices (such as sensors, transmitters, and actuators) in hazardous areas (which may contain flammable gases, vapors, or dust) from control systems (such as controllers) in safe areas (non-hazardous areas). Intrinsically safe barriers are electronic protective devices installed in safe areas (or boundaries). Through precisely designed voltage and current limiting circuits and fuses, they strictly limit the energy (voltage and current) delivered to hazardous areas, ensuring that even sparks or thermal effects generated during circuit failures are insufficient to ignite a specific explosive atmosphere. Simultaneously, they allow reliable transmission of control signals between the control system and intrinsically safe field devices, making them a core component of intrinsically safe explosion-proof systems.

[0182] The communication protocols in this embodiment belong to the application layer protocols of a fire alarm system, and are all proprietary protocols. Proprietary protocols are communication protocols designed by specific manufacturers or organizations to meet their own needs. Specific protocol content may vary between different manufacturers or systems. In a fire alarm system, proprietary protocols can precisely control the data format, transmission method, verification method, etc. Therefore, using proprietary protocols for the application layer can ensure the stability and compatibility of the system, thereby ensuring the accuracy and reliability of the data. Proprietary protocols are highly customized and specialized.

[0183] The communication protocol in this embodiment is a communication protocol between the controller and field devices (including detectors, etc.) in a fire alarm system, used for data communication between the controller and field devices.

[0184] The solutions provided in the embodiments of this disclosure can be used to achieve, for example... Figure 16 The communication protocol level analysis shown is isolated from the communication circuit. For example, Figure 16 The communication protocol shown is a proprietary protocol, a bidirectional serial communication protocol, and also an analog protocol. In this embodiment of the disclosure, the proprietary protocol can be implemented purely in hardware within the safety barrier.

[0185] For example, the communication protocol signal sent by the controller includes: Clock (CLK) level (e.g., 20V, i.e., the first voltage signal VEE mentioned above), Logic 1 level (logic 1, e.g., 6V, i.e., the third voltage signal mentioned above) and Logic 0 level (logic 0, e.g., 0V, i.e., the fourth voltage signal mentioned above). The corresponding information is sent to the peripheral device (e.g., the intrinsically safe peripheral device 1600 mentioned above, which can be a detector or module or other fire protection product) through the combination of the above three levels.

[0186] For example, the controller sends a Logic 1 level signal, and the peripheral responds by pulling the code current, for example, 40mA, when the controller outputs a 6V third voltage signal. The corresponding response information is transmitted according to the length of the code current.

[0187] The protocol in this embodiment is a unit address query protocol. The controller polls each unit address of the loop (i.e., the unique identifier of each loop unit), and the queried loop unit responds by pulling a specific current (e.g., 40mA) on the loop.

[0188] like Figure 16As shown, the loop voltage Vdd (i.e., the first voltage signal VEE) is equal to 20V, and the 20V high level is the clock bit. The data bit voltage of 6V (i.e., the third voltage signal) represents logic "1", and the voltage of 0V (i.e., the fourth voltage signal) represents logic "0". The cell return code bit, that is, the return code bit of the loop cell, the return code information or return code bit is an analog quantity of the pull current time width.

[0189] The detector in this embodiment includes a detection device with remote testing function (in the remote testing state, the detection device outputs an analog signal higher than the alarm value), an LED indicator unit 1, a processing unit 1 for controlling and adjusting the remote testing state of the detection device and the operating state of the LED indicator unit 1, and a communication register connected to the processing unit 1. The processing unit 1 is connected to both the detection device and the LED indicator unit 1. The processing unit 1 is connected to a communication circuit.

[0190] The output control module in this embodiment includes an output controller, an LED indicator unit 2, a communication register connected to the output controller, and a processor 2 that controls the output controller and the LED indicator unit 2 respectively. Both the output controller and the LED indicator unit 2 are connected to the processor 2.

[0191] In this embodiment of the disclosure, the specific product types of the detection device include any one or more of the following: temperature detectors and photoelectric detectors. However, this is only for illustrative purposes and is not limited thereto.

[0192] Figure 17 A schematic diagram of a fire alarm system according to an embodiment of this disclosure is shown.

[0193] The protocol in question is a communication protocol used in fire alarm systems. The controller, acting as the master, initiates communication, and the loop unit (which includes a loop card connected to the controller and detection devices connected to that loop card) responds as a slave. During communication, the controller sends voltage signals (e.g., communication protocol code signals), and the loop unit responds with pull-code current signals.

[0194] like Figure 17 As shown, the fire alarm system includes a controller 101, N loop cards (N is a positive integer greater than or equal to 1, and loop cards 201, ..., 202 are shown in the figure) or communication circuits that are connected to the controller 101, and N fire detectors.

[0195] N fire detectors communicate bidirectionally with controller 101 via N loop cards or communication circuits. Each loop card or communication circuit communicates bidirectionally with the controller 101, and all N fire detectors are connected via communication lines. Each of the N loop cards corresponds to one of the N fire detectors, and each fire detector and each loop card forms a corresponding loop unit for transmitting and receiving information with controller 101. The loop card separates or superimposes the clock signal and data signal from each frame of data it transmits. Each fire detector has a unique physical address.

[0196] In this disclosure, the loopback card refers to a loop control card specific to a safety barrier. The loopback card connects the controller to field devices (such as detectors, modules, etc.) to enable data transmission and monitoring. The loopback card manages and controls one or more communication loops, ensuring accurate data transmission within the loops. Multiple field devices (such as fire detectors, manual alarm buttons, etc.) can be connected to the controller via the loopback card. The loopback card supports bidirectional data communication, receiving signals from field devices and transmitting this information to the controller for processing. The loopback card supports specific communication protocols to ensure compatibility and communication efficiency with the controller and field devices.

[0197] The illustrative embodiments and descriptions of this disclosure are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0198] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following related objects are in an "or" relationship. In this disclosure, unless otherwise explicitly specified and limited, terms such as "connection" should be interpreted broadly, for example, it can mean an electrical connection or the ability to communicate with each other; it can mean a direct connection or an indirect connection through an intermediate medium. Exemplary embodiments of this disclosure have been specifically shown and described above. This disclosure is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A communication circuit, characterized in that, include: A first voltage control signal generation circuit is used to generate and output a first voltage control signal; A first switching circuit, wherein the first input terminal and the second input terminal of the first switching circuit are respectively used to receive a first voltage signal and a first voltage control signal, and the output terminal of the first switching circuit is connected to the input terminal of a peripheral circuit. A shutdown circuit, wherein the first and second terminals of the shutdown circuit are used to receive the first voltage signal, and the third terminal of the shutdown circuit is connected to the control terminal of the first switching circuit.

2. The circuit according to claim 1, characterized in that, The first switching circuit includes: The first transistor has its base used to receive the first voltage control signal, its emitter used to receive the ground voltage, and its collector connected to the first and third terminals of the turn-off circuit, respectively. The first PMOS transistor has its control terminal connected to the collector of the first transistor, its first terminal connected to the second terminal of the turn-off circuit, and its second terminal connected to the output terminal of the first switching circuit.

3. The circuit according to claim 2, characterized in that, The shutdown circuit includes: The second transistor has its base and collector used to receive the first voltage signal, and its emitter is connected to the control terminal of the first PMOS transistor. A first resistor, wherein a first end of the first resistor is connected to the collector of the second transistor, and a second end of the first resistor is connected to the base of the second transistor; and / or, The second resistor has its first end connected to the base of the second transistor and its second end connected to the collector of the first transistor.

4. The circuit according to claim 1, characterized in that, Also includes: The second switching circuit has a first input terminal and a second input terminal for receiving a second voltage signal and a second voltage control signal, respectively, and the output terminal of the second switching circuit is connected to the input terminal of the peripheral circuit. A bleeder circuit, wherein the first terminal of the bleeder circuit is used to receive the second voltage signal, and the second terminal of the bleeder circuit is connected to the output terminal of the first switching circuit.

5. The circuit according to claim 4, characterized in that, The second switching circuit includes: The second transistor has its base used to receive the second voltage control signal, its collector used to receive the second voltage signal, and its emitter used to receive the ground voltage. The second PMOS transistor has its control terminal connected to the collector of the second transistor and the first terminal of the discharge circuit, respectively. The first terminal of the second PMOS transistor is used to receive the second voltage signal, and the second terminal of the second PMOS transistor is connected to the output terminal of the first switching circuit.

6. The circuit according to claim 5, characterized in that, The discharge circuit includes: A first Zener diode, the anode of which is connected to the first terminal of the discharge circuit, and the cathode of which is connected to the second terminal of the discharge circuit; The third resistor has its first end connected to the negative or positive terminal of the first Zener diode, and its second end connected to the second or first terminal of the discharge circuit. A first diode, the negative terminal of which is connected to a first terminal of the discharge circuit, and the positive terminal of which is connected to a second terminal of the discharge circuit.

7. The circuit according to claim 5, characterized in that, Also includes: A first sampling resistor, the first end of which is connected to the second end of the second PMOS transistor, and the second end of which is connected to the input terminal of the peripheral circuit; A current slack detection circuit is provided, wherein the input terminal of the current slack detection circuit is used to receive the second voltage control signal, the first terminal of the current slack detection circuit is connected to the first terminal of the first sampling resistor, and the second terminal of the current slack detection circuit is connected to the second terminal of the first sampling resistor.

8. The circuit according to claim 7, characterized in that, The current delay detection circuit includes: A first capacitor, wherein a first terminal of the first capacitor is used to receive the second voltage control signal; The fourth transistor has its base connected to the second terminal of the first capacitor, and its emitter is used to receive the ground voltage. The third PMOS transistor has its control terminal connected to the collector of the fourth transistor, its first terminal connected to the first terminal of the first sampling resistor, and its second terminal connected to the second terminal of the first sampling resistor.

9. The circuit according to claim 8, characterized in that, The current delay detection circuit also includes: The second diode has its cathode connected to the second terminal of the first capacitor; The fourth resistor has its first end connected to the positive terminal of the second diode, and its second end used to receive ground voltage. The fifth resistor, the first end of which is connected to the second end of the fourth resistor; The sixth resistor has its first end connected to the second end of the first capacitor, and its second end connected to the second end of the fifth resistor and the base of the fourth transistor. The seventh resistor has its first end connected to the collector of the fourth transistor and its second end connected to the first end of the first sampling resistor. The second Zener diode has its anode connected to the collector of the fourth transistor and its cathode connected to the second terminal of the seventh resistor.

10. The circuit according to claim 7, characterized in that, Also includes: A first current detection chip, wherein the positive input terminal of the first current detection chip is connected to the first terminal of the first sampling resistor, and the negative input terminal of the first current detection chip is connected to the second terminal of the first sampling resistor; A current threshold detection circuit is provided, wherein the input terminal of the current threshold detection circuit is connected to the output terminal of the first current detection chip, and the output terminal of the current threshold detection circuit is used to output a first pull-up current control signal.

11. The circuit according to claim 10, characterized in that, The current threshold detection circuit includes: The first comparator has a non-inverting input terminal for receiving a first reference voltage and connecting to the first terminal of an eighth resistor, and an inverting input terminal for connecting to the output terminal of the first current detection chip. The second comparator has its inverting input connected to the output of the first comparator and the second terminal of the eighth resistor, respectively. Its non-inverting input is used to receive the second reference voltage, and its output is used to output the first pull-up current control signal.

12. The circuit according to claim 10, characterized in that, Also includes: The second voltage control signal generation circuit is used to output the second voltage control signal. A voltage sustaining circuit, wherein the input terminal of the voltage sustaining circuit is connected to the output terminal of the current threshold detection circuit, and the output terminal of the voltage sustaining circuit is connected to the first input terminal of the second voltage control signal generation circuit.

13. The circuit according to claim 12, characterized in that, The voltage sustaining circuit includes: The first NMOS transistor has its control terminal connected to the output terminal of the current threshold detection circuit, its first terminal connected to the first input terminal of the second voltage control signal generation circuit, and its second terminal used to receive the ground voltage. The ninth resistor has its first end connected to the output terminal of the current threshold detection circuit and its second end connected to the control terminal of the first NMOS transistor. The tenth resistor has its first end connected to the second end of the ninth resistor, and its second end connected to the second end of the first NMOS transistor.

14. The circuit according to claim 12, characterized in that, The second voltage control signal generation circuit includes: A first inverter, the input terminal of which is connected to the first input terminal of the second voltage control signal generation circuit; The first AND gate has its first input connected to the output of the first inverter, its second input connected to the second input of the second voltage control signal generation circuit, and its output connected to the output of the second voltage control signal generation circuit.

15. The circuit according to claim 12, characterized in that, Also includes: The third voltage control signal generation circuit, the output of which is used to output a third voltage control signal; The output of the voltage sustaining circuit is also connected to the first input of the third voltage control signal generation circuit.

16. The circuit according to claim 15, characterized in that, The third voltage control signal generation circuit includes: The second AND gate has its first input connected to the first input of the third voltage control signal generation circuit, its second input connected to the second input of the second voltage control signal generation circuit, and its output connected to the output of the third voltage control signal generation circuit.

17. The circuit according to claim 1 or 4, characterized in that, Also includes: A third switching circuit, wherein the input terminal of the third switching circuit is used to receive a third voltage control signal, and the output terminal of the third switching circuit is connected to the output terminal of the first switching circuit; The switch-off control circuit is connected to the third switch circuit.

18. The circuit according to claim 17, characterized in that, The third switching circuit includes: The eleventh resistor has a first end for receiving the third voltage control signal and a second end for connecting to the on / off control circuit. The second NMOS transistor has its control terminal connected to the turn-on / turn-off control circuit, its first terminal connected to the output terminal of the first switching circuit, and its second terminal used to receive ground voltage. The on / off control circuit includes: The third diode, the negative terminal of which is connected to the second terminal of the eleventh resistor, and the positive terminal of which is connected to the control terminal of the second NMOS transistor; The twelfth resistor has its first end connected to the negative terminal of the third diode and its second end connected to the positive terminal of the third diode. The second capacitor has its first end connected to the control terminal of the second NMOS transistor, and its second end connected to the second terminal of the second NMOS transistor. The thirteenth resistor is connected in parallel with the second capacitor.

19. The circuit according to claim 1, characterized in that, Also includes: A first voltage control signal generation circuit, wherein the output terminal of the first voltage control signal generation circuit is used to output the first voltage control signal; A short-circuit detection circuit is provided, wherein the first input terminal of the short-circuit detection circuit is used to receive the first voltage signal, the second input terminal of the short-circuit detection circuit is used to connect to the first switching circuit, and the output terminal of the short-circuit detection circuit is connected to the input terminal of the first voltage control signal generation circuit.

20. The circuit according to claim 19, characterized in that, The short-circuit detection circuit includes: The second sampling resistor has its first and second ends connected to the first and second input ends of the short-circuit detection circuit, respectively. The second current detection chip has its non-inverting input connected to the first terminal of the second sampling resistor, and its inverting input connected to the second terminal of the second sampling resistor. The third comparator has its inverting input connected to the output of the second current detection chip, and its non-inverting input used to receive a third reference voltage. The fourth diode has its cathode connected to the output of the third comparator and its anode connected to the input of the first voltage control signal generation circuit.

21. The circuit according to claim 19, characterized in that, The first voltage control signal generation circuit includes: The second inverter has its input terminal connected to the input terminal of the first voltage control signal generation circuit, and its output terminal connected to the output terminal of the first voltage control signal generation circuit.

22. A safety barrier, characterized in that, include: Non-intrinsically safe side circuit; Intrinsically safe side circuit, said intrinsically safe side circuit including the communication circuit as described in any one of claims 1 to 21; as well as An isolation circuit located between the non-intrinsically safe side circuit and the intrinsically safe side circuit.

23. The safety barrier according to claim 22, characterized in that, The intrinsically safe side circuit further includes a power supply circuit; wherein the power supply circuit includes: Fifth transistor; An undervoltage cutoff circuit is connected to the fifth transistor.

24. The safety barrier according to claim 23, characterized in that, The undervoltage cutoff circuit includes: Third Zener diode; Fourth Zener diode; The sixteenth resistor is connected in parallel with the fourth Zener diode; The seventeenth resistor, the first end of which is connected to the positive terminal of the third Zener diode; The eighteenth resistor has its first end connected to the positive terminal of the fourth Zener diode and its second end connected to the collector of the fifth transistor. The nineteenth resistor has its first end connected to the second end of the seventeenth resistor and the base of the fifth transistor, and its second end connected to the emitter of the fifth transistor. A fourth capacitor, the first terminal of which is connected to the base of the fifth transistor, and the second terminal of which is connected to the emitter of the fifth transistor; The fourth PMOS transistor, the second terminal of which is connected to the positive terminal of the fourth Zener diode.

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