K-line switching circuit and energy storage system

Abstract

The application discloses a K-line switching circuit and an energy storage system, comprising: a first signal transmission unit and a second signal transmission unit, the first signal transmission unit comprises a controlled end, which is used for connecting a communication end of a battery management system and an input end of a host computer, synchronizing signals of the communication end to the input end, and being in a disconnected state to stop signal synchronization between the communication end and the input end when signals of the controlled end are valid; the second signal transmission unit is used for connecting the communication end and an output end of the host computer, to be turned on to synchronize signals of the output end to the communication end when signals of the output end are valid, and to be in a disconnected state to prevent signals of the communication end from entering the controlled end when signals of the output end are invalid and signals of the communication end are valid. The application is used for solving the problem that the load rate of K-line transmission is high, which affects the efficiency of communication.

Description

Technical Field

[0001] This application relates to the field of battery technology, and in particular to a K-line adapter circuit and energy storage system. Background Technology

[0002] K-line communication was originally used as a communication protocol for automotive diagnostics. With technological advancements, it was gradually replaced by CAN communication. However, after the implementation of the new national standard for electric bicycles, some manufacturers have revived K-line communication in the research and development and maintenance of two-wheeled vehicles. When developing, testing, or repairing the BMS (Battery Management System) of electric two-wheeled vehicles, K-line conversion tools are typically needed to enable the host computer to interact with the BMS via K-line. Existing K-line communication conversion tools are mostly general-purpose adapters or self-designed adapter boards. Their basic principle is to connect the transmitting and receiving lines in parallel to the K-line using a short-circuit direct connection. When the host computer sends a command, such as "0X59 44 C1 04", the bus signal returned on the K-line will become "0X59 44 C1 0459 44 D1 8B", where the first four bytes are the repeated content of the host computer's self-sent command. Current solutions generally rely on the host computer software to filter redundant self-sent data at the application layer, but this method significantly increases the load rate of K-line transmission, easily affecting communication efficiency. Utility Model Content

[0003] This application provides a candlestick chart converter circuit and energy storage system to solve the problem that the high load rate of candlestick chart transmission affects communication efficiency.

[0004] The technical solution adopted in this application is as follows.

[0005] In a first aspect, this application provides a K-line adapter circuit, including: a first signal transmission unit, including a controlled terminal for connecting to the output terminal of a host computer, the first signal transmission unit for connecting the communication terminal of a battery management system and the input terminal of the host computer, synchronizing the signal of the communication terminal to the input terminal, and being in a disconnected state when the signal of the controlled terminal is valid to stop the signal synchronization between the communication terminal and the input terminal; The second signal transmission unit is used to connect the communication end and the output end of the host computer. It is turned on when the signal at the output end is valid to synchronize the signal at the output end to the communication end, and is turned off when the signal at the output end is invalid and the signal at the communication end is valid to prevent the signal at the communication end from entering the controlled end.

[0006] The first and second signal transmission units form a "transmit-receive" interlock control: when the host computer sends a valid signal, the receiving path is automatically closed and the transmitting path is opened; when the host computer is invalid, the receiving path is automatically opened and reverse coupling is suppressed through a unidirectional circuit. This hardware-level timing mutual exclusion does not rely on host computer software filtering, reducing dependence on the host computer protocol stack and application layer algorithms, reducing processing latency and computational overhead, and improving system real-time performance.

[0007] By controlling the disconnection of the host computer's receiving path through the first signal transmission unit, physical layer isolation of spontaneously transmitted data during the host computer's transmission is achieved. This prevents spontaneously transmitted signals from the host computer from being fed back to the input end and re-acquired when the host computer sends commands, eliminating "self-looping" bytes and reducing redundant data entering the bus and host computer receiving channel from the source end. This significantly reduces the invalid load rate of the K-line bus and improves effective bandwidth and communication efficiency.

[0008] By utilizing the unidirectional conduction characteristic of the second signal transmission unit, when the upper computer output is invalid but the BMS communication terminal is valid, the BMS signal is blocked from entering the controlled terminal, eliminating reverse interference to the upper computer's transmission channel during the BMS response period; when the upper computer output is valid, the upper computer signal is only synchronized to the BMS, ensuring unidirectional and clear signal transmission, avoiding bus contention and level conflicts, and improving link stability and anti-interference capability.

[0009] Compared to the existing method of directly connecting the transmit and receive lines in parallel in the host computer, this solution filters redundant spontaneous data from the host computer with simple components without changing the physical layer of the K-line and the host computer / BMS interface. The circuit implementation cost is low, the transformation threshold is small, and it is transparent to the existing host computer software and BMS protocol, with good versatility and scalability.

[0010] In conjunction with the first aspect, in one possible implementation, the first signal transmission unit includes a controlled switch, which includes a first terminal, a second terminal, and a control terminal. The first terminal is used to connect to the input terminal, and the second terminal is used to connect to the communication terminal. The control terminal of the controlled switch serves as the controlled terminal of the first communication signal transmission unit, and the control terminal is used to receive the output signal output by the output terminal. The first terminal and the control terminal are connected to a power supply to receive a first-level signal. The controlled switch is used to: disconnect the first terminal from the second terminal when the control terminal is a second-level signal; disconnect when both the control terminal and the second terminal are at the first-level signal; and conduct when both the control terminal and the second terminal are at the second-level signal. The second-level signal represents a valid signal, and the first-level signal represents an invalid signal.

[0011] When the control terminal is at the second level signal, the first and second terminals are disconnected, thus preventing invalid signals from entering the input terminal. When the control terminal is at the first level signal, the connection or disconnection is further determined based on the level state of the communication terminal, ensuring that only valid signals from the communication terminal can be transmitted to the input terminal. Therefore, this structure not only prevents spontaneous signals from the host computer from entering the input terminal but also avoids invalid signals from being repeatedly transmitted on the K-line, improving the accuracy and stability of signal transmission while reducing the bus load rate, providing a reliable guarantee for efficient communication between the host computer and the battery management system.

[0012] In conjunction with the first aspect, in one possible implementation, the controlled switch is a transistor, which includes a base, a collector, and an emitter, with the base being the control terminal, the collector being the first terminal, and the emitter being the second terminal.

[0013] In the K-bus protocol, a low level represents a valid signal, and a high level represents an invalid signal; that is, the second level signal is a low level signal, and the first level signal is a high level signal. The three states are implemented sequentially by rapidly switching between cutoff and saturation under the drive of the control terminal level: Because the second level signal represents a valid signal, when the control terminal is at the second level, the transistor enters the cutoff state, making the first and second terminals highly blocking, thus stopping the synchronization from the communication terminal to the input terminal; because the first level signal represents an invalid signal, when both the control and second terminals are at the first level, the transistor remains cutoff, not forming a current path, and the first and second terminals remain disconnected, avoiding false triggering when the bus is silent; when both the control and second terminals are at the first level, the transistor receives sufficient drive to enter saturation conduction, forming a low-impedance connection between the first and second terminals, allowing the signal from the communication terminal to be synchronized to the input terminal. Because transistors have high input impedance and fast edges, the control terminal requires less drive, the load on the host computer output terminal and the communication terminal is light, and the switching delay is low. This can effectively suppress backfeed during host computer transmission and reduce glitch triggering. Furthermore, transistors provide stable low on-resistance when saturated and high isolation when cut off, improving the physical layer isolation and anti-interference capability of the receiving path and the transmitting path. Thus, without changing the interface and protocol, the invalid load rate is reduced and the effective bandwidth and stability of K-line communication are improved.

[0014] In conjunction with the first aspect, in one possible implementation, the transistor is an NPN transistor.

[0015] When the control terminal (base) receives a second-level signal, the base current is forcibly pulled low, the NPN transistor is in the off state, the collector and emitter are disconnected, and the first and second terminals are not conducting, thus blocking the signal synchronization from the communication terminal to the input terminal. When the control terminal is a first-level signal, if the second terminal (emitter) is also a first-level signal, the collector-emitter voltage difference is insufficient, the transistor remains off, and it remains in the disconnected state, ensuring that no redundant signal is introduced when the bus is idle. When the control terminal is a first-level signal and the second terminal is a second-level signal, the base potential and emitter potential form an effective bias, the transistor conducts, the collector and emitter form a low-impedance path, and the effective signal from the communication terminal is reliably synchronized to the input terminal.

[0016] In conjunction with the first aspect, in one possible implementation, the second signal transmission unit includes a self-controlled switch, which includes a third terminal and a fourth terminal. The third terminal is connected to the communication terminal, and the fourth terminal is connected to the output terminal. The self-controlled switch is used to: conduct when the third terminal is a second-level signal and the fourth terminal is a first-level signal, and to disconnect when the third terminal is a first-level signal and the fourth terminal is a second-level signal. The communication terminal is connected to a power supply to receive the first-level signal. The second-level signal represents a valid signal, and the first-level signal represents an invalid signal.

[0017] In the K-bus protocol, a low level is a valid signal, and a high level is an invalid signal; that is, the second level signal is a low level signal, and the first level signal is a high level signal. The automatic control switch implements local closed-loop control of the signal path between the communication end and the controlled end based on the level combination of the third and fourth terminals. When the third terminal is a second level signal and the fourth terminal is a first level signal, the automatic control switch is turned on, allowing the communication end to provide a valid signal to the controlled end or subsequent circuits (through the second / third terminal). This ensures that the BMS signal can be correctly transmitted when the BMS communication end has a valid output and the controlled end is in a silent / invalid state. Conversely, when the third terminal is a first level signal and the fourth terminal is a second level signal, the automatic control switch is turned off, blocking the signal flow from the communication end to the controlled end, avoiding reverse coupling when the BMS is silent and the controlled end (e.g., the host computer's transmission path) is active or driven. Because the communication end has already connected to the first level signal via power supply as a default silent reference, this local level determination can achieve real-time judgment and response to signal direction and timing at the hardware level, without relying on filtering by the host computer software or manual intervention. Therefore, it can be deduced that the logic of the self-controlled switch can automatically adjust the path state when conflicts occur at the sending and receiving ends, prevent signal backflow and bus competition, reduce invalid repeated transmissions on the K line, reduce bus load, and improve communication reliability and real-time performance. At the same time, local self-control reduces the coupling dependency between the host computer and BMS, making the system implementation simpler and cheaper.

[0018] In conjunction with the first aspect, in one possible implementation, the self-controlled switch is a diode, which includes a cathode and an anode, with the anode serving as the third terminal and the cathode serving as the fourth terminal.

[0019] The unidirectional conductivity of a diode—conducting when forward-biased and cutting off when reverse-biased—allows for passive level determination logic: when the third and fourth terminals are combined to forward-bias the diode, it conducts, allowing the effective signal from the communication terminal to be transmitted as expected; when the level combination reverse-biases the diode, it cuts off, blocking the signal from the communication terminal and preventing reverse coupling into the controlled terminal. Therefore, using a diode as a self-controlled switch allows for passive directional control with minimal external circuitry, eliminating complex drive logic and external power supply, thus simplifying circuit implementation.

[0020] In conjunction with the first aspect, in one possible implementation, the first signal transmission unit includes a first resistor, and a second terminal is connected to a power supply via the first resistor.

[0021] First, the first resistor provides a defined pull-up / pull-down reference for the communication terminal, eliminating the floating state of the communication terminal and preventing uncertain levels caused by parasitic capacitance or interference when the communication terminal is idle, which could lead to accidental triggering of the controlled switch. Second, when working with the controlled switch (e.g., a transistor-based switch), the default first level signal of the communication terminal serves as a silent reference, ensuring that the controlled switch remains in the expected cutoff state during idle periods. This guarantees that the receiving path is receptive when the host computer is not transmitting, preventing invalid signals from flowing back to the input terminal. Third, the first resistor limits the static current flowing through the communication terminal. When short-term reverse coupling or glitches occur, the resistor can limit the peak current, reducing the impact on the host computer and BMS interface and enhancing the robustness of the circuit.

[0022] In conjunction with the first aspect, in one possible implementation, the first signal transmission unit includes a second resistor, with the first terminal connected to a power supply via the second resistor.

[0023] First, the second resistor provides a defined level bias for the input terminal, ensuring that the input terminal maintains the first level signal without external drive or transient interference, preventing the input terminal from floating or exhibiting uncertain levels, thereby eliminating false triggering or glitches caused by a floating input terminal. Second, once the input terminal is stably pulled to the first level signal, it ensures that the first signal transmission unit is in the expected logic state when idle or when the communication terminal is silent (in coordination with the judgment of the controlled switch / automatic switch), fundamentally reducing unnecessary path switching or false disconnection, and improving the stability and determinism of interlock control. Third, the second resistor limits the leakage current and transient inrush current through the input terminal, protecting back-end devices and reducing the impact on the host computer / BMS interface during abnormal coupling or level surges, enhancing the robustness of the circuit.

[0024] In conjunction with the first aspect, in one possible implementation, the second signal transmission unit includes a third resistor, and the fourth terminal is connected to the power supply via the third resistor.

[0025] First, the third resistor provides a stable level bias for the output, maintaining the first level signal when no valid signal is received from the host computer or the BMS communication terminal is silent, thus avoiding false triggering or signal glitches caused by the output terminal floating. Second, after the output is stably pulled to the first level signal, the second signal transmission unit can maintain the logical correctness of the disconnected path in the idle state, ensuring that no unexpected data backflow or interference occurs between the communication terminal and the host computer, achieving reliable interlock control at the hardware level. Third, the third resistor limits the possible leakage current and transient interference at the output, reducing the impact on the host computer / BMS interface and improving the circuit's anti-interference capability and overall robustness.

[0026] Secondly, this application also provides a candlestick chart adapter circuit, comprising: An NPN transistor includes a base, a collector, and an emitter. The base is connected to the output terminal of a host computer, the collector is connected to the input terminal of the host computer, and the emitter is connected to the communication terminal of a battery management system. The emitter, base, and collector are connected to the power supply. A diode includes a cathode and an anode, with the cathode connected to the base and the anode connected to the emitter; In conjunction with the second aspect, in one possible implementation, the K-line adapter circuit includes a first resistor, and the emitter is connected to a power supply via the first resistor; The collector of the second resistor is connected to the power supply via the second resistor; The base is connected to the power supply via the third resistor.

[0027] In conjunction with the second aspect, in one possible implementation, the K-line adapter circuit also includes: The fourth resistor is connected between the first resistor and the emitter; The fifth resistor connects the base to the cathode. The sixth resistor connects the collector to the cathode.

[0028] Thirdly, this application also provides an energy storage system, including: a host computer, a battery management system, and a K-line adapter circuit as described in the first or second aspect. The host computer includes an input terminal and an output terminal. The input terminal is used to receive signals output by the battery management system through the K-line adapter circuit, and the output terminal is used to output signals to the battery management system through the K-line adapter circuit.

[0029] The beneficial effects of the second and third aspects described above can be referenced to the first aspect or any possible implementation thereof, and will not be elaborated upon here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations.

[0030] Other advantages, objectives and features of this application will be partly apparent from the description below, and partly understood by those skilled in the art through study and practice of this application. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0032] Figure 1 This is one of the structural schematic diagrams illustrating the connection method between the host computer and the battery management system in an exemplary embodiment of this application; Figure 2 This is a second schematic diagram illustrating the connection method between the host computer and the battery management system in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of a K-line adapter circuit shown in an exemplary embodiment of this application; Figure 4 This is a schematic diagram showing the changes in the second-level signal and the first-level signal of the K-line conversion circuit; Figure 5 This is a structural diagram illustrating the connection method between the host computer and the battery management system in the background technology. Detailed Implementation

[0033] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0034] The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. In this application, "at least one" means one or more, and "more than one" means two or more. The terms "first," "second," and other ordinal terms used in this application may be used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is solely to distinguish one constituent element from others and should not be construed as indicating or implying relative importance. For example, without departing from the scope of this application, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element.

[0035] Before introducing the embodiments of this application, the technical terms and background technology involved in this application will be introduced first.

[0036] K-line communication is a single-bus-based serial communication protocol. The K-line is a single bus, typically connected to the power supply via pull-up resistors. When the bus is idle, the voltage remains high, indicating a "no signal" state, i.e., logic invalid. When the communication terminal 201 (such as BMS200) needs to send data, it pulls the voltage low by pulling down or driving the bus, creating a low-level pulse, indicating a valid logic signal. Each low-level pulse corresponds to a bit "1" or "0" (depending on the protocol encoding), completing the data transmission.

[0037] When developing, testing, or repairing the BMS200 (Battery Management System 200) for electric two-wheeled vehicles, a K-line conversion tool is typically required to enable the host computer 100 to interact with the BMS200 via K-lines. (Reference) Figure 5Existing K-line communication conversion tools are mostly general-purpose adapters or self-designed adapter boards. Their basic principle is to connect the transmitting and receiving lines in parallel to the K-line via a short-circuit direct connection. When the host computer 100 sends a command, such as "0X59 44 C1 04", the bus signal returned on the K-line will become "0X59 44 C1 04 59 44 D1 8B", where the first four bytes are a repetition of the host computer 100's self-sent command. Existing solutions generally rely on the host computer 100 software to filter redundant self-sent data at the application layer, but this method significantly increases the load rate of K-line transmission, easily affecting communication efficiency. To solve the above problems, this application provides a K-line adapter circuit 300, which forms a "transmit-receive" interlock control through the first and second signal transmission units 302: when the host computer 100 sends a valid signal, it automatically closes the receiving path and opens the transmitting path; when the host computer 100 is invalid, it automatically opens the receiving path and suppresses reverse coupling through a unidirectional circuit. This hardware-level timing mutual exclusion does not rely on the host computer 100 software filtering, reducing the dependence on the host computer 100 protocol stack and application layer algorithms, reducing processing latency and computational overhead, and improving system real-time performance.

[0038] The following first describes one or more exemplary operating environments. In one possible operating environment, this circuit is configured in an energy storage system to realize K-line communication between a host computer 100 and a battery management system (BMS) 200. The system includes a host computer 100, a battery management system 200, and a K-line adapter circuit 300. The input terminal 102 of the host computer 100 receives communication signals from the BMS 200 through the K-line adapter circuit 300, and the output terminal 101 of the host computer 100 sends control or command signals to the BMS 200 through the K-line adapter circuit 300. The K-line adapter circuit 300 is located between the host computer 100 and the BMS 200, and is used to isolate the BMS 200 signals during transmission by the host computer 100, synchronize the BMS 200 signals during reception by the host computer 100, and ensure unidirectional, interlocked signal transmission. This operating environment can reduce redundant data on the K-line bus, improve communication efficiency and reliability without relying on the application layer filtering of the host computer, while ensuring accurate and stable data exchange of the energy storage system during research and development, testing and maintenance.

[0039] Several embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the following embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0040] refer to Figure 1 , Figure 2 and Figure 3In a first aspect, this application provides a K-line adapter circuit 300, including: a first signal transmission unit 301 and a second signal transmission unit 302. The first signal transmission unit 301 includes a controlled terminal for connecting to the output terminal 101 of a host computer 100. The first signal transmission unit 301 is used to connect the communication terminal 201 of a battery management system 200 and the input terminal 102 of the host computer 100, to synchronize the signal of the communication terminal 201 to the input terminal 102, and to be in a disconnected state when the signal of the controlled terminal is valid, so as to stop the signal synchronization between the communication terminal 201 and the input terminal 102. The second signal transmission unit 302 is used to connect the communication terminal 201 of the battery management system 200 and the output terminal 101 of the host computer 100, so as to be turned on when the signal of the output terminal 101 of the host computer 100 is valid, to synchronize the signal of the output terminal 101 to the communication terminal 201, and to be in a disconnected state when the signal of the output terminal 101 is invalid and the signal of the communication terminal 201 is valid, so as to prevent the signal of the communication terminal 201 from entering the controlled terminal.

[0041] It should be noted that in K-line communication, a low level indicates a valid signal, while a high level indicates an invalid signal.

[0042] Signal synchronization means that the host computer 100 receives a signal that is completely consistent with the output of BMS200, or BMS200 receives a signal that is completely consistent with the output of host computer 100. For example, when the host computer 100 outputs a valid signal to BMS200, the signal at the output terminal 101 of the host computer 100 is at a low level, then the signal at the communication terminal 201 of BMS200 is also at a low level.

[0043] Being in a disconnected state means that the signal transmission path is broken. For example, when the first signal transmission unit 301 is disconnected, the signals of the input terminal 102 and the communication terminal 201 cannot be synchronized. That is, the signal of the communication terminal 201 cannot be transmitted to the input terminal 102, which causes the signal of the BMS200 to be unable to be transmitted to the host computer 100.

[0044] Preventing the signal from communication terminal 201 from entering the controlled terminal means that the signal from communication terminal 201 cannot be synchronized to the controlled terminal.

[0045] The first signal transmission unit 301 and the second signal transmission unit 302 form a "transmit-receive" interlock control: when the host computer 100 sends a valid signal, it automatically closes the receiving path and opens the transmitting path; when the host computer 100 is invalid, it automatically opens the receiving path and suppresses reverse coupling through a unidirectional circuit. This hardware-level timing mutual exclusion does not rely on the host computer 100's software filtering, reducing the dependence on the host computer 100's protocol stack and application layer algorithms, reducing processing latency and computational overhead, and improving system real-time performance.

[0046] By controlling the disconnection of the receiving path of the host computer 100 through the first signal transmission unit 301, physical layer isolation of spontaneous data during the transmission of the host computer 100 is achieved. This prevents the spontaneous signals of the host computer 100 from being fed back to the input terminal 102 and collected again when the host computer 100 sends commands, eliminating "self-looping" bytes and reducing redundant data entering the bus and the receiving channel of the host computer 100 from the source end. This significantly reduces the invalid load rate of the K-line bus and improves the effective bandwidth and communication efficiency.

[0047] By utilizing the unidirectional conduction characteristic of the second signal transmission unit 302, when the output of the host computer 100 is invalid but the communication terminal 201 of the BMS200 is valid, the signal of the BMS200 is blocked from entering the controlled terminal, thus eliminating the reverse interference to the transmission channel of the host computer 100 during the response of the BMS200; when the output of the host computer 100 is valid, the signal of the host computer 100 is synchronized to the BMS200, ensuring unidirectional and clear signal transmission, avoiding bus contention and level conflicts, and improving link stability and anti-interference capability.

[0048] Compared to the existing parallel connection method of the transmitting and receiving lines of the host computer 100, this solution filters redundant spontaneous data from the host computer 100 with simple components without changing the physical layer of the K-line and the interface between the host computer 100 and BMS200. The circuit implementation cost is low, the transformation threshold is small, and it is transparent to the existing host computer 100 software and BMS200 protocol, with good versatility and scalability.

[0049] In some embodiments, reference Figure 2 and Figure 3 The first signal transmission unit 301 includes a controlled switch, which also includes a first terminal, a second terminal, and a control terminal. The first terminal is used to connect to the input terminal 102, the second terminal is used to connect to the communication terminal 201, and the control terminal is used to connect to the output terminal 101. The control terminal is used to receive the output signal output by the output terminal 101. The first terminal and the control terminal are connected to a power supply to receive a first level signal. The controlled switch is used to: disconnect the first terminal from the second terminal when the control terminal is a second level signal; disconnect when both the control terminal and the second terminal are at the first level signal; and conduct when both the control terminal and the second terminal are at the second level signal. The second level signal represents a valid signal, and the first level signal represents an invalid signal.

[0050] When the control terminal is at the second level signal, the first terminal is disconnected from the second terminal, thus preventing invalid signals from entering the input terminal 102. When the control terminal is at the first level signal, the conduction or disconnection is further determined according to the level state of the communication terminal 201, thereby ensuring that only valid signals from the communication terminal 201 can be transmitted to the input terminal 102. Therefore, this structure not only prevents spontaneous signals from the host computer 100 from entering the input terminal 102, but also avoids invalid signals from being repeatedly transmitted on the K-line, improving the accuracy and stability of signal transmission, while reducing the bus load rate, providing a reliable guarantee for efficient communication between the host computer 100 and the battery management system 200.

[0051] In candlestick chart communication, a low-level signal represents a valid signal, and a high-level signal represents an invalid signal. That is, the second level signal is a low-level signal, and the first level signal is a high-level signal.

[0052] In some embodiments, reference Figure 2 and Figure 3 The controlled switch is a transistor, which includes a base, a collector, and an emitter. The base is the control terminal, the collector is the first terminal, and the emitter is the second terminal.

[0053] In the K-bus protocol, a low level is a valid signal, and a high level is an invalid signal; that is, the second level signal is a low level signal, and the first level signal is a high level signal. The three states are implemented sequentially by rapidly switching between cutoff and saturation under the drive of the control terminal level: Because the second level signal represents a valid signal, when the control terminal is at the second level, the transistor enters the cutoff state, making the first and second terminals highly blocking, thus stopping the synchronization from communication terminal 201 to input terminal 102; Because the first level signal represents an invalid signal, when both the control and second terminals are at the first level, the transistor remains cutoff, not forming a current path, and the first and second terminals remain disconnected, avoiding false triggering when the bus is silent; When both the control and second terminals are at the first level, the transistor receives sufficient drive to enter saturation conduction, forming a low-impedance connection between the first and second terminals, allowing the signal from communication terminal 201 to be synchronized to input terminal 102. Because transistors have high input impedance and fast edges, the control terminal requires less drive, the load on the output terminal 101 of the host computer 100 and the communication terminal 201 is light, and the switching delay is low. This can effectively suppress backfeed during the transmission of the host computer 100 and reduce glitch triggering. Furthermore, transistors provide stable low on-resistance when saturated and high isolation when cut off, improving the physical layer isolation and anti-interference capability of the receiving path and the transmitting path. Thus, without changing the interface and protocol, the invalid load rate is reduced and the effective bandwidth and stability of K-line communication are improved.

[0054] In some embodiments, reference Figure 2 and Figure 3The transistor is an NPN type transistor.

[0055] When the control terminal (base) receives a second-level signal, the base current is forcibly pulled low, the NPN transistor is in the off state, the collector and emitter are disconnected, and the first terminal and the second terminal are not conducting, thereby blocking the signal synchronization from the communication terminal 201 to the input terminal 102. When the control terminal is a first-level signal, if the second terminal (emitter) is also a first-level signal, the collector-emitter voltage difference is insufficient, the transistor is still off, and it remains in the disconnected state, ensuring that no redundant signal is introduced when the bus is idle. When the control terminal is a first-level signal and the second terminal is a second-level signal, the base potential and the emitter potential form an effective bias, the transistor is turned on, the collector and emitter form a low-impedance path, and the effective signal of the communication terminal 201 is reliably synchronized to the input terminal 102.

[0056] In some embodiments, reference Figure 2 and Figure 3 The second signal transmission unit 302 includes a self-control switch, which has a third terminal and a fourth terminal. The third terminal is connected to the communication terminal, and the fourth terminal is connected to the output terminal. The self-control switch is used to: conduct when the third terminal is a second level signal and the fourth terminal is a first level signal, and disconnect when the third terminal is a first level signal and the fourth terminal is a second level signal. The communication terminal 201 is connected to a power supply to receive the first level signal. The second level signal represents a valid signal, and the first level signal represents an invalid signal.

[0057] It should be noted that when the automatic control switch is on, it means that the signals at the third and fourth terminals are synchronized; when the automatic control switch is off, it means that the signals at the third and fourth terminals are not synchronized.

[0058] In the K-bus protocol, a low level is a valid signal, and a high level is an invalid signal; that is, the second level signal is a low level signal, and the first level signal is a high level signal. The automatic control switch implements local closed-loop control of the signal path between the communication terminal 201 and the control terminal based on the level combination of the third and fourth terminals. When the third terminal is a second level signal and the fourth terminal is a first level signal, the automatic control switch is turned on, allowing the communication terminal 201 to provide a valid signal to the control terminal or subsequent circuits (through the second / third terminal). This ensures that the BMS200 signal can be correctly transmitted when the BMS200 communication terminal 201 has a valid output and the control terminal is in a silent / invalid state. Conversely, when the third terminal is a first level signal and the fourth terminal is a second level signal, the automatic control switch is turned off, blocking the signal flow from the communication terminal 201 to the control terminal, preventing reverse coupling when the BMS200 is silent while the control terminal (e.g., the transmission path of the host computer 100) is active or driven. Because the communication terminal 201 has already connected the first-level signal via power supply as the default silent reference, this local level determination can realize real-time judgment and response to signal direction and timing at the hardware level, without relying on filtering or manual intervention by the host computer 100 software. Therefore, it can be deduced that the logic of the self-control switch can automatically adjust the path state when conflicts occur at the transmitting and receiving ends, preventing signal backflow and bus contention, reducing invalid repeated transmissions on the K-line, alleviating bus load, and improving communication reliability and real-time performance. Simultaneously, local self-control reduces the coupling dependency between the host computer 100 and BMS200, making the system implementation simpler and lower in cost.

[0059] In some embodiments, reference Figure 2 and Figure 3 The self-control switch is a diode D1, which includes a cathode and an anode. The anode serves as the third terminal and is used to connect to the communication terminal, while the cathode serves as the fourth terminal and is used to connect to the output terminal.

[0060] The unidirectional conductivity of diode D1, which conducts when forward-biased and cuts off when reverse-biased, enables passive level determination logic: when the third and fourth terminals combine to forward-bias diode D1, it conducts, allowing the valid signal from communication terminal 201 to be transmitted as expected; when the level combination reverse-biases diode D1, it cuts off, blocking the signal from communication terminal 201 and preventing reverse coupling into the controlled terminal. Therefore, using diode D1 as a self-controlled switch allows for passive directional control with minimal external circuitry, eliminating complex drive logic and external power supply, thus simplifying circuit implementation.

[0061] In some embodiments, reference Figure 3 The first signal transmission unit 301 includes a first resistor R1, and a second terminal is connected to the power supply via the first resistor R1, so that the second terminal is maintained at a first level signal by default. That is, the first resistor R1 acts as a pull-up resistor for the second terminal.

[0062] First, the first resistor R1 provides a defined pull-up / pull-down reference for the second terminal. Since the second terminal is connected to the communication terminal, the first resistor R1 provides a defined pull-up / pull-down reference for the communication terminal 201, eliminating the floating state of the communication terminal 201 and preventing the communication terminal 201 from generating uncertain levels due to parasitic capacitance or interference when idle, thus avoiding accidental triggering of the controlled switch. Second, when working with the controlled switch (e.g., a transistor-based switch), the default first level signal of the communication terminal 201 serves as a silent reference, ensuring that the controlled switch remains in the expected cutoff state during idle periods. This guarantees that the receiving path is receptive when the host computer 100 is not transmitting, preventing invalid signals from being fed back to the input terminal 102. Third, the first resistor R1 limits the static current flowing through the communication terminal 201. When short-term reverse coupling or glitches occur, the resistor can limit the peak current, reducing the impact on the host computer 100 and BMS200 interface and enhancing the robustness of the circuit.

[0063] In some embodiments, reference Figure 2 and Figure 3 The first signal transmission unit 301 includes a second resistor R2, and the first terminal is connected to the power supply via the second resistor R2 so that the first terminal is maintained at a first level signal by default. That is, the second resistor R2 acts as a pull-up resistor for the first terminal.

[0064] First, the second resistor R2 provides a defined level bias for the first terminal. Since the first terminal is connected to the input terminal 102, the second resistor R2 provides a defined level bias for the input terminal 102, ensuring that the input terminal 102 maintains a first level signal without external drive or transient interference. This prevents the input terminal 102 from floating or exhibiting an uncertain level, thereby eliminating false triggering or glitches caused by the input terminal 102 being floating. Second, after the input terminal 102 is stably pulled to the first level signal, it ensures that the first signal transmission unit 301 is in the expected logic state when idle or when the communication terminal 201 is silent (in coordination with the judgment of the controlled switch / automatic switch), fundamentally reducing unnecessary path switching or false disconnection, and improving the stability and determinism of the interlock control. Third, the second resistor R2 limits the leakage current and transient inrush current through the input terminal 102, protecting the back-end devices and reducing the impact on the host computer 100 / BMS200 interface during abnormal coupling or level surges, thus enhancing the robustness of the circuit.

[0065] In some embodiments, reference Figure 2 and Figure 3 The second signal transmission unit 302 includes a third resistor R3, and the fourth terminal is connected to the power supply via the third resistor R3 so that the fourth terminal is kept at the first level signal by default, that is, the third resistor R3 acts as the pull-up resistor of the fourth terminal.

[0066] First, the third resistor R3 provides a stable level bias for the fourth terminal. Since the fourth terminal is connected to the output terminal 101, the third resistor R3 provides a stable level bias for the output terminal 101, ensuring that it maintains the first level signal when no valid signal is received from the host computer 100 or the BMS200 communication terminal 201 is silent. This avoids false signal transmission or signal glitches caused by the output terminal 101 floating. Second, after the output terminal 101 is stably pulled to the first level signal, the second signal transmission unit 302 can maintain the logical correctness of the disconnected path in the idle state, ensuring that no unexpected data backflow or interference occurs between the communication terminal 201 and the host computer 100, achieving reliable interlock control at the hardware level. Third, the third resistor R3 limits the possible leakage current and transient interference of the output terminal 101, reducing the impact on the host computer 100 / BMS200 interface and improving the circuit's anti-interference capability and overall robustness.

[0067] Secondly, refer to Figure 2 and Figure 3 Based on the same technical concept, embodiments of this application also provide a K-line adapter circuit 300, including: The NPN transistor Q1 includes a base, a collector, and an emitter. The base is connected to the output terminal 101 of the host computer 100, the collector is connected to the input terminal 102 of the host computer 100, and the emitter is connected to the communication terminal 201 of the battery management system 200. The emitter, the base, and the collector are connected to the power supply. Diode D1 includes a cathode and an anode, with the cathode connected to the base and the anode connected to the emitter.

[0068] In some embodiments, the K-line adapter circuit 300 further includes: a first resistor R1, the emitter being connected to a power supply via the first resistor R1; The collector of the second resistor R2 is connected to the power supply via the second resistor R2. The base of the third resistor R3 is connected to the power supply via the third resistor R3.

[0069] In some embodiments, the K-line adapter circuit 300 further includes: a fourth resistor R4, connected between the first resistor R1 and the emitter; The fifth resistor R5 connects the base to the cathode. The sixth resistor R6 connects the collector to the cathode.

[0070] refer to Figure 4 , Figure 4In the diagram, H represents a high-level signal and L represents a low-level signal. When the output terminal 101 of the host computer 100 sends a high-level signal, the base of the NPN transistor Q1 is at a high level. At this time, if the emitter is at a low level, the NPN transistor Q1 is turned on, and the input terminal 102 of the host computer 100 becomes low. If the emitter is at a high level, the NPN transistor Q1 is turned off, and the input terminal 102 of the host computer 100 remains pulled up high.

[0071] When the transmitter of the host computer 100 sends a low level, the base of the NPN transistor Q1 is at a low level. At this time, the emitter is connected to the base at a low level through the diode D1. The communication terminal 201 of the BMS200 is directly pulled down to a low level, the NPN transistor Q1 is turned off, and the input terminal 102 of the host computer 100 remains pulled up to a high level.

[0072] Thirdly, refer to Figure 2 Based on the same technical concept, this application also provides an energy storage system, including: a host computer 100, a battery management system 200, and a K-line adapter circuit 300 as described in the first or second aspect. The host computer 100 includes an input terminal 102 and an output terminal 101. The input terminal 102 is used to receive signals output by the battery management system 200 through the K-line adapter circuit 300, and the output terminal 101 is used to output signals to the battery management system 200 through the K-line adapter circuit 300.

[0073] The beneficial effects of the second and third aspects mentioned above can be referred to in the first aspect or any possible implementation of the first aspect, and will not be elaborated here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations.

[0074] It should be noted that the order in which the embodiments are described in this application is not intended to limit the priority of the embodiments. The reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0075] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application and in its specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0076] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many forms under the guidance of this application without departing from the spirit and scope of protection of the claims. All equivalent transformations made based on the content of this application's specification and drawings under the inventive concept of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A candlestick chart adapter circuit, characterized in that, include: The first signal transmission unit includes a controlled terminal for connecting to the output terminal of a host computer. The first signal transmission unit is used to connect the communication terminal of the battery management system and the input terminal of the host computer, synchronize the signal of the communication terminal to the input terminal, and be in a disconnected state when the signal of the controlled terminal is valid to stop the signal synchronization between the communication terminal and the input terminal. The second signal transmission unit is used to connect the communication terminal and the output terminal, so as to conduct when the signal at the output terminal is valid to synchronize the signal at the output terminal to the communication terminal, and to be in a disconnected state when the signal at the output terminal is invalid and the signal at the communication terminal is valid, so as to prevent the signal at the communication terminal from entering the controlled terminal.

2. The K-line adapter circuit according to claim 1, characterized in that, The first signal transmission unit includes a controlled switch, which includes a first terminal, a second terminal, and a control terminal. The first terminal is used to connect to the input terminal, and the second terminal is used to connect to the communication terminal. The control terminal of the controlled switch serves as the controlled terminal of the first signal transmission unit. The control terminal is used to receive the output signal output by the output terminal. The first terminal and the control terminal are connected to a power supply to receive a first level signal. The controlled switch is used to: disconnect the first terminal from the second terminal when the control terminal is a second level signal; disconnect when both the control terminal and the second terminal are at the first level signal; and conduct when both the control terminal and the second terminal are at the second level signal. The second level signal represents a valid signal, and the first level signal represents an invalid signal.

3. The K-line adapter circuit according to claim 2, characterized in that, The controlled switch is a transistor, which includes a base, a collector, and an emitter. The base is the control terminal, the collector is the first terminal, and the emitter is the second terminal.

4. The K-line adapter circuit according to claim 3, characterized in that, The transistor is an NPN type transistor.

5. The K-line adapter circuit according to claim 1, characterized in that, The second signal transmission unit includes a self-controlled switch, which has a third terminal and a fourth terminal. The third terminal is connected to the communication terminal, and the fourth terminal is connected to the output terminal. The self-controlled switch is configured to: be turned on when the third terminal is a second level signal and the fourth terminal is a first level signal, and be turned off when the third terminal is the first level signal and the fourth terminal is the second level signal. The communication terminal is connected to a power source to receive the first level signal. The second level signal represents a valid signal, and the first level signal represents an invalid signal.

6. The K-line adapter circuit according to claim 5, characterized in that, The self-controlled switch is a diode, which includes a cathode and an anode, with the anode serving as the third terminal and the cathode serving as the fourth terminal.

7. The K-line adapter circuit according to claim 2, characterized in that, The first signal transmission unit includes a first resistor, and the second terminal is connected to the power supply via the first resistor.

8. The K-line adapter circuit according to claim 2, characterized in that, The K-line adapter circuit includes a second resistor, and the first end is connected to the power supply via the second resistor.

9. The K-line adapter circuit according to claim 5, characterized in that, The K-line adapter circuit includes a third resistor, and the fourth terminal is connected to the power supply via the third resistor.

10. A K-line adapter circuit, characterized in that, include: An NPN transistor includes a base, a collector, and an emitter. The base is connected to the output terminal of a host computer, the collector is connected to the input terminal of the host computer, and the emitter is connected to the communication terminal of a battery management system. The emitter, the base, and the collector are connected to a power supply. A diode includes a cathode and an anode, the cathode being connected to the base and the anode being connected to the emitter.

11. The K-line adapter circuit according to claim 10, characterized in that, Also includes: A first resistor, through which the emitter is connected to the power supply; A second resistor, the collector being connected to the power supply via the second resistor; A third resistor is provided, through which the base is connected to the power supply.

12. The K-line adapter circuit according to claim 11, characterized in that, Also includes: A fourth resistor is connected between the first resistor and the emitter; The fifth resistor connects the base to the cathode via the fifth resistor; A sixth resistor, through which the collector is connected to the cathode.

13. An energy storage system, characterized in that, The system includes a host computer, a battery management system, and a K-line adapter circuit as described in any one of claims 1-10. The host computer includes an input terminal and an output terminal. The input terminal is used to receive signals output by the battery management system through the K-line adapter circuit, and the output terminal is used to output signals to the battery management system through the K-line adapter circuit.

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