Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first nanostructure and a second nanostructure, a gate structure located between the first nanostructure and the second nanostructure, a first dielectric layer located on a sidewall of the gate structure, and a second dielectric layer located on the first dielectric layer. The first dielectric layer can include a first material, and the second dielectric layer can include a second material different from the first material. The second dielectric layer contacts the first nanostructure and the second nanostructure.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit elements and components on them.

[0003] The semiconductor industry continuously increases the packing density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, which allows more components to be integrated into a specific area. However, as the minimum feature size shrinks, other problems arise that need to be addressed. Utility Model Content

[0004] This invention provides a semiconductor device comprising: a first nanostructure and a second nanostructure, wherein the first nanostructure and the second nanostructure are vertically stacked; a gate structure located between the first nanostructure and the second nanostructure; a first dielectric layer located on the sidewall of the gate structure, wherein the first dielectric layer comprises a first material; and a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer comprises a second material different from the first material, and wherein the second dielectric layer contacts the first nanostructure and the second nanostructure.

[0005] In some embodiments, the thickness of the first dielectric layer is 1 nm to 2 nm.

[0006] In some embodiments, the semiconductor device further includes: a protrusion located below the first nanostructure and the second nanostructure; an isolation region along the sidewall of the protrusion; and a third dielectric layer and a fourth dielectric layer, the third dielectric layer being located on the isolation region and the fourth dielectric layer being located on the third dielectric layer, wherein the third dielectric layer includes a third material and the fourth dielectric layer includes a fourth material, and wherein the third material has a material composition different from that of the fourth material.

[0007] This invention provides a semiconductor device, comprising: a first nanostructure and a second nanostructure; a gate structure located between the first nanostructure and the second nanostructure; a first dielectric layer located on the sidewall of the gate structure, wherein the first dielectric layer comprises a first material; a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer comprises a second material, and wherein the second material has a dielectric constant lower than that of the first material; and a first source / drain region, wherein the first nanostructure, the second nanostructure, and the second dielectric layer contact the first source / drain region, and wherein the first dielectric layer and the first source / drain region are separated by the second dielectric layer.

[0008] In some embodiments, the second dielectric layer contacts the first nanostructure and the second nanostructure.

[0009] In some embodiments, the semiconductor device further includes: a protrusion located below the first nanostructure; an isolation region located on a sidewall of the protrusion; and a third dielectric layer located on the isolation region, wherein the bottom surface of the third dielectric layer is located below the top surface of the isolation region and the top surface of the protrusion.

[0010] In some embodiments, the semiconductor device further includes a fourth dielectric layer located on the third dielectric layer.

[0011] In some embodiments, the fourth dielectric layer directly contacts the first source / drain region.

[0012] In some embodiments, the first source / drain region has a facet.

[0013] In some embodiments, the thickness of the first dielectric layer is 1 nm to 2 nm. Attached Figure Description

[0014] The various embodiments of this utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily enlarged or reduced.

[0015] Figure 1 Examples of nanostructured field-effect transistors (nano-FETs) according to some embodiments are illustrated in a three-dimensional view.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C, Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20C This is a view of an intermediate process in the fabrication of a semiconductor device including a nanofield-effect transistor, according to some embodiments.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 20: Separator line

[0019] 50: Substrate

[0020] 50N: n-type region

[0021] 50P: p-type area

[0022] 51: First semiconductor layer

[0023] 51A: First semiconductor layer

[0024] 51B: First semiconductor layer

[0025] 51C: First semiconductor layer

[0026] 52: First Nanostructure

[0027] 52A: First Nanostructure

[0028] 52B: First Nanostructure

[0029] 52C: The First Nanostructure

[0030] 53: Second semiconductor layer

[0031] 53A: Second semiconductor layer

[0032] 53B: Second semiconductor layer

[0033] 53C: Second semiconductor layer

[0034] 54: Second Nanostructure

[0035] 54A: Second Nanostructure

[0036] 54B: Second Nanostructure

[0037] 54C: Second Nanostructure

[0038] 55: Nanostructures

[0039] 64: Multi-layer stacking

[0040] 66: Fins

[0041] 68: Shallow trench isolation (STI) zone

[0042] 70: Virtual dielectric layer

[0043] 71: Dummy gate dielectric

[0044] 72: Dummy gate layer

[0045] 74: Masking layer

[0046] 76: Dummy Gate

[0047] 78: Mask

[0048] 81: Spacer

[0049] 86: First recess

[0050] 87: Sacrificial Layer

[0051] 88: Second recess

[0052] 89: Protective layer

[0053] 90: Internal spacer

[0054] 91: Dielectric layer

[0055] 92: Epitaxial source / drain region

[0056] 92A: First inner lining layer

[0057] 92B: Second inner lining layer

[0058] 92C: Filler layer

[0059] 94: Contact etch stop layer (CESL) 96: Interlayer dielectric

[0060] 98: The third concave part

[0061] 100: Gate dielectric layer

[0062] 102: Gate electrode

[0063] 104: Gate mask

[0064] 106: Interlayer dielectric

[0065] 108: The fourth concave part

[0066] 110: First silicide region

[0067] 112: Source / Drain Contact

[0068] 114: Gate contact

[0069] 120: Semiconductor device

[0070] X: X direction

[0071] Y: Y direction

[0072] Z: Z-direction; A-A': Section B-B': Section

[0073] C-C': Section Detailed Implementation

[0074] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the illustration of embodiments of the present invention. Of course, the above are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element forming above a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0075] Furthermore, spatially relative terms may be used, such as "below," "under," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0076] Various embodiments provide semiconductor devices. For example, some embodiments provide nano-field-effect transistors (nano-FETs) including a protective layer between an inner spacer and a gate structure. The inner spacer may be located between the protective layer and the source / drain regions. Prior to forming the inner spacer, the protective layer may be formed by a chemical reaction between a sacrificial layer and plasma. In this way, during the etching process, the inner spacer and the source / drain regions can be protected by the protective layer, and sufficient electrical insulation between the source / drain regions and the gate structure can be provided by the protective layer and the inner spacer, which can reduce or eliminate parasitic capacitance between the source / drain regions and the gate structure. This improves the performance and reliability of the semiconductor device.

[0077] Some of the embodiments discussed herein are described within the context of semiconductor devices including nano-FETs. However, various embodiments can be applied to chips that replace or combine nano-FETs with other types of transistors, such as FinFETs, vertical field-effect transistors (VFETs), complementary field-effect transistors (CFETs), planar transistors, etc.

[0078] Figure 1An example of a nanofield-effect transistor (e.g., nanowire FETs, nanosheet FETs, etc.) is illustrated in a three-dimensional view. The nanofield-effect transistor includes nanostructures 55 (e.g., nanosheets, nanowires, etc.) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 serve as channel regions of the nanofield-effect transistor. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as being spaced apart from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Furthermore, although the bottom of the fins 66 is illustrated as being a single, continuous material with respect to the substrate 50, the bottom of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 66 refers to the portion extending between adjacent STI regions 68. Gate dielectric layer 100 is located above the top surface of fin 66 and along the top, sidewalls, and bottom surface of nanostructure 55. Gate electrode 102 is located above gate dielectric layer 100. Epitaxial source / drain region 92 is disposed on one side of fin 66 opposite to gate dielectric layer 100 and gate electrode 102.

[0079] Figure 1 Further illustrations are provided for the reference cross-sections used in the following figures. Reference cross-section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanofield-effect transistor. Reference cross-section B-B' is parallel to reference cross-section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanofield-effect transistors. Reference cross-section C-C' is perpendicular to reference cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanofield-effect transistor and in a direction, for example, along the current flow direction between the epitaxial source / drain regions 92 of the nanofield-effect transistor. For clarity, the following figures refer to these reference cross-sections. Some embodiments discussed herein are discussed in the context of nanofield-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate usage in planar devices, such as planar field-effect transistors or FinFETs.

[0080] Figures 2 to 20C This is a view of an intermediate process in the fabrication of a semiconductor device including a nanofield-effect transistor according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A Examples along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B Examples along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C Examples along Figure 1 The cross-sectional view of reference section C-C' is shown.

[0081] exist Figure 2The diagram provides a substrate 50. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0082] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor or an n-type nanofield-effect transistor, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor or a p-type nanofield-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (as illustrated by separator line 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided.

[0083] In addition, Figure 2In this configuration, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layer 51 may subsequently be removed and the second semiconductor layer 53 may be patterned to form channel regions of nanofield-effect transistors in the n-type region 50N and the p-type region 50P. In some embodiments, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form channel regions of nanofield-effect transistors in the n-type region 50N, and the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form channel regions of nanofield-effect transistors in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nano-field-effect transistor in the n-type region 50N, and the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nano-field-effect transistor in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nano-field-effect transistor in both the n-type region 50N and the p-type region 50P.

[0084] For illustrative purposes, the multilayer stack 64 is illustrated as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be fabricated using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon or germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material, such as silicon.

[0085] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of a nano-field-effect transistor. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of a nano-field-effect transistor.

[0086] exist Figure 3 In some embodiments, fins 66 are formed in a substrate 50 and nanostructures 55 are formed in a multilayer stack 64. Fins 66 may protrude from the substrate 50 and may be referred to as protrusions or protruding structures. In some embodiments, nanostructures 55 and fins 66 may be formed in the multilayer stack 64 and substrate 50, respectively, by etching trenches in the multilayer stack 64 and substrate 50. The etching step may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching step may be anisotropic. The step of forming nanostructures 55 by etching the multilayer stack 64 may also define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from a first semiconductor layer 51 and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from a second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 may be collectively referred to as nanostructure 55.

[0087] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins 66 and nanostructures 55. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0088] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are illustrated as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or thinner than that of the fins 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is illustrated as having a consistent width throughout the fabrication process, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0089] exist Figure 4 In the substrate 50, shallow trench isolation (STI) regions 68 are formed adjacent to the fins 66. The STI regions 68 can be formed by depositing an insulating material over the substrate 50, the fins 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. Although the insulating material is illustrated as a single layer, some embodiments may use multiple layers.

[0090] A removal process can then be applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof, can be utilized. The planarization process exposes the nanostructure 55 such that the top surfaces of the nanostructure 55 and the insulating material are substantially coplanar or flush after the planarization process is completed. The insulating material can then be etched to form STI regions 68. The insulating material can be recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. The STI regions 68 can be etched using an acceptable etching process, such as an etching process that is selective to the material of the insulating material and etches the material of the insulating material at a faster rate than the materials of the fins 66 and the nanostructure 55. For example, dilute hydrofluoric acid can be used when the insulating material is an oxide. After the removal process, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface, or a combination thereof, as shown in the figure.

[0091] The above reference Figures 2 to 4 The described process is one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the material being epitaxially grown can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0092] Additionally, for illustrative purposes, the first semiconductor layer 51 (and the resulting first nanostructure 52) is illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 (and the resulting second nanostructure 54) is illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N.

[0093] In addition, Figure 4 In this process, suitable traps (not shown separately) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different trap types, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for n-type region 50N and p-type region 50P. For example, photoresist can be formed over fin 66 and STI region 68 in n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin coating technology and can be patterned using acceptable optical lithography techniques. When the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3Between. After implantation, photoresist is removed, for example, through an acceptable ashing process.

[0094] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable optical lithography techniques. When the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted in the region at a concentration of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Between. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0095] exist Figure 5In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The masking layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques used for depositing the selected material. The dummy gate layer 72 can be made of other materials with high etch selectivity for the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes, the dummy dielectric layer 70 is illustrated as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0096] Figures 6A to 20C Various additional processes in the fabrication of nanofield-effect transistor devices according to some embodiments are illustrated. Figures 6A to 20C Examples are given for components in either or both of the n-type region 50N or the p-type region 50P. Figures 6A to 6C In this process, a mask 78, a dummy gate 76, and a dummy gate dielectric 71 are formed. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as the dummy gate structure. The mask layer 74 (see [reference]) can be processed using suitable optical lithography and etching processes. Figure 5 The mask 78 is patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 using a suitable etching process to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover the corresponding channel regions of the fin 66 and overlying the corresponding nanostructures 55. The pattern of the mask 78 can be used to separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0097] exist Figures 7A to 7CIn this process, spacer 81 is formed. Spacer 81 can self-align the subsequently formed source / drain regions and protect the dummy gate dielectric 71 and dummy gate 76 during subsequent etching processes. Spacer 81 can be a single layer of one material or multiple sublayers of different materials with different etching rates. In some embodiments, spacer 81 comprises two sublayers of different materials with different etching rates, which may be selected from silicon oxide, silicon nitride, silicon oxynitride, etc. Spacer 81 can be formed by thermal oxidation or a suitable deposition process (e.g., CVD, ALD, etc.) and then patterned by a suitable etching process, such as anisotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching), etc. Spacer layers can be formed on the top surface of STI region 68; the top surface and sidewalls of fin 66, nanostructure 55 and mask 78; and the sidewalls of dummy gate 76 and dummy gate dielectric 71. After the etching process, spacers 81 can be retained on the sidewalls of fins 66 and / or nanostructures 55, such as Figure 7B As shown; and the sidewalls of the shield 78, the dummy gate 76, and the dummy gate dielectric 71, as Figure 7C As shown.

[0098] In embodiments where spacer 81 comprises two sublayers of different materials, the implantation of lightly-doped source / drain (LDD) regions (not illustrated separately) can be performed after the formation of the first sublayer and before the formation of the second sublayer. Similar to the above. Figure 4 The implantation discussed earlier can involve forming a mask, such as a photoresist, over the n-type region 50N while exposing the p-type region 50P. An appropriate type of impurity (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 within the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have a density of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The concentration of impurities between [a certain range]. Annealing can be used to repair implant damage and revitalize implants by addressing impurities.

[0099] exist Figures 8A to 8CIn this configuration, a first recess 86 is formed in the fin 66 and the nanostructure 55. The first recess 86 can extend through the first nanostructure 52 and the second nanostructure 54 and enter the fin 66. For example... Figure 8B As shown, the top surface of the STI region 68 (e.g., the top surface of the fin 66) may be flush with the bottom surface of the first recess 86. In some embodiments, the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68. The first recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). Spacers 81 and mask 78 may shield portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the first recess 86. Each layer of the nanostructure 55 and / or fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching after the first recess 86 has reached a desired depth.

[0100] exist Figures 9A to 9C In this process, the first nanostructure 52 is replaced by a sacrificial layer 87. Replacing the first nanostructure 52 with a sacrificial layer 87 can reduce or prevent the formation of defects on the surface of the second nanostructure 54 adjacent to the first nanostructure 52 during subsequent annealing processes. The step of replacing the first nanostructure 52 may include first removing the first nanostructure 52 using a suitable etching process (e.g., an isotropic etching process) performed through the first groove 86. The etching process can selectively remove material from the first nanostructure 52 without significantly removing material from the second nanostructure 54 or the semiconductor fin 66. In embodiments where the first nanostructure 52 comprises silicon germanium and the second nanostructure 54 comprises silicon, an etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., is used to remove the first nanostructure 52.

[0101] Subsequently, a sacrificial layer 87 can be deposited in the space occupied by the first nanostructure 52 before it is removed. The sacrificial layer 87 can be deposited using a suitable deposition process, such as CVD, ALD, etc. The sacrificial layer 87 may include an insulating material, such as silicon oxide. The sacrificial layer 87 can then be partially removed by an etching process to form a second recess 88, after which the sidewalls of the sacrificial layer 87 are recessed from the sidewalls of the second nanostructure 54. The etching process can selectively remove material from the sacrificial layer 87 without significantly removing material from the second nanostructure 54 or the semiconductor fin 66. The etching process can be isotropic or anisotropic. In some embodiments, the sacrificial layer 87 can be etched using a wet etching process using diluted HF, etc. As an example, the sidewalls of the sacrificial layer 87 are... Figure 9CThe middle is illustrated as straight, but in some embodiments, the sidewalls of the sacrificial layer 87 may be concave or convex.

[0102] exist Figures 10A to 10C In this configuration, a protective layer 89 is formed on the sidewall of the sacrificial layer 87, and a dielectric layer 91 is formed on the exposed surface of the STI region 68. The protective layer 89 protects subsequently formed internal spacers and subsequently formed source / drain regions during subsequent etching processes that allow the sacrificial layer 87 to be removed, as described in more detail below. The protective layer 89 may comprise a dielectric material that has high etch selectivity to the material of the sacrificial layer 87, such as silicon oxynitride. The material of the protective layer 89 may have a dielectric constant (k) between about 5 and about 7, which can result in sufficient electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, as described in more detail below.

[0103] It can be done by means of Figures 10A to 10C The structure shown is exposed to plasma, and a portion of the sidewalls of the sacrificial layer 87 adjacent to the sacrificial layer 87 is transformed into a protective layer 89 by a chemical reaction to form the protective layer 89. During the chemical reaction, free radicals in the plasma can react with the material of the sacrificial layer 87 to produce the material of the protective layer 89. In some embodiments, the material of the sacrificial layer 87 is silicon oxide, and the chemical reaction uses ammonia plasma, during which nitrogen free radicals react with silicon oxide to produce silicon oxynitride as the material of the protective layer 89. During the chemical reaction, free radicals in the plasma can also react with the STI region 68 and transform a portion of the exposed surface of the STI region 68 adjacent to the STI region 68 into a dielectric layer 91. In some embodiments, the material of the STI region 68 is silicon oxide, and ammonia plasma is used for the chemical reaction, during which nitrogen free radicals react with silicon oxide to produce silicon oxynitride as the material of the dielectric layer 91. In some embodiments, the protective layer 89 and the dielectric layer 91 comprise the same material.

[0104] Following the chemical reaction, the protective layer 89 may have a linear stripe shape and completely cover the sidewalls of the remaining portion of the sacrificial layer 87 (e.g., the unconverted portion), while partially exposing the top and bottom surfaces of the second nanostructure 54. The protective layer 89 may have a thickness T2 between about 2 nm and about 3 nm. This shape, size, and location of the protective layer 89 can result in adequate protection of subsequently formed internal spacers and subsequently formed source / drain regions during subsequent etching processes, as well as adequate electrical insulation between the subsequently formed source / drain regions. The bottom surface of the dielectric layer 91 may be located below the top surface of the fin 66 and the STI region 68. The dielectric layer 91 may have a thickness T1 between about 1 nm and about 2 nm. In some embodiments, the thickness T2 is greater than the thickness T1 because the material of the STI region 68 has a higher density than the material of the sacrificial layer 87.

[0105] exist Figures 11A to 11C In the second recess 88, an inner spacer 90 is formed. The inner spacer 90 and the protective layer 89 together also provide electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, as discussed in more detail below. The inner spacer 90 may extend along the sidewalls of the protective layer 89 and partially contact the top and bottom surfaces of the previously exposed second nanostructure 54 after the formation of the protective layer 89 and before the formation of the inner spacer 90. The inner spacer 90 may be separated from the sacrificial layer 87 by the protective layer 89. This shape, size, and location of the inner spacer 90 can be attributed at least in part to the shape, size, and location of the protective layer 89 described above, and can result in sufficient electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure.

[0106] The inner spacer 90 can be used by... Figures 10A to 10C An inner spacer layer (not shown separately) is deposited on the structure shown, and then etched to form the inner spacer layer. The inner spacer layer can be deposited by a suitable deposition process, such as CVD, ALD, etc. The inner spacer layer can include a dielectric material, such as silicon nitride. The material of the inner spacer layer can have a dielectric constant (k) of less than about 3.5, which can be lower than the dielectric constant (k) of the protective layer 89. The inner spacer layer can include a material different from the material of the protective layer 89. The inner spacer layer can be etched to form the inner spacer 90 by an anisotropic etching process, such as RIE, NBE, etc. As an example, the outer wall of the inner spacer 90 is... Figure 11C The inner spacer 90 is exemplified as being flush with the sidewall of the second nanostructure 54. In some embodiments, the outer sidewall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54.

[0107] exist Figures 12A to 12CIn this configuration, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the epitaxial source / drain regions 92 can apply stress to the second nanostructure 54, thereby improving performance. As shown in Figure 12C, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between each pair of adjacent epitaxial source / drain regions 92. The protective layer 89 can be separated from the epitaxial source / drain regions 92 by inner spacers 90.

[0108] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The source / drain region 92 is then epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoscale field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0109] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanofield-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which compressive strain is applied to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding surface of the nanostructure 55 and can have facets.

[0110] The epitaxial source / drain region 92, sacrificial layer 87, second nanostructure 54, and / or substrate 50 can be doped to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The source / drain region can have approximately 1 × 10⁻⁶ ppm. 19 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0111] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 may have facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanofield-effect transistor to merge, such as Figure 12B As shown in Figure 12D, in some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed.

[0112] The epitaxial source / drain region 92 may include one or more layers of semiconductor material. In some embodiments, the epitaxial source / drain region 92 includes a first liner layer 92A on the sidewall of the second nanostructure 54, a second liner layer 92B on the first liner layer 92A, and a fill layer 92C on the second liner layer 92B, as shown in Figure 12C. The first liner layer 92A, the second liner layer 92B, and the fill layer 92C may be formed of different semiconductor materials and / or may be doped to different dopant concentrations. The first liner layer 92A may be grown first, the second liner layer 92B may be grown on the first liner layer 92A, and the fill layer 92C may be grown on the second liner layer 92B.

[0113] exist Figures 13A to 13C In the middle, the first interlayer dielectric (ILD) 96 is deposited on Figures 12A to 12CAbove the structure shown. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphor-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 92, mask 78, spacer 81, and dielectric layer 91. The contact etch stop layer 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the overlying first interlayer dielectric 96. In some embodiments, the dielectric layer 91 includes a material different from that of the contact etch stop layer 94.

[0114] exist Figures 14A to 14C In this process, a planarization process such as CMP can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and portions of the spacers 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the spacers 81, and the first interlayer dielectric 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed by the first interlayer dielectric 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the spacers 81.

[0115] exist Figures 15A to 15CIn one or more etching processes, a dummy gate 76 and a dummy gate dielectric 71 are removed to form a third recess 98. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 and the dummy gate dielectric 71 at a faster rate than the first interlayer dielectric 96 and / or spacer 81. Each third recess 98 exposes and / or covers a portion of a nanostructure 55, which serves as a channel region in a subsequently completed nanofield-effect transistor. The portion of the nanostructure 55 that may serve as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the etching process, the dummy gate dielectric 71 may serve as an etch stop layer when the dummy gate 76 is removed and may be removed after the dummy gate 76 is removed.

[0116] exist Figures 16A to 16C In the process, the sacrificial layer 87 is removed, which extends the third recess 98. The sacrificial layer 87 can be removed by performing an isotropic etching process, such as wet etching, which uses an etchant with a material that selectively removes the sacrificial layer 87, while the second nanostructure 54, substrate 50, and STI region 68 can be etched at most slightly. The protective layer 89 can protect the inner spacer 90 and the epitaxial source / drain region 92 during the etching process, so that the inner spacer 90 and the epitaxial source / drain region 92 can remain unetched. The protective layer 89 can also be etched at most slightly. After the etching process, the protective layer 89 can have a thickness T3 between about 1 nm and about 2 nm. In some embodiments, the thickness T2 is greater than the thickness T3. In embodiments where the sacrificial layer 87 comprises silicon germanium and the second nanostructure 54 comprises silicon, the sacrificial layer 87 is removed using an etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0117] exist Figures 17A to 17C In this structure, a gate dielectric layer 100 and a gate electrode 102 are formed in a third recess 98. The gate dielectric layer 100 can be conformally deposited in the third recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the spacer 81, and the STI region 68, as well as on the sidewalls of the spacer 81 and the protective layer 89.

[0118] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0119] Gate electrodes 102 are deposited over gate dielectric layer 100 and fill the remaining portion of third recess 98. Gate electrode 102 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102 is illustrated in Figures 17A and 17C, gate electrode 102 may include any number of substrates, any number of work function adjustment layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited between adjacent second nanostructures 54 and between second nanostructure 54A and substrate 50.

[0120] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0121] After filling the third recess 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material, which lie above the top surface of the first interlayer dielectric 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the replacement gate structure of the resulting nanofield-effect transistor. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the gate structure. The inner spacer 90 and the protective layer 89 separate the epitaxial source / drain region 92 from the gate structure and provide sufficient electrical insulation between the epitaxial source / drain region 92 and the gate structure. In this way, the parasitic capacitance between the epitaxial source / drain region 92 and the gate structure can be reduced or eliminated, thereby improving the performance and reliability of the subsequently formed semiconductor device.

[0122] exist Figures 18A to 18C In this design, the gate structure (including a gate dielectric layer 100 and a corresponding overlying gate electrode 102) is recessed, a gate mask 104 is formed in the recess, and a second interlayer dielectric 106 is formed above the first interlayer dielectric 96 and the gate mask 104. The recess can be formed directly above the gate structure and between opposing portions of the spacer 81. The gate mask 104 can include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc. A planarization process can be performed to remove excess material from the gate mask 104. The second interlayer dielectric 106 can be formed of dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, FCVD, etc.

[0123] exist Figures 19A to 19CIn the process, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a fourth recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or a portion of the gate structure. The fourth recess 108 can be formed by an etching step using anisotropic etching processes such as RIE or NBE. In some embodiments, the fourth recess 108 can be etched through the second interlayer dielectric 106 and the first interlayer dielectric 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then it can be etched through the contact etch stop layer 94 using a third etching process. A mask such as a photoresist can be formed and patterned over the second interlayer dielectric 106 to shield portions of the second interlayer dielectric 106 from the effects of the first and second etching processes. In some embodiments, the etching process may be over-etched, and therefore, the fourth recess 108 extends into the epitaxial source / drain region 92 and / or some gate structures, and the bottom of the fourth recess 108 may be flush with (e.g., on the same horizontal plane, or at the same distance from the substrate 50) or lower than (e.g., closer to the substrate 50) the epitaxial source / drain region 92 and / or some gate structures.

[0124] After the fourth recess 108 is formed, a first silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by the following steps: first, a metal (not shown separately) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 is deposited to form a silicide or germanide region over the exposed portion of the epitaxial source / drain region 92. The metals mentioned include, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Then, a thermal annealing process is performed to form the first silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide).

[0125] exist Figures 20A to 20CIn the fourth recess 108, source / drain contacts 112 and gate contacts 114 (also referred to as conductive contacts) are formed. Source / drain contacts 112 and gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, source / drain contacts 112 and gate contacts 114 each include a barrier layer and a conductive material, and are each electrically connected to an underlying conductive component (e.g., gate electrode 102 and / or first silicide region 110). Gate contact 114 is electrically connected to gate electrode 102, and source / drain contacts 112 are electrically connected to first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second interlayer dielectric 106. Figures 20A to 20C The structure shown can be called semiconductor device 120.

[0126] The embodiments of this invention have several advantageous features. By forming a protective layer 89, the inner spacer 90 and the epitaxial source / drain region 92 can be protected during the etching process, and sufficient electrical insulation can be provided between the epitaxial source / drain region 92 and the gate structure, which can reduce or eliminate parasitic capacitance between the epitaxial source / drain region 92 and the gate structure. This improves the performance and reliability of the semiconductor device 120.

[0127] In one embodiment, the semiconductor device includes a first nanostructure and a second nanostructure, wherein the first nanostructure and the second nanostructure are vertically stacked; a gate structure located between the first nanostructure and the second nanostructure; a first dielectric layer located on the sidewall of the gate structure, wherein the first dielectric layer includes a first material; and a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer includes a second material different from the first material, and wherein the second dielectric layer contacts the first nanostructure and the second nanostructure. In one embodiment, the first material has a first dielectric constant and the second material has a second dielectric constant, wherein the second dielectric constant is less than the first dielectric constant. In one embodiment, the first material has a first dielectric constant between 5 and 7. In one embodiment, the first material is silicon oxynitride, and the second material is silicon nitride. In one embodiment, the thickness of the first dielectric layer is between 1 nm and 2 nm. In one embodiment, the semiconductor device further includes a protrusion beneath the first and second nanostructures; an isolation region along the sidewall of the protrusion; and a third dielectric layer and a fourth dielectric layer, the third dielectric layer being on the isolation region and the fourth dielectric layer being on the third dielectric layer, wherein the third dielectric layer comprises a third material and the fourth dielectric layer comprises a fourth material, and wherein the third material has a different material composition than the fourth material. In one embodiment, the third material has the same material composition as the first material.

[0128] In one embodiment, the semiconductor device includes a first nanostructure and a second nanostructure; a gate structure located between the first nanostructure and the second nanostructure; a first dielectric layer located on a sidewall of the gate structure, wherein the first dielectric layer includes a first material; a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer includes a second material, and wherein the second material has a lower dielectric constant than the first material; and a first source / drain region, wherein the first nanostructure, the second nanostructure, and the second dielectric layer contact the first source / drain region, and wherein the first dielectric layer is separated from the first source / drain region by the second dielectric layer. In one embodiment, the first material has a dielectric constant between 5 and 7, and the second material has a dielectric constant less than 3.5. In one embodiment, the first material is silicon oxynitride. In one embodiment, the second dielectric layer contacts the first nanostructure and the second nanostructure. In one embodiment, the semiconductor device further includes a protrusion beneath the first nanostructure; an isolation region located on the sidewall of the protrusion; and a third dielectric layer on the isolation region, wherein the bottom surface of the third dielectric layer is located below the top surface of the isolation region and the top surface of the protrusion. In one embodiment, the third dielectric layer includes a first material.

[0129] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure and a second nanostructure over a fin; forming an isolation region along the sidewalls of the fin; forming a sacrificial layer between the first nanostructure and the second nanostructure, wherein the sidewalls of the sacrificial layer are recessed from the sidewalls of the first nanostructure and the second nanostructure, and wherein the sacrificial layer comprises a first material; converting a portion of the sacrificial layer adjacent to the sidewalls of the sacrificial layer into a protective layer by a chemical reaction, wherein the protective layer comprises a second material different from the first material; forming a spacer layer on the protective layer; and forming source / drain regions, wherein the source / drain regions contact the first nanostructure, the second nanostructure, and the spacer layer. In one embodiment, the chemical reaction step includes exposing a portion of the sacrificial layer adjacent to the sidewalls of the sacrificial layer to an ammonia plasma. In one embodiment, the first material is silicon oxide and the second material is silicon oxynitride. In one embodiment, the sacrificial layer contacts the top surface of the first nanostructure and the bottom surface of the second nanostructure, and wherein the top surface of the first nanostructure and the bottom surface of the second nanostructure remain partially exposed after the chemical reaction. In one embodiment, the method further includes converting a portion of the exposed top surface of the isolation region adjacent to the isolation region into a dielectric layer by a chemical reaction, wherein the dielectric layer comprises a material different from the isolation region. In one embodiment, the spacer layer has a lower dielectric constant than the protective layer. In another embodiment, the method further includes removing the sacrificial layer and forming a gate structure between the first nanostructure and the second nanostructure, wherein the gate structure contacts the protective layer.

[0130] The components of several embodiments are outlined above to facilitate a better understanding of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized by comprising: include: A first nanostructure and a second nanostructure, wherein the first nanostructure and the second nanostructure are stacked vertically; A gate structure is located between the first nanostructure and the second nanostructure; A first dielectric layer is located on one sidewall of the gate structure; as well as A second dielectric layer is located on the first dielectric layer, and wherein the second dielectric layer contacts the first nanostructure and the second nanostructure.

2. The semiconductor device according to claim 1, wherein The thickness of the first dielectric layer is 1 nm to 2 nm.

3. The semiconductor device according to claim 1 or 2, wherein Including: A protrusion is located below the first nanostructure and the second nanostructure; An isolation zone, along the sidewall of the protrusion; and A third dielectric layer and a fourth dielectric layer, wherein the third dielectric layer is located on the off-region and the fourth dielectric layer is located on the third dielectric layer.

4. A semiconductor device, characterized by comprising: include: A first nanostructure and a second nanostructure; A gate structure is located between the first nanostructure and the second nanostructure; A first dielectric layer is located on the sidewall of the gate structure; A second dielectric layer is located on the first dielectric layer; as well as A first source / drain region, wherein the first nanostructure, the second nanostructure, and the second dielectric layer contact the first source / drain region, and wherein the first dielectric layer is separated from the first source / drain region by the second dielectric layer.

5. The semiconductor device according to claim 4, wherein The second dielectric layer contacts the first nanostructure and the second nanostructure.

6. The semiconductor device according to claim 4, wherein Including: A protrusion is located below the first nanostructure; An isolation zone, located on one side wall of the protrusion; and A third dielectric layer is located on the isolation region, wherein the bottom surface of the third dielectric layer is located below the top surface of the isolation region and the top surface of the protrusion.

7. The semiconductor device according to claim 6, wherein It also includes: a fourth dielectric layer located on the third dielectric layer.

8. The semiconductor device according to claim 7, wherein The fourth dielectric layer is in direct contact with the first source / drain region.

9. The semiconductor device according to claim 4, wherein The first source / drain region has a facet.

10. The semiconductor device according to claim 4, wherein The thickness of the first dielectric layer is 1 nm to 2 nm.

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