Passivation structure, solar cell, solar cell module and system
By introducing passivation structures into solar cells, including a stacked arrangement of tunneling oxide layer, polycrystalline silicon layer, metal oxide layer and carrier selective contact layer, the parasitic absorption of light by the polycrystalline silicon layer is solved, thereby improving cell efficiency and short-circuit current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BYD CO LTD
- Filing Date
- 2025-05-19
- Publication Date
- 2026-08-04
AI Technical Summary
The thick polycrystalline silicon layer on the back surface of existing solar cells has parasitic absorption of light, which affects the short-circuit current of the cell and thus limits the improvement of cell efficiency.
A passivation structure is adopted, including a tunneling oxide layer, a polysilicon layer, a metal oxide layer, and a carrier selective contact layer. The thickness of the polysilicon layer is reduced by stacking, which prevents the metal electrode from being sintered too deeply and damaging the tunneling oxide layer, thereby reducing current loss.
It effectively reduces parasitic absorption in the polycrystalline silicon layer, improves the efficiency and short-circuit current of solar cells, and reduces current loss.
Smart Images
Figure CN224596887U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cell technology, and in particular to a passivation structure, a solar cell, a solar cell module, and a solar cell system. Background Technology
[0002] In recent years, crystalline silicon solar cells have become the mainstream choice for commercial solar cells due to their advantages in material cost, mature manufacturing technology, stable product performance, relatively high photoelectric conversion efficiency, and relatively environmental friendliness.
[0003] Currently, in the fabrication process of TOPCon (Tunnel Oxide Passivated Contact) solar cells, the metal contact electrode is usually formed into the doped polycrystalline silicon layer by screen printing and high-temperature sintering. A relatively thick doped polycrystalline silicon layer is required to prevent sintering into the tunnel oxide layer or even the crystalline silicon substrate.
[0004] However, the thick doped polycrystalline silicon layer on the back surface of existing solar cells has parasitic absorption of light and affects the short-circuit current of the cell, which is beneficial to improving the efficiency of solar cells. Utility Model Content
[0005] Based on this, this application provides a passivation structure, a solar cell, a solar cell module, and a solar cell system to solve the problem that the thick polycrystalline silicon layer on the back surface of existing solar cells has parasitic absorption of light and affects the short-circuit current of the cell.
[0006] In a first aspect, this application provides a passivation structure, which includes a tunneling oxide layer, a polysilicon layer, a metal oxide layer, and a carrier-selective contact layer.
[0007] A polycrystalline silicon layer is stacked on one side of the tunneling oxide layer, a metal oxide layer is stacked on the side of the polycrystalline silicon layer opposite to the tunneling oxide layer, and a carrier selective contact layer is stacked on the side of the metal oxide layer opposite to the polycrystalline silicon layer.
[0008] In one possible implementation, the metal oxide layer includes at least one of a titanium dioxide layer, a zinc oxide layer, a tantalum pentoxide layer, a niobium pentoxide layer, a cadmium oxide layer, a scandium trioxide layer, a barium oxide layer, a tin dioxide layer, and a magnesium oxide layer.
[0009] And / or, the thickness of the metal oxide layer is 2 nm to 30 nm.
[0010] In one possible implementation, the metal oxide layer is a titanium dioxide layer, and the titanium dioxide layer also contains a dielectric material, which is at least one of tantalum and aluminum.
[0011] In one possible implementation, the carrier selection contact layer includes at least one of a lithium fluoride layer and a magnesium fluoride layer;
[0012] And / or, the thickness of the carrier selection contact layer is 1 nm to 10 nm.
[0013] In one possible implementation, the metal oxide layer includes at least one of a molybdenum trioxide layer, a vanadium pentoxide layer, a tungsten trioxide layer, a nickel oxide layer, a cuprous oxide layer, a chromium trioxide layer, a cobalt oxide layer, and a rhenium trioxide layer;
[0014] And / or, the thickness of the metal oxide layer is 5 nm to 30 nm.
[0015] In one possible implementation, the carrier-selective contact layer includes at least one of a molybdenum trioxide layer, a poly-polystyrene sulfonic acid layer, and a cuprous sulfide layer.
[0016] And / or, the thickness of the carrier selection contact layer is 1 nm to 10 nm.
[0017] In one possible implementation, the polycrystalline silicon layer contains phosphorus.
[0018] And / or, the thickness of the polycrystalline silicon layer is 20nm to 100nm.
[0019] In one possible implementation, the tunneling oxide layer includes at least one of a silicon dioxide layer and a silicon oxynitride layer;
[0020] And / or, the thickness of the tunneling oxide layer is 0.5 nm to 3 nm.
[0021] In a second aspect, this application also provides a solar cell, a substrate and any of the passivation structures provided in the first aspect, the substrate having a light-receiving surface and a back-lighting surface, and a tunneling oxide layer stacked on the back-lighting surface on the side opposite to the polycrystalline silicon layer.
[0022] In one possible implementation, it also includes a P-type emitter, a first electrode, and a second electrode, with the P-type emitter stacked on the light-receiving surface;
[0023] The first electrode is in electrical contact with the P-type emitter, and the second electrode is in electrical contact with the carrier selective contact layer.
[0024] In one possible implementation, a passivation layer and a first antireflection layer are also included, with the passivation layer stacked on the side of the P-type emitter facing away from the substrate and the first antireflection layer stacked on the side of the passivation layer facing away from the substrate.
[0025] In one possible implementation, a second anti-reflection layer is also included, which is stacked on the side of the carrier selection contact layer facing away from the substrate.
[0026] In one possible implementation, the second electrode is a gate line electrode or a full back electrode.
[0027] Thirdly, this application also provides a solar cell module, including any of the solar cells provided in the second aspect.
[0028] Fourthly, this application also provides a solar cell system, including any of the solar cells provided in the second aspect or including the solar cell modules provided in the third aspect.
[0029] The passivation structure, solar cell, solar cell module, and solar cell system provided in this application include a tunneling oxide layer, a polycrystalline silicon layer, a metal oxide layer, and a carrier selective contact layer. This is achieved by stacking the polycrystalline silicon layer on one side of the tunneling oxide layer, then stacking the metal oxide layer on the side of the polycrystalline silicon layer facing away from the tunneling oxide layer, and finally stacking the carrier selective contact layer on the side of the metal oxide layer facing away from the polycrystalline silicon layer. Therefore, the passivation structure provided in this application can reduce the thickness of the polycrystalline silicon layer, reduce parasitic absorption, prevent excessive sintering of the metal electrode from damaging the tunneling oxide layer, reduce current loss, and thereby improve the efficiency of the solar cell. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a partial structural schematic diagram of the passivation structure provided in the embodiments of this application;
[0032] Figure 2 This is a partial structural schematic diagram of a solar cell provided in an embodiment of this application;
[0033] Figure 3 A comparison of the electrical characteristics of the solar cells provided in the embodiments of this application with those of conventional solar cells;
[0034] Figure 4 Comparison of the electrical characteristics of the solar cell provided in the embodiments of this application with conventional solar cells (Part 2);
[0035] Figure 5 This is a partial structural schematic diagram of another solar cell provided in an embodiment of this application.
[0036] Figure label:
[0037] 10: Base;
[0038] 11: The surface receiving light;
[0039] 12: Backlit side;
[0040] 20: P-type emitter;
[0041] 30: First electrode;
[0042] 40: Second electrode;
[0043] 50: Passivation layer;
[0044] 60: First anti-reflection layer;
[0045] 70: Second anti-reflection layer;
[0046] 100: Tunneling oxide layer;
[0047] 200: Polycrystalline silicon layer;
[0048] 300: Metal oxide layer;
[0049] 400: Carrier-selective contact layer. Detailed Implementation
[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods and apparatus consistent with some aspects of this application as detailed in the appended claims.
[0051] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0052] In recent years, crystalline silicon solar cells have become the mainstream choice for commercial solar cells due to their advantages in material cost, mature manufacturing technology, stable product performance, relatively high photoelectric conversion efficiency, and relatively environmental friendliness. Tunnel oxide passivated contact solar cells (TOPCon) are simple to manufacture and compatible with existing mainstream PERC production lines, allowing for cost reduction through line upgrades. In the context of rapid advancements in photovoltaic technology, TOPCon cells balance cost and photoelectric conversion efficiency, representing a potential mainstream direction for future photovoltaic cell production technology development.
[0053] In TOPCon solar cells, the metal contact electrode is typically fabricated using screen-printed metal paste, followed by high-temperature sintering. Ultimately, the metal paste is sintered into the doped polycrystalline silicon layer. To prevent the metal paste from sintering into the tunneling oxide layer or even the crystalline silicon substrate, the thickness of the doped polycrystalline silicon is usually controlled to around 150 nm. However, the doped polycrystalline silicon layer exhibits severe parasitic absorption of light; increasing its thickness affects the cell's short-circuit current, which is detrimental to improving solar cell efficiency.
[0054] To address the aforementioned problems in the prior art, this application provides a passivation structure, a solar cell, a solar cell module, and a solar cell system. The passivation structure provided in this application includes a tunneling oxide layer, a polycrystalline silicon layer, a metal oxide layer, and a carrier selective contact layer. By stacking the polycrystalline silicon layer on one side of the tunneling oxide layer, then stacking the metal oxide layer on the side of the polycrystalline silicon layer facing away from the tunneling oxide layer, and finally stacking the carrier selective contact layer on the side of the metal oxide layer facing away from the polycrystalline silicon layer, a passivation structure is formed. This reduces the thickness of the polycrystalline silicon layer, reduces parasitic absorption, prevents excessive sintering of the metal electrode from damaging the tunneling oxide layer, reduces current loss, and thereby improves the efficiency of the solar cell.
[0055] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0056] Firstly, please refer to Figures 1-5 As shown, this application provides a passivation structure, which includes a tunneling oxide layer 100, a polysilicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400.
[0057] A polysilicon layer 200 is stacked on one side of the tunneling oxide layer 100, a metal oxide layer 300 is stacked on the side of the polysilicon layer 200 facing away from the tunneling oxide layer 100, and a carrier selection contact layer 400 is stacked on the side of the metal oxide layer 300 facing away from the polysilicon layer 200.
[0058] In this embodiment, a tunneling oxide layer 100, a polysilicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400 are sequentially stacked to form a passivation structure.
[0059] For example, a metal oxide layer 300 (TiO2) was prepared on the tunneling oxide layer 100 and the polycrystalline silicon layer 200 on the back side of the substrate 10 using an electron beam evaporation apparatus. x The passive structure of this application is formed by combining a carrier-selective contact layer 400 (LiF) and a carrier-selective contact layer 400, and the resulting material is prepared. Figure 2 The solar cell shown has a structure and dimensions of 182mm × 182mm. The efficiency of this solar cell is compared with that of conventional solar cells. The solar cell of this application increases the peak minority carrier lifetime from 3662μs to 4180μs. Figure 3 As shown, A1 represents the efficiency distribution point of the N-type solar cell of this application, where the polycrystalline silicon thickness is 70~80nm and the total thickness of the metal oxide and carrier selective contact layer is 30~35nm. A2 represents the efficiency distribution point of the conventional solar cell without the passivation structure of this application, where the polycrystalline silicon thickness is 110~120nm. The efficiency distribution of the solar cell of this application (A1) is 22.65%~24.56%, compared with the efficiency distribution of the conventional solar cell (A2) of 23.95%~24.45%. Although the efficiency distribution is relatively dispersed, the peak efficiency of the solar cell of this application has been improved to a certain extent.
[0060] Furthermore, the introduction of the carrier-selective contact layer 400 reduces parasitic absorption in the polycrystalline silicon layer 200, thereby lowering the reverse saturation current of the battery and reducing current loss. Figure 4 As shown, A1 represents the short-circuit current distribution point of the solar cell of this application, and A2 represents the short-circuit current distribution point of the conventional solar cell. The short-circuit current has increased from 6.823A~6.890A in the conventional solar cell (A2) to 6.875A~7.388A in the solar cell of this application (A1).
[0061] It is understandable that, compared with the existing technology which has a thicker doped polycrystalline silicon layer structure, the application of the passivation structure in the embodiments of this application, by providing a metal oxide layer 300 and a carrier selection contact layer 400 on the tunneling oxide layer 100 and the polycrystalline silicon layer 200 to form a passivation structure, can reduce the thickness of the polycrystalline silicon layer 200, reduce parasitic absorption, prevent the metal electrode from being sintered too deeply and damaging the tunneling oxide layer 100, reduce current loss, and thus improve the efficiency of the solar cell.
[0062] Therefore, the passivation structure provided in this embodiment includes a tunneling oxide layer 100, a polycrystalline silicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400. By stacking the polycrystalline silicon layer 200 on one side of the tunneling oxide layer 100, then stacking the metal oxide layer 300 on the side of the polycrystalline silicon layer 200 facing away from the tunneling oxide layer 100, and finally stacking the carrier selective contact layer 400 on the side of the metal oxide layer 300 facing away from the polycrystalline silicon layer 200, a passivation structure is formed. This can reduce the thickness of the polycrystalline silicon layer 200, reduce parasitic absorption, prevent the metal electrode from being sintered too deeply and damaging the tunneling oxide layer 100, reduce current loss, and thus improve the efficiency of the solar cell.
[0063] In some embodiments, when the substrate 10 is an N-type silicon wafer, the metal oxide layer 300 includes at least one of a titanium dioxide layer (TiO2), a zinc oxide layer (ZnO), a tantalum pentoxide layer (Ta2O5), a niobium pentoxide layer (Nb2O5), a cadmium oxide layer (CdO), a scandium trioxide layer (Sc2O3), a barium oxide layer (BaO), a tin dioxide layer (SnO2), and a magnesium oxide layer (MgO). The various specific component layers in the metal oxide layer 300 can be stacked or mixed. Furthermore, the thickness of the metal oxide layer 300 can be 2 nm to 30 nm, preferably 20 nm to 30 nm.
[0064] Furthermore, in this embodiment, the metal oxide layer 300 is a titanium dioxide layer (TiO2), and the titanium dioxide layer (TiO2) may also contain a dielectric (i.e., a doped dielectric), which includes at least one of tantalum (Ta) and aluminum (Al). For example, the doping concentration of the dielectric can be 0.5% to 50%, preferably 0.5% to 10%.
[0065] Furthermore, in this embodiment, the carrier selective contact layer 400 includes at least one of a lithium fluoride layer (LiF) and a magnesium fluoride layer (MgF2). The various specific component layers in the carrier selective contact layer 400 can be stacked or mixed. Moreover, the thickness of the carrier selective contact layer 400 can be 1 nm to 10 nm, preferably 5 nm to 10 nm.
[0066] In some embodiments, when the substrate 10 is a P-type silicon wafer, the metal oxide layer 300 includes at least one of a molybdenum trioxide (MoO3), a vanadium pentoxide (V2O5), a tungsten trioxide (WO3), a nickel oxide (NiO), a cuprous oxide (Cu2O), a chromium trioxide (CrO3), a cobalt oxide (CoO), and a rhenium trioxide (ReO3). The various specific component layers in the metal oxide layer 300 can be stacked or mixed. Furthermore, the thickness of the metal oxide layer 300 can be 20 nm to 30 nm.
[0067] Furthermore, in this embodiment, the carrier selective contact layer 400 includes at least one of a molybdenum trioxide layer (MoO3), a poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonate) layer (PEDOT:PSS), and a cuprous sulfide layer (Cu2S). The various specific component layers in the carrier selective contact layer 400 can be stacked or mixed. Moreover, the thickness of the carrier selective contact layer 400 can be 1 nm to 10 nm, preferably 5 nm to 10 nm.
[0068] In some embodiments, the polysilicon layer 200 may also contain phosphorus as a dopant. Furthermore, the doping concentration of the polysilicon layer 200 may be 0.5 × 10⁻⁶. 21 cm 3 ~3×10 21 cm 3 Furthermore, the thickness of the polycrystalline silicon layer 200 can be 20nm to 100nm.
[0069] Furthermore, in this embodiment, the tunneling oxide layer 100 includes a silicon dioxide layer (SiO2) and a silicon oxynitride layer (SiO2). x N y At least one of the following. The various specific component layers in the tunneling oxide layer 100 can be stacked or mixed; X and Y are not specifically limited, and their specific ratio can be adjusted according to the refractive index requirements of the film. Furthermore, the thickness of the tunneling oxide layer 100 can be from 0.5 nm to 3 nm.
[0070] The specific method for preparing the passivation structure in this embodiment is as follows:
[0071] 1) A tunneling oxide layer 100 is formed by deposition, wherein the tunneling oxide layer 100 is a silicon dioxide layer (SiO2) and a silicon oxynitride layer (SiO2). x N y At least one of the following, with a thickness of 0.5 nm to 3 nm;
[0072] 2) An amorphous silicon layer with a thickness of 20 nm to 100 nm is deposited on the tunneling oxide layer 100. The amorphous silicon layer is then phosphorus-doped using phosphorus oxychloride (POCl3) as the phosphorus source via high-temperature diffusion doping at a concentration of 0.5 × 10⁻⁶. 21 cm 3 ~3×10 21 cm 3 After high-temperature annealing, a polycrystalline silicon layer of 200 is obtained;
[0073] 3) A metal oxide layer 300 is deposited on the polycrystalline silicon layer 200. For N-type silicon wafers, the metal oxide layer 300 is at least one of titanium dioxide (TiO2), zinc oxide (ZnO), tantalum pentoxide (Ta2O5), niobium pentoxide (Nb2O5), cadmium oxide (CdO), scandium trioxide (Sc2O3), barium oxide (BaO), tin dioxide (SnO2), and magnesium oxide (MgO), with a thickness of 2 nm to 30 nm.
[0074] When the metal oxide layer 300 is a titanium dioxide layer (TiO2), the titanium dioxide layer (TiO2) may also contain a doping medium, which is at least one of tantalum (Ta) and aluminum (Al), with a doping concentration of 0.5% to 50%.
[0075] For P-type silicon wafers, the metal oxide layer 300 is at least one of the following: molybdenum trioxide (MoO3), vanadium pentoxide (V2O5), tungsten trioxide (WO3), nickel oxide (NiO), cuprous oxide (Cu2O), chromium trioxide (CrO3), cobalt oxide (CoO), and rhenium trioxide (ReO3), with a thickness of 5 nm to 30 nm.
[0076] 4) Deposit a carrier selective contact layer 400 on the metal oxide layer 300. For N-type silicon wafers, the carrier selective contact layer 400 is at least one of lithium fluoride layer (LiF) and magnesium fluoride layer (MgF2), with a thickness of 1 nm to 10 nm.
[0077] For P-type silicon wafers, the carrier selection contact layer 400 is at least one of molybdenum trioxide (MoO3), poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonate), and cuprous sulfide (Cu2S), with a thickness of 1 nm to 10 nm.
[0078] The tunneling oxide layer 100 in this embodiment can be prepared by high-temperature thermal oxidation, ozone oxidation, or plasma-assisted nitrous oxide process. The polycrystalline silicon layer 200 in this embodiment can be prepared by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The metal oxide layer 300 and the carrier-selective contact layer 400 in this embodiment can be prepared by electron beam assisted evaporation, thermal evaporation, atomic layer deposition, PVD, PECVD, or other processes.
[0079] Secondly, such as Figure 2 , Figure 5 As shown, this application embodiment also provides a solar cell, including a substrate 10 and a passivation structure provided in any of the above embodiments. The substrate 10 has a light-receiving surface 11 and a back-lighting surface 12, and a tunneling oxide layer 100 is stacked on the back-lighting surface 12 on the side opposite to the polycrystalline silicon layer 200.
[0080] In this embodiment, the substrate 10, also called a silicon wafer or substrate, has a light-receiving surface 11 (i.e., the front or upper surface of the substrate 10) and a back-lighting surface 12 (i.e., the back or lower surface of the substrate 10). Furthermore, the substrate 10 can typically be fabricated as an N-type silicon wafer or a P-type silicon wafer. N-type silicon wafers are typically made of materials with higher electron mobility than hole mobility. Conversely, P-type silicon wafers are typically made of materials with higher hole mobility than electron mobility.
[0081] The passivation structure has been described in detail in the above embodiments and will not be repeated here.
[0082] It is understood that the solar cell provided in this application embodiment, by configuring the above-mentioned passivation structure, which includes a tunneling oxide layer 100, a polycrystalline silicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400, forms a passivation structure by stacking the polycrystalline silicon layer 200 on one side of the tunneling oxide layer 100, then stacking the metal oxide layer 300 on the side of the polycrystalline silicon layer 200 opposite to the tunneling oxide layer 100, and finally stacking the carrier selective contact layer 400 on the side of the metal oxide layer 300 opposite to the polycrystalline silicon layer 200. This can reduce the thickness of the polycrystalline silicon layer 200, reduce parasitic absorption, prevent the metal electrode from being sintered too deeply and damaging the tunneling oxide layer 100, reduce current loss, and thereby improve the efficiency of the solar cell.
[0083] In some embodiments, the solar cell provided in this application further includes a P-type emitter 20, a first electrode 30, and a second electrode 40, with the P-type emitter 20 stacked on the light-receiving surface 11.
[0084] The first electrode 30 is in electrical contact with the P-type emitter 20, and the second electrode 40 is in electrical contact with the carrier selective contact layer 400.
[0085] Furthermore, in this embodiment, the solar cell provided by this application further includes a passivation layer 50 and a first antireflection layer 60. The passivation layer 50 is stacked on the side of the P-type emitter 20 facing away from the substrate 10, and the first antireflection layer 60 is stacked on the side of the passivation layer 50 facing away from the substrate 10.
[0086] Furthermore, the solar cell provided in this application also includes a second antireflection layer 70, which is stacked on the side of the carrier selection contact layer 400 facing away from the substrate 10.
[0087] Furthermore, in this embodiment, the second electrode 40 is a grid line electrode or a full back electrode.
[0088] The specific method for preparing the solar cell in this embodiment is as follows:
[0089] 1) Clean the substrate 10 to remove surface dirt and damaged layers, and then texturize it using an alkaline solution;
[0090] 2) High-temperature boron diffusion is performed on the light-receiving surface 11 of the substrate 10 to form a P-type emitter 20, thereby forming a PN junction. Then, the borosilicate glass on the surface of the substrate 10 is removed with hydrofluoric acid, and the backlight surface 12 of the substrate 10 is polished with alkaline solvent and additives.
[0091] 3) A tunneling silicon dioxide layer is deposited on the back of the silicon wafer using a high-temperature thermal oxidation process, an ozone oxidation process, or a plasma-assisted nitrous oxide process.
[0092] 4) After depositing an intrinsic polycrystalline silicon thin film on the back surface 12 of the substrate 10 using low-pressure chemical vapor deposition (LPCVD), a phosphorus source is used for high-temperature diffusion doping to form a phosphorus-doped polycrystalline silicon layer. The edge-coated phosphosilicate glass (PSG) is removed by acid etching. Alternatively, a phosphorus-doped amorphous silicon thin film is deposited in situ on the back surface 12 of the substrate 10 using plasma-enhanced chemical vapor deposition (PECVD), and a phosphorus-doped polycrystalline silicon thin film is obtained by high-temperature crystallization annealing.
[0093] 5) Remove the polycrystalline silicon wrapped around the front side with alkaline solution, remove the phosphosilicate glass and borosilicate glass on the front side with hydrofluoric acid, perform RCA cleaning, and remove excess phosphosilicate glass on the back side;
[0094] 6) The selection of materials for the metal oxide layer 300 and the carrier selection contact layer 400 needs to be based on different battery types (N-type batteries usually select materials with higher electron mobility than hole mobility; conversely, P-type batteries usually select materials with higher hole mobility than electron mobility). The metal oxide layer 300 and the carrier selection contact layer 400 are sequentially prepared on the lower surface of the polycrystalline silicon layer 200 on the backlight surface 12.
[0095] 7) A passivation layer 50 and a first antireflection layer 60 are deposited on the upper surface of the p-type emitter 20. The film structure of the passivation layer 50 and the first antireflection layer 60 includes, but is not limited to, a stacked structure, a gradient structure, and a hybrid structure of stacked and gradient, and can be prepared by processes such as ALD, PVD and PECVD.
[0096] 8) A second antireflection layer 70 is deposited on the lower surface of the carrier selective contact layer 400, which can be prepared by processes such as ALD, PVD and PECVD;
[0097] 9) The first electrode 30 can be fabricated on the light-receiving surface 11 and the second electrode 40 can be fabricated on the back-lighting surface 12 using processes such as screen printing, thermal evaporation, and electron beam assisted evaporation; wherein, the second electrode 40 can be a grid line electrode or a full back electrode (e.g., Figure 2 As shown, the second electrode 40 is a grid line electrode, such as... Figure 5 As shown, the second electrode 40 is a full-back electrode.
[0098] Thirdly, embodiments of this application also provide a solar cell module, including the solar cell provided in any of the above embodiments.
[0099] It is understood that the solar cell module provided in this application embodiment, by configuring the above-mentioned solar cell, includes the above-mentioned passivation structure. The passivation structure includes a tunneling oxide layer 100, a polycrystalline silicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400. By stacking the polycrystalline silicon layer 200 on one side of the tunneling oxide layer 100, then stacking the metal oxide layer 300 on the side of the polycrystalline silicon layer 200 opposite to the tunneling oxide layer 100, and finally stacking the carrier selective contact layer 400 on the side of the metal oxide layer 300 opposite to the polycrystalline silicon layer 200 to form a passivation structure, the thickness of the polycrystalline silicon layer 200 can be reduced, parasitic absorption can be reduced, and the metal electrode can be prevented from being sintered too deeply and damaging the tunneling oxide layer 100, thereby reducing current loss and improving the efficiency of the solar cell.
[0100] Fourthly, embodiments of this application also provide a solar cell system, including the solar cell or solar cell module provided in any of the above embodiments.
[0101] It is understood that the solar cell system provided in this application embodiment, by configuring the above-mentioned solar cell, includes the above-mentioned passivation structure. The passivation structure includes a tunneling oxide layer 100, a polycrystalline silicon layer 200, a metal oxide layer 300, and a carrier selective contact layer 400. By stacking the polycrystalline silicon layer 200 on one side of the tunneling oxide layer 100, then stacking the metal oxide layer 300 on the side of the polycrystalline silicon layer 200 opposite to the tunneling oxide layer 100, and finally stacking the carrier selective contact layer 400 on the side of the metal oxide layer 300 opposite to the polycrystalline silicon layer 200 to form a passivation structure, the thickness of the polycrystalline silicon layer 200 can be reduced, parasitic absorption can be reduced, and the metal electrode can be prevented from being sintered too deeply and damaging the tunneling oxide layer 100, thereby reducing current loss and improving the efficiency of the solar cell.
[0102] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.
[0103] It should be understood that this application is not limited to the precise structures described above and shown in the appendix, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A passivation structure, characterized in that, The passivation structure includes a tunneling oxide layer (100), a polysilicon layer (200), a metal oxide layer (300), and a carrier-selective contact layer (400). The polysilicon layer (200) is stacked on one side of the tunneling oxide layer (100), the metal oxide layer (300) is stacked on the side of the polysilicon layer (200) facing away from the tunneling oxide layer (100), and the carrier selective contact layer (400) is stacked on the side of the metal oxide layer (300) facing away from the polysilicon layer (200).
2. The passivation structure according to claim 1, characterized in that, The metal oxide layer (300) includes at least one of the following: titanium dioxide layer, zinc oxide layer, tantalum pentoxide layer, niobium pentoxide layer, cadmium oxide layer, scandium trioxide layer, barium oxide layer, tin dioxide layer, and magnesium oxide layer; And / or, the thickness of the metal oxide layer (300) is 2 nm to 30 nm.
3. The passivation structure according to claim 2, characterized in that, The carrier selective contact layer (400) includes at least one of a lithium fluoride layer and a magnesium fluoride layer; And / or, the thickness of the carrier selection contact layer (400) is 1 nm to 10 nm.
4. The passivation structure according to claim 1, characterized in that, The metal oxide layer (300) includes at least one of the following: molybdenum trioxide layer, vanadium pentoxide layer, tungsten trioxide layer, nickel oxide layer, cuprous oxide layer, chromium trioxide layer, cobalt oxide layer, and rhenium trioxide layer; And / or, the thickness of the metal oxide layer (300) is 5 nm to 30 nm.
5. The passivation structure according to claim 4, characterized in that, The carrier selective contact layer (400) includes at least one of a molybdenum trioxide layer, a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid layer, and a cuprous sulfide layer. And / or, the thickness of the carrier selection contact layer (400) is 1 nm to 10 nm.
6. The passivation structure according to any one of claims 1 to 5, characterized in that, The polycrystalline silicon layer (200) contains phosphorus. And / or, the thickness of the polycrystalline silicon layer (200) is 20 nm to 100 nm.
7. The passivation structure according to any one of claims 1 to 5, characterized in that, The tunneling oxide layer (100) includes at least one of a silicon dioxide layer and a silicon oxynitride layer; And / or, the thickness of the tunneling oxide layer (100) is 0.5 nm to 3 nm.
8. A solar cell, characterized in that, The substrate (10) includes a substrate (10) and a passivation structure as described in any one of claims 1 to 7, wherein the substrate (10) has a light-receiving surface (11) and a back-lighting surface (12), and the tunneling oxide layer (100) is stacked on the back-lighting surface (12) on the side opposite to the polysilicon layer (200).
9. The solar cell according to claim 8, characterized in that, It also includes a P-type emitter (20), a first electrode (30), and a second electrode (40), wherein the P-type emitter (20) is stacked on the light-receiving surface (11); The first electrode (30) is in electrical contact with the P-type emitter (20), and the second electrode (40) is in electrical contact with the carrier selective contact layer (400).
10. The solar cell according to claim 9, characterized in that, It also includes a passivation layer (50) and a first antireflection layer (60), wherein the passivation layer (50) is stacked on the side of the P-type emitter (20) facing away from the substrate (10), and the first antireflection layer (60) is stacked on the side of the passivation layer (50) facing away from the substrate (10).
11. The solar cell according to claim 9, characterized in that, It also includes a second anti-reflection layer (70), which is stacked on the side of the carrier selection contact layer (400) facing away from the substrate (10).
12. The solar cell according to any one of claims 9 to 11, characterized in that, The second electrode (40) is a grid line electrode or a full back electrode.
13. A solar cell module, characterized in that, Including the solar cell as described in any one of claims 8 to 12.
14. A solar cell system, characterized in that, It includes the solar cell as described in any one of claims 8 to 12 or the solar cell module as described in claim 13.