Semiconductor wafer multi-stage gradient cooling disc
By designing a multi-level gradient cooling pad for semiconductor wafers, combining water cooling and electric cooling, the problem of excessive temperature gradient during wafer thermal processing was solved, achieving multi-level temperature regulation and uniform cooling, and improving the chip's structural and electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGSU SEMIPOWER TECH CO LTD
- Filing Date
- 2026-05-25
- Publication Date
- 2026-08-04
AI Technical Summary
In existing technologies, the temperature of wafers cannot be controlled in a timely and effective manner during the heating process, resulting in excessive temperature gradients, which cause thermal stress and thermal deformation, affecting the integrity of the chip structure and its electrical performance.
A multi-level gradient cooling disk for semiconductor wafers is designed. Through a combination of a base frame, a cooling frame, and a partition frame, combined with water-cooled pipes and electric cooling pipes, multi-level temperature regulation and uniform cooling are achieved. The wafer position is adjusted and distributed by the design of the winding tube and spacer ring.
It achieves effective temperature control of multiple wafers, reduces temperature gradients, prevents thermal stress and thermal deformation, and improves the structural integrity and electrical performance of the chip.
Smart Images
Figure CN224596905U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of wafer cooling device technology, specifically to a multi-level gradient cooling plate for semiconductor wafers. Background Technology
[0002] In the semiconductor manufacturing process, wafer cooling has a crucial impact on product quality and production efficiency. As chip integration continues to increase and feature sizes continue to shrink, semiconductor manufacturing processes place increasingly stringent demands on the precision of temperature control.
[0003] During critical process steps such as photolithography, etching, deposition, and ion implantation, the wafer surface undergoes extremely intense thermal processes, releasing a large amount of heat energy. If this heat cannot be managed in a timely and effective manner, it will cause a significant temperature gradient inside the wafer. An excessively large temperature gradient can easily lead to thorny problems such as thermal stress and thermal deformation, which will damage the structural integrity of the chip and severely interfere with its electrical performance. Utility Model Content
[0004] Technical problems to be solved
[0005] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a multi-level gradient cooling disk for semiconductor wafers, which can effectively solve the problems in the existing technology.
[0006] Technical solution
[0007] To achieve the above objectives, this utility model provides the following technical solution:
[0008] This utility model provides a multi-level gradient cooling pad for semiconductor wafers, including a base frame and a cooling frame. The base frame and the cooling frame are stacked and fixedly connected. A partition frame is fixedly attached to the top of the base frame, and a cover plate is fixedly attached to the top of the partition frame. Radial and annular partition grooves are opened through the top of the base frame. Multiple sets of connecting holes are opened through the middle of the base frame, and a spiral groove is opened in the middle of the base frame, with a winding tube fixed in the groove. An electric cooling tube is fixed to the top of the cooling frame, and a spacer ring is fixed to the side wall of the partition frame.
[0009] Furthermore, one end of the electric cooling tube is connected to the electrical component, and the electric cooling tube has a spiral wound structure.
[0010] Furthermore, multiple sets of the annular partition grooves are concentrically formed, and multiple sets of the connecting holes are provided.
[0011] Furthermore, both ends of the spiral tube are connected to the water-cooling pipe installed in the bottom frame, and the water-cooling pipe serves as the medium inlet and outlet pipe.
[0012] Furthermore, multiple sets of the spacer rings are fixed at equal intervals on the inner sidewall of the partition frame, and the cross-section of each set of spacer rings is a right trapezoid with a sloping bottom, and a slot is provided in the middle of each set of spacer rings.
[0013] Furthermore, the cover plate has multiple sets of air holes inside.
[0014] Beneficial effects
[0015] The technical solution provided by this utility model has the following advantages compared with the known public technology:
[0016] This utility model, through the combination structure of a bottom frame, a cooling frame, a partition frame, and a cover plate, allows users to place multiple wafers within the spacer ring to achieve a spaced distribution function. Therefore, when the bottom structure is cooled, the temperature distribution within the partition frame varies due to the different distances between the interior and the bottom frame and the cooling frame. Users can adjust the wafer position distribution as needed to achieve multi-level temperature adjustment and can cool multiple wafers simultaneously.
[0017] In this device, through the structure of the bottom frame and the cooling frame, the user can first connect the water-cooling pipe at the bottom with the internal spiral tube to achieve the cooling function, and the cooling is dissipated to the top through the partition groove. The cooling frame structure at the bottom can further cool through the electrical components and the electric cooling pipe structure to reduce the temperature inside the partition frame and meet the usage requirements. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the structure of this utility model;
[0020] Figure 2 This is a structural exploded view of the separator frame and cover plate of this utility model;
[0021] Figure 3 This is an exploded view of the structure of this utility model;
[0022] Figure 4 This is a cross-sectional view of the bottom frame of this utility model.
[0023] The labels in the diagram represent: 1. Base frame; 11. Water-cooled pipe; 12. Spiral wound pipe; 13. Divider groove; 14. Connecting hole; 2. Cooling frame; 21. Electrical components; 22. Electric cooling pipe; 3. Divider frame; 31. Spacer ring; 4. Cover plate. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.
[0025] The present invention will be further described below with reference to the embodiments.
[0026] Example: A multi-level gradient cooling pad for semiconductor wafers, as shown in the attached figure. Figure 1 - Appendix Figure 4 The system includes a base frame 1 and a cooling frame 2, which are stacked and fixedly connected. A partition frame 3 is fixedly attached to the top of the base frame 1, and a cover plate 4 is fixedly attached to the top of the partition frame 3. A radial and annular partition groove 13 is opened through the top of the base frame 1. Multiple sets of connecting holes 14 are opened through the middle of the base frame 1, and a spiral groove is opened in the middle of the base frame 1. A winding tube 12 is fixed in the groove. An electric cooling tube 22 is fixed to the top of the cooling frame 2. A spacer ring 31 is fixed to the side wall of the partition frame 3.
[0027] One end of the electrocooling tube 22 is connected to the electrical component 21, and the electrocooling tube 22 has a spiral wound structure. By setting a combination structure of bottom frame 1, cooling frame 2, partition frame 3 and cover plate 4, the user can place multiple wafers in the spacer ring 31 to achieve the function of spaced distribution. Therefore, when the bottom structure is cooled, the temperature distribution in the partition frame 3 is different due to the different distances between the inside and the bottom frame 1 and cooling frame 2. The user can adjust the position distribution of the wafers as needed to achieve the function of multi-level temperature adjustment, and can cool multiple wafers at the same time.
[0028] Multiple sets of annular partition grooves 13 are concentrically formed, and multiple sets of connecting holes 14 are provided. Both ends of the winding tube 12 are connected to the water-cooling tube 11 installed in the bottom frame 1, and the water-cooling tube 11 serves as the medium inlet and outlet tubes. Multiple sets of spacer rings 31 are equidistantly fixed on the inner side wall of the partition frame 3, and the cross-section of each set of spacer rings 31 is a right trapezoid with a sloping bottom, and a slot is provided in the middle of each set of spacer rings 31. Multiple sets of air holes are provided inside the cover plate 4. Through the structure of the bottom frame 1 and the cooling frame 2, the user can first connect the water-cooling tube 11 at the bottom with the winding tube 12 inside to achieve the cooling function, and the cooling is dissipated to the top through the partition grooves 13. The cooling frame 2 at the bottom can be cooled again through the electrical components 21 and the electric cooling tube 22, reducing the temperature inside the partition frame 3 to meet the requirements of use.
[0029] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this utility model.
Claims
1. A semiconductor wafer multi-stage gradient cooling disc, characterized in that, The system includes a base frame (1) and a cooling frame (2), which are stacked and fixedly connected. A partition frame (3) is fixedly attached to the top of the base frame (1), and a cover plate (4) is fixedly attached to the top of the partition frame (3). A radial and annular partition groove (13) is opened through the top of the base frame (1). Multiple sets of connecting holes (14) are opened through the middle of the base frame (1). A spiral groove is opened in the middle of the base frame (1), and a winding tube (12) is fixed in the groove. An electric cooling tube (22) is fixed to the top of the cooling frame (2), and a spacer ring (31) is fixed to the side wall of the partition frame (3).
2. The multi-stage gradient cooling disc for semiconductor wafer according to claim 1, wherein, One end of the electric cooling tube (22) is connected to the electrical component (21), and the electric cooling tube (22) has a spiral wound structure.
3. The multi-stage gradient cooling disc for semiconductor wafer according to claim 1, wherein, The annular partition groove (13) is concentrically formed in multiple sets, and the connecting hole (14) is provided in multiple sets.
4. The multi-stage gradient cooling disc for semiconductor wafer according to claim 1, wherein, Both ends of the winding tube (12) are connected to the water cooling tube (11) installed in the bottom frame (1), and the water cooling tube (11) serves as the medium inlet and outlet tube.
5. The multi-stage semiconductor wafer cooling disk of claim 4, wherein, Multiple sets of spacer rings (31) are fixed at equal intervals on the inner sidewall of the partition frame (3), and the cross-section of each set of spacer rings (31) is a right trapezoid with a sloping bottom, and a hole or groove is provided in the middle of each set of spacer rings (31).
6. The multi-stage gradient cooling disc for semiconductor wafer according to claim 1, wherein, The cover plate (4) has multiple sets of air holes inside.