Test structure for rewire via overetch problem detection
By designing a test structure for the M1 metal layer, M2 metal layer, and aluminum pad layer, and using redistribution vias and pinouts for leakage current testing, the problem of excessive etching of redistribution vias was solved, improving chip reliability and reducing rework costs in the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GUANGLIWEI (BEIJING) TECHNOLOGY CO LTD
- Filing Date
- 2025-06-27
- Publication Date
- 2026-08-04
AI Technical Summary
The existing technology lacks an effective electrical test structure to detect over-etching of rewiring vias, which can lead to failure of chip metal layer interconnects and fail to ensure chip quality and reliability.
Design a test structure including an M1 metal layer, an M2 metal layer, and an aluminum pad layer, connected by redistribution vias. The M1 and M2 metal layers partially overlap and are not connected by vias. Leakage current testing is performed using pins to quickly detect over-etching issues.
This test structure enables early detection of over-etching of rewiring vias, reducing rework costs and improving chip reliability and lifespan.
Smart Images
Figure CN224596922U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a test structure for detecting over-etching problems in rewiring vias. Background Technology
[0002] In the chip manufacturing process, test structures are used to detect and analyze manufacturing defects to ensure chip quality and reliability. For example... Figure 1 and Figure 2 As shown, in the chip design phase, in order to save costs, as long as the testing needs can be met, the test structure will often not be designed with all metal layers (metal option). The most basic metal interconnect layer (1x Metal / 1xVia) is often only two or three layers, such as M1 metal layer and M2 metal layer. In some cases, the top via and top metal layer are even skipped above the M2 metal layer and directly connected to APL (Aluminum Pad Layer) through RV (Redistribution Via).
[0003] However, the height of APL / RV can reach several thousand nanometers, the height of Top Metal / Top Via can reach several hundred nanometers, and the height of 1xMetal / 1x Via is only tens of nanometers (where "1x" refers to the standard size of the metal interconnect layer). Therefore, there is a possibility that RV Etch may be over-etched, penetrating the M2 metal layer and directly connecting to the M1 metal layer below the M2 metal layer, causing a short circuit and resulting in the failure of the chip metal layer interconnect. However, there is currently no electrical test structure to detect this failure. Utility Model Content
[0004] Therefore, it is necessary to provide a test structure for detecting over-etching issues in redistribution vias, addressing the technical challenges of detecting over-etching problems.
[0005] To achieve the above objectives, this application provides a test structure for detecting over-etching issues in redistribution vias, comprising at least one test unit, wherein the test unit includes: The system comprises an M1 metal layer, an M2 metal layer, and an aluminum pad layer, wherein the M1 metal layer and the M2 metal layer at least partially overlap, and the M1 metal layer and the M2 metal layer are not connected by through-holes. In the overlapping area of the M1 metal layer and the M2 metal layer, the aluminum pad layer is connected to the M2 metal layer through a redistribution via, and the M1 metal layer and the M2 metal layer are respectively connected through pins.
[0006] In some embodiments, the M1 metal layer includes a plurality of first metal lines arranged at intervals, and the plurality of first metal lines are connected through first pins; The M2 metal layer includes a plurality of second metal lines arranged at intervals, and the plurality of second metal lines are connected through second pins; the second metal lines and the first metal lines are at least partially overlapped. The aluminum pad layer includes a plurality of third metal lines arranged at intervals. In the overlapping area of the first metal line and the second metal line, the third metal line is connected to the second metal line through the redistribution via. The line width of both the third metal line and the second metal line is greater than the width of the redistribution via.
[0007] In some embodiments, the first metal wire and the second metal wire are arranged in multiple rows along a first direction, wherein... The first pin and the second pin are comb-shaped pins. Multiple rows of the first metal wires are connected through the comb-shaped pins, and multiple rows of the second metal wires are connected through the comb-shaped pins; and / or, The first metal wires arranged in multiple rows are connected in a serpentine series, and one end is connected through the first pin; the second metal wires arranged in multiple rows are connected in a serpentine series, and one end is connected through the second pin.
[0008] In some embodiments, in the overlapping area of the third metal wire and the second metal wire, the number of rewiring vias is at least two.
[0009] In some embodiments, in the M1 metal layer, at least one fourth metal line is provided between two adjacent first metal lines, and one end of the plurality of fourth metal lines is connected through the first pin; In the M2 metal layer, at least one fifth metal line is provided between two adjacent second metal lines, and several fifth metal lines are connected through a third pin; The fourth metal wire and the fifth metal wire are arranged in an overlapping manner.
[0010] In some embodiments, the width of the fourth metal wire is less than or equal to the width of the first metal wire, and the width of the fifth metal wire is less than or equal to the width of the second metal wire.
[0011] In some embodiments, the test structure for detecting over-etching issues of redistribution vias includes a first test unit and at least one second test unit, wherein the positional offset of the redistribution via in the first test unit is equal to zero, and the positional offset of the redistribution via in the second test unit is greater than zero.
[0012] In some embodiments, the linewidths of the first, second, and third metal lines range from 5 nm to 10 μm, the linewidths of the fourth and fifth metal lines range from 1 nm to 5 μm, the lengths of the first, second, third, fourth, and fifth metal lines range from 10 nm to 0.1 mm, and the spacing ranges from 5 nm to 10 μm.
[0013] In some embodiments, the height of the M1 metal layer and the M2 metal layer is 10nm-1um, and the height of the redistribution via and the aluminum pad layer is 100nm-10um. The aforementioned test structure for detecting over-etching issues in redistribution vias includes at least one test unit. This unit comprises an M1 metal layer, an M2 metal layer, and an aluminum pad layer. The M1 and M2 metal layers at least partially overlap. In the overlapping area, the aluminum pad layer is connected to the M2 metal layer via a redistribution via. The M1 and M2 metal layers are respectively connected via pins. This configuration effectively eliminates interlayer short circuits caused by via connections, ensuring the accuracy of test results, as the M1 and M2 metal layers partially overlap without via connections. Furthermore, the aluminum pad layer connects to the M2 metal layer via a redistribution via in the overlapping area. Therefore, when over-etching occurs in the redistribution via, the overlapping area of the M1 and M2 metal layers is short-circuited. This allows for leakage current testing of the M1 and M2 metal layers via pins, enabling rapid and accurate detection of over-etching issues. By using the above test structure, excessive etching of rewiring vias can be detected and reduced at an early stage, reducing rework costs in the manufacturing process and improving chip reliability and lifespan. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 This is a design table for the most basic metal interconnect layer in related technologies.
[0016] Figure 2 This is a schematic diagram of a test structure in a related technology where the metal interconnect layer has two layers.
[0017] Figure 3This is a schematic diagram of a test structure for detecting excessive etching of rewiring vias, provided in Embodiment 1 of this utility model.
[0018] Figure 4 This is a schematic diagram of a test structure for detecting excessive etching of rewiring vias, provided in Embodiment 2 of this utility model.
[0019] Figure 5 This is a schematic diagram of a test structure for detecting excessive etching of rewiring vias, provided in Embodiment 3 of this utility model.
[0020] Figure 6 This is a schematic diagram of a test structure for detecting excessive etching of rewiring vias, provided in Embodiment 4 of this utility model.
[0021] Figure 7 This is a diagram showing the leakage current test results between the first and second pins in Embodiment 5 of this utility model.
[0022] Figure 8 This is a diagram showing the leakage current test results between the first and third pins in Embodiment 5 of this utility model.
[0023] Figure 9 This is a diagram showing the leakage current test results between the second and third pins in Embodiment 5 of this utility model.
[0024] Figure 10 This is a prediction diagram of the test results of the rewiring via in Embodiment 5 of this utility model under process conditions with multiple different position offset values RV MisAlign. Detailed Implementation
[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0027] The test structure involved in this utility model includes a test unit. Depending on the test conditions, the test structure can consist of a single test unit or a combination of multiple test units. The test unit is described below with reference to the accompanying drawings using three embodiments.
[0028] Example 1 like Figure 3 As shown, this application provides a test structure for detecting over-etching issues in redistribution vias (RV). The test structure includes at least one test unit, which comprises: an M1 metal layer, an M2 metal layer, an RV (Redistribution Via), and an APL (Aluminum Pad Layer).
[0029] To meet testing requirements, the test structure in this application does not include all metal options. The metal interconnect layer 1x Metal includes the M1 metal layer and the M2 metal layer, and skips the Top Via and Top Metal layers. The M2 metal layer is directly connected to the APL layer through the RV via.
[0030] Metal layers M1 and M2 are metal interconnect layers in the back-end processes of chip manufacturing. M1 connects the source, drain, and gate of transistors. M2 spans M1, enabling more complex circuit interconnects. M1 and M2 at least partially overlap; specifically, the metal lines in M1 and M2 have the same size and arrangement in at least some regions. This partial overlap allows for electrical connection between M1 and M2 vias (when redistribution vias are over-etched).
[0031] It should be noted that in this embodiment, no vias (Via) are provided between the M1 and M2 metal layers. Since the M1 and M2 metal layers partially overlap and there are no vias (Via), the interlayer short circuit problem caused by the Via connection is effectively eliminated, ensuring the accuracy of the test results for the RV over-etching problem.
[0032] Redeployment vias (RVs) are vertical conductive vias used to connect the upper APL layer to the lower metal layer. Typically, one or more layers of dielectric material (such as silicon oxide or silicon nitride) are first deposited on the chip surface as interlayer insulation. Then, photolithography is used to define the positions of the RVs on the dielectric layer. Through etching processes (such as dry etching or wet etching) are then used to form the vias, where the position and size of the vias are precisely controlled to ensure alignment with the underlying metal layer. The formed vias are then filled with a conductive material (such as aluminum) to form conductive channels. Finally, chemical mechanical polishing (CMP) is used to remove excess conductive material, making the surface flat and ensuring good interlayer bonding.
[0033] In the overlapping region of the M1 and M2 metal layers, the APL layer is connected to the M2 metal layer via a redistribution via RV. The position offset (RV MisAlign) of the redistribution via RV is 0. The M1 and M2 metal layers are respectively connected via pins. With the above configuration, since the height of the redistribution via RV can reach several thousand nanometers, if there is an over-etching problem with the redistribution via RV, since the height of 1x Metal / 1x Via is only tens of nanometers, the redistribution via RV can easily penetrate the M2 metal layer in the overlapping region and directly connect to the M1 metal layer, causing a short circuit between the M1 and M2 metal layers.
[0034] For details, please refer to Figure 3 The M1 metal layer includes a plurality of first metal lines arranged at intervals, the M2 metal layer includes a plurality of second metal lines arranged at intervals, and the APL layer includes a plurality of third metal lines arranged at intervals. The second metal lines and the first metal lines overlap to form an overlapping region. The overlapping arrangement of the second metal lines and the first metal lines can improve the area utilization of the test structure, optimize the signal path for leakage current detection, and reduce delay and resistance. Of course, in other embodiments, the second metal lines and the first metal lines include overlapping regions and non-overlapping regions to provide greater design flexibility and can be adaptively arranged while meeting design rules. This application is not limited thereto.
[0035] In the overlapping region, the third metal line is connected to the second metal line through the redistribution via RV. Both the third and second metal lines have relatively large linewidths, exceeding the width of the redistribution via RV to match its size. In the overlapping region of the third and second metal lines, there is one redistribution via. In other embodiments, the number of redistribution vias in the overlapping region of the third and second metal lines can be at least two; this application is not limited thereto.
[0036] Several of the first metal lines are connected through the first pin combPin1, and several of the second metal lines are connected through the second pin combPin2. By testing the leakage current between the first pin combPin1 and the second pin combPin2, it is possible to detect whether the redistribution via RV has a short circuit problem due to over-etching.
[0037] In this embodiment, the first metal line and the second metal line are arranged in multiple rows along a first direction. In some embodiments, the first pin combPin1 and the second pin combPin2 are both comb-shaped pins, and the first metal line arranged in multiple rows is connected through the comb-shaped pin, and the second metal line arranged in multiple rows is connected through the comb-shaped pin. In other embodiments, the first pin combPin1 and the second pin combPin2 are both ordinary pins, and one end of the first metal line arranged in multiple rows is connected through the ordinary pin after being serpentinely connected; one end of the second metal line arranged in multiple rows is connected through the ordinary pin after being serpentine connected. By setting the first metal line and the second metal line as multiple rows of metal lines, the random errors in the rewiring via etching process can be better compensated for, and the reliability of the measurement results can be improved. The first direction generally refers to the arrangement direction of the metal lines on the wafer or chip, which can be horizontal (e.g., along the X-axis of the wafer) or vertical (e.g., along the Y-axis of the wafer), depending on the design layout.
[0038] It should be noted that for the test link composed of the first metal wire and the second metal wire, one or two pins can be provided at each end. When one pin is provided at each of the first and second metal wires, two-terminal resistance tests can be performed on the test link in the test unit through the two pins; when two pins are provided at each end, four-terminal Kelvin tests can be performed on the test link in the test unit through the four pins.
[0039] The aforementioned test structure for detecting over-etching issues in redistribution vias involves an APL layer connected to the M2 metal layer via a redistribution via in the overlapping area of the M1 and M2 metal layers. When over-etching occurs in the redistribution via, the overlapping area of the M1 and M2 metal layers short-circuits, allowing leakage current testing by connecting the M1 and M2 metal layers via pins. This enables rapid and accurate detection of over-etching issues. By using this test structure, over-etching of redistribution vias can be detected and reduced at an early stage, reducing rework costs during manufacturing and improving chip reliability and lifespan.
[0040] In this embodiment, the linewidth range of the first, second, and third metal lines is 5nm-10um, the length range is 10nm-0.1mm, and the spacing range is 5nm-10um. The height of the M1 and M2 metal layers is 10nm-1um, and the height of the redistribution via RV and the APL layer is 100nm-10um. To adapt to different conditions, in other embodiments, the line length and linewidth of the first, second, third, fourth, and fifth metal lines, the spacing range of the metal lines, the height of the metal layers, the height of the redistribution via RV, and the height of the APL layer in the above test structure can all be adjusted under the premise of satisfying the design rule.
[0041] Example 2 like Figure 4 The diagram shown is a schematic of the test structure provided in this application for detecting over-etching issues in redistribution vias. During the detection of over-etching issues in redistribution vias using the test structure in Embodiment 1, there may be a process environment where the position of the redistribution via RV is offset. To better detect over-etching issues of the redistribution via RV under different process environments, the following test structure is provided.
[0042] The test structure provided in this embodiment two can refer to the test structure in embodiment one. The position offset (RV MisAlign) of the redistribution via RV is 0. At this time, the position offset of the redistribution via RV is zero, which can be used to determine the possibility of over-etching when the redistribution via RV does not show offset. The difference between this embodiment and embodiment one is that, specifically, in the M1 metal layer, a fourth metal line is provided between two adjacent first metal lines, and in the M2 metal layer, a fifth metal line is provided between two adjacent second metal lines. The fourth and fifth metal lines overlap, and the size and arrangement of the fourth metal line in the M1 metal layer and the fifth metal line in the M2 metal layer are the same.
[0043] The second metal line has a larger linewidth value, which is greater than the diameter of the redistribution via RV, to match the size of the redistribution via. In this embodiment, neither a redistribution via RV nor a via Via is provided between the fourth and fifth metal lines. The width of the fourth metal line can be less than or equal to the width of the first metal line, and the width of the fifth metal line can be less than or equal to the width of the second metal line. In some embodiments, the width of the fourth metal line is less than the width of the first metal line, and the width of the fifth metal line is less than the width of the second metal line. The first and fourth metal lines in the M1 metal layer are configured with a thick-thin spacing structure (think metal + thin metal), and the corresponding second and fifth metal lines in the M2 metal layer are configured with a thick-thin spacing structure (think metal + thin metal). This not only facilitates the detection of the redistribution via RV position offset but also improves the area utilization of the test structure.
[0044] Meanwhile, the distance between the first and fourth metal lines or the distance between the second and fifth metal lines can be set to a minimum value according to the design rules to limit the OPC (Optical Proximity Correction) correction unit of the first metal line. A finer OPC correction can better compensate for deviations in the photolithography process, and a smaller spacing can further improve detection sensitivity and accuracy.
[0045] In this embodiment, a plurality of the first and fourth metal lines are connected through a first pin combPin1, a plurality of the second metal lines are connected through a second pin combPin2, and a plurality of the fifth metal lines are connected through a third pin combPin3. By testing the leakage current between the first pin combPin1 and the second pin combPin2, as well as the leakage current between the first pin combPin1 and the third pin combPin3, it is possible to analyze whether the rewiring via RV experiences a short circuit due to over-etching in a process environment where no positional displacement occurs.
[0046] By using the above settings, the distance between the first metal lines and the distance between the second metal lines can be increased, making it easier to determine the possibility of over-etching issues with the redistribution vias (RV) under different test environments. When there is no positional offset in the redistribution vias, and over-etching occurs, the M1 and M2 metal layers can be electrically connected through the vertical redistribution vias (RV) between the first and second metal lines, resulting in leakage current. Since the first and second metal lines, as well as the fourth and fifth metal lines, are all overlapped and there are no redistribution vias (RV) or via connections (Via), interlayer short circuits caused by Via connections are effectively eliminated, ensuring the accuracy of the RV over-etching test results.
[0047] Example 3 like Figure 5 The diagram shown is a schematic of the test structure provided in this application for detecting over-etching of redistribution vias. In order to better detect the over-etching problem of RV redistribution vias under different process environments, another test structure is provided.
[0048] The test structure provided in this embodiment three can refer to the test structure in embodiment two. For any part not mentioned in this embodiment three, please refer to the relevant description in embodiment two. The difference between this embodiment three and embodiment two is that the position offset (RV MisAlign) of the redistribution via RV is 0.5μm. At this time, the redistribution via RV is located at the edge of the second metal line, which can be used to determine the possibility of over-etching under different process environments when the redistribution via RV is offset.
[0049] In this embodiment, a plurality of the first and fourth metal lines are connected through a first pin combPin1, a plurality of the second metal lines are connected through a second pin combPin2, and a plurality of the fifth metal lines are connected through a third pin combPin3. By testing the leakage current between the first pin combPin1 and the second pin combPin2, and the leakage current between the first pin combPin1 and the third pin combPin3, it can be determined whether a short circuit problem occurs due to over-etching when the rewiring via RV shows a positional shift.
[0050] By using the above settings, the distance between the first metal lines and the distance between the second metal lines can be increased, making it easier to determine the possibility of over-etching issues with the redistribution vias (RV) under different test environments. When there is a positional misalignment of the redistribution vias, and over-etching occurs, the M1 and M2 metal layers can be electrically connected through the vertical redistribution vias (RV) between the first and second metal lines, resulting in leakage current. Since the first and second metal lines, as well as the fourth and fifth metal lines, are all overlapped and there are no redistribution vias (RV) or via connections (Via), interlayer short circuits caused by Via connections are effectively eliminated, ensuring the accuracy of the RV over-etching test results.
[0051] Example 4 like Figure 6 The diagram shown is a schematic of the test structure provided in this application for detecting over-etching of redistribution vias. In order to better detect the over-etching problem of RV redistribution vias under different process environments, another test structure is provided.
[0052] The test structure provided in this embodiment three can refer to the test structure in embodiment two. For any aspects not mentioned in this embodiment three, please refer to the relevant descriptions in embodiment two. The difference between this embodiment three and embodiment two is that the position offset (RV MisAlign) of the redistribution via RV is 0.9 μm. At this time, the redistribution via RV is located above the second and fifth metal lines, which can be used to determine the possibility of over-etching under different process environments when the redistribution via RV is offset. The fourth metal line in the M1 metal layer and the fifth metal line in the M2 metal layer have the same size and arrangement. In the M1 metal layer, four fourth metal lines are arranged between adjacent first metal lines. In the M2 metal layer, four fifth metal lines are correspondingly arranged between adjacent second metal lines. The fourth and fifth metal lines overlap. In this embodiment, neither redistribution vias RV nor vias Via are provided between the fourth and fifth metal lines. The width of the fourth metal line can be smaller than the width of the first metal line, and the width of the fifth metal line can be smaller than the width of the second metal line. Setting up multiple fourth and fifth metal lines can be used to control the test environment for dimensions such as hole spacing and metal line spacing of the redistribution vias (RV) of the test structure.
[0053] In this embodiment, a plurality of the first metal lines and the fourth metal lines are connected through a first pin combPin1, a plurality of the second metal lines are connected through a second pin combPin2, and a plurality of the fifth metal lines are connected through a third pin combPin3. By testing the leakage current between the first pin combPin1 and the second pin combPin2, and the leakage current between the first pin combPin1 and the third pin combPin3, it can be determined whether a short circuit problem occurs due to over-etching when the rewiring via RV shows a positional misalignment.
[0054] In this embodiment, in the overlapping area of the third metal line and the second metal line, the number of redistribution vias can be at least two. When the number of redistribution vias increases, the detection sensitivity of the over-etching problem is higher and the accuracy is higher.
[0055] The above settings increase the distance between the first and second metal lines and allow for better control over the dimensional testing environment, such as the spacing between redistribution vias, facilitating the assessment of the likelihood of over-etching issues in the redistribution vias (RV) under different testing conditions. Furthermore, because the fourth and fifth metal lines overlap, and the redistribution vias (RV) are located above them, electrical connections can be established between the first and second metal lines, as well as between the fourth and fifth metal lines, vias (RV). Since there are no redistribution vias (RV) or vias (Via) connecting the first and second metal lines, the fourth and fifth metal lines, the interlayer short circuit problem caused by Via connections is effectively eliminated, ensuring the accuracy of the RV over-etching test results. When over-etching occurs, the redistribution vias (RV) may shift position, potentially causing them to penetrate the second metal line and connect directly to the first metal line in the overlapping area, or penetrate the fourth metal line and connect directly to the fifth metal line, resulting in a short circuit between the M1 and M2 metal layers and improving detection sensitivity.
[0056] Example 5 This embodiment provides a test structure for detecting over-etching problems in redistribution vias, including a first test unit and at least one second test unit. In the first test unit, the positional offset of the redistribution via is zero. The first test unit can be the test unit described in Embodiment 1 or Embodiment 2 above. In the second test unit, the positional offset of the redistribution via is greater than zero. The second test unit can be one or more of the test units described in Embodiments 3 and 4. The second test unit can also be a test unit where the positional offset RVMisAlign of the redistribution via RV is any non-zero value between -10μm and 10μm. This application is not limited to this. The second test unit may be located at the edge of the second metal line due to the displacement of the redistribution via RV, or even simultaneously fall on the second metal line and the fifth metal line, to determine the possibility of over-etching problems occurring under different process environments below the redistribution via RV.
[0057] The following describes the testing method for the over-etching problem of rewiring vias using the first test unit as Example 2 and the second test unit as Examples 3 and 4.
[0058] like Figures 7-9 As shown, leakage current was measured between combPin2 / combPin3, combPin2 / combPin1, and combPin3 / combPin1 using the two-end method. Since the first pin (combPin1), the second pin (combPin2), and the third pin (combPin3) are insulated from each other, all three test results should show low leakage current. A high leakage current indicates a short circuit between the corresponding pins. Specifically: First, the test unit (RV MisAlign = 0) in Example 2 is used to determine whether there is a short circuit between the M1 metal layer and the M2 metal layer.
[0059] (1) When the detection result of combPin2 / combPin3 is high leakage current, that is, there is a short circuit problem between combPin2 and combPin3. This may be due to the manufacturing process problem of the M2 metal layer or the alignment problem between the redistribution via RV and the M2 mask, which are not the problems of over-etching discussed in this application.
[0060] (2) The test results of combPin1 / combPin2 show high leakage current, that is, there is a short circuit problem in combPin1 and combPin2. This is most likely caused by excessive RV etching of the redistribution via. In the future, the high leakage current area can be sliced and observed by electron microscopy to further determine whether there is excessive RV etching of the redistribution via.
[0061] (3) The test result of combPin1 / combPin3 is high leakage current, that is, there is a short circuit problem between combPin1 and combPin3. This may be caused by the alignment problem between the redistribution via RV and M2 mask and the over-etching problem of the redistribution via RV. Generally speaking, this is difficult to occur.
[0062] Then, a comprehensive analysis was conducted based on the test units (RV MisAlign≠0) in Examples 3 and 4: (1) If RV MisAlign = 0, the detection result of combPin1 / combPin2 is low leakage current; if RV MisAlign ≠ 0, the detection result of combPin1 / combPin2 is high leakage current. This indicates that when the redistribution via RV falls on the center of the first metal line, there will be no over-etching problem; when the redistribution via RV falls on the edge of the first metal line, there will be an over-etching problem, and vice versa.
[0063] (2) If the detection results of combPin1 / combPin2&combPin2 / combPin3&combPin1 / combPin3 are all low leakage current when RV MisAlign = 0 or 0.5 μm, and the detection results of combPin1 / combPin2&combPin2 / combPin3&combPin1 / combPin3 are all high leakage current when RV MisAlign = 0.9 μm, it indicates that the redistribution via RV will cause over-etching problem when it falls above the second metal line and the fifth metal line at the same time.
[0064] The above are just examples illustrating several possibilities for over-etching issues under different environments below redistribution vias (RV). Actual situations require comprehensive analysis based on specific test results.
[0065] Of course, in other embodiments, such as Figure 10 As shown, the test structure for detecting over-etching issues of redistribution vias includes a first test unit and multiple second test units. In the multiple second test units, the redistribution via RV can be set to multiple different position offset values RV MisAlign from negative to positive, thereby comprehensively detecting over-etching issues of redistribution via RV under different process environments.
[0066] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0068] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A test structure for via overetch problem detection for rewiring, characterized by, Includes at least one test unit, said test unit comprising: The system comprises an M1 metal layer, an M2 metal layer, and an aluminum pad layer, wherein the M1 metal layer and the M2 metal layer at least partially overlap, and the M1 metal layer and the M2 metal layer are not connected by through-holes. In the overlapping area of the M1 metal layer and the M2 metal layer, the aluminum pad layer is connected to the M2 metal layer through a redistribution via, and the M1 metal layer and the M2 metal layer are respectively connected through pins.
2. The test structure for detecting over-etching issues in rewiring vias according to claim 1, characterized in that, The M1 metal layer includes a plurality of first metal lines arranged at intervals, and the plurality of first metal lines are connected through first pins; The M2 metal layer includes a plurality of second metal lines arranged at intervals, and the plurality of second metal lines are connected through second pins; the second metal lines and the first metal lines are at least partially overlapped. The aluminum pad layer includes a plurality of third metal lines arranged at intervals. In the overlapping area of the first metal line and the second metal line, the third metal line is connected to the second metal line through the redistribution via. The line width of both the third metal line and the second metal line is greater than the width of the redistribution via.
3. The test structure for via overetch problem detection for rewiring according to claim 2, wherein, The first metal wire and the second metal wire are arranged in multiple rows along the first direction, wherein, The first pin and the second pin are comb-shaped pins. Multiple rows of the first metal wires are connected through the comb-shaped pins, and multiple rows of the second metal wires are connected through the comb-shaped pins; and / or The first metal wires arranged in multiple rows are connected in a serpentine series, and one end is connected through the first pin; the second metal wires arranged in multiple rows are connected in a serpentine series, and one end is connected through the second pin.
4. The test structure for via overetch problem detection for rewiring according to claim 2, wherein, In the overlapping area of the third metal wire and the second metal wire, the number of rewiring vias is at least two.
5. The test structure for via overetch problem detection for rewiring according to claim 2, wherein, In the M1 metal layer, at least one fourth metal line is provided between two adjacent first metal lines, and one end of the plurality of fourth metal lines is connected through the first pin. In the M2 metal layer, at least one fifth metal line is provided between two adjacent second metal lines, and several fifth metal lines are connected through a third pin; The fourth metal wire and the fifth metal wire are arranged in an overlapping manner.
6. The test structure for via overetch problem detection for rewiring according to claim 5, wherein, The width of the fourth metal wire is less than or equal to the width of the first metal wire, and the width of the fifth metal wire is less than or equal to the width of the second metal wire.
7. The test structure for via overetch problem detection for rewiring according to claim 1, wherein, It includes a first test unit and at least one second test unit, wherein in the first test unit, the position offset of the rewiring via is equal to zero, and in the second test unit, the position offset of the rewiring via is greater than zero.
8. The test structure for via overetch problem detection for rewiring according to claim 5, wherein, The linewidth range of the first, second, and third metal lines is 5nm-10um, the linewidth range of the fourth and fifth metal lines is 1nm-5um, the length range of the first, second, third, fourth, and fifth metal lines is 10nm-0.1mm, and the spacing range is 5nm-10um.
9. The test structure for via overetch problem detection for rewiring according to claim 1 or 5, wherein, The height of the M1 metal layer and the M2 metal layer is 10 nm-1 um, and the height of the redistribution via and the aluminum pad layer is 100 nm-10 um.