A semiconductor device measurement structure
By setting positioning lines and pad structures on the top of the wafer, the problem of not being able to accurately determine the cutting position in the prior art is solved, and high efficiency and accuracy of QLC testing of semiconductor devices and optimization of equipment resources are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-08-28
- Publication Date
- 2026-08-04
AI Technical Summary
Existing QLC testing structures for semiconductor devices cannot accurately determine the cutting position, resulting in time consumption and the use of a large amount of equipment resources.
A positioning line is set on the top of the wafer, and a focused ion beam cutting positioning structure is provided on the positioning line. The position to be cut is accurately marked and positioned by the focused ion beam cutting positioning structure, and a first pad and a second pad are set inside the wafer to define the cutting area.
It improves the accuracy and efficiency of quality level testing, reduces the occupation of equipment resources, and simplifies the thickness testing process.
Smart Images
Figure CN224596923U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor testing technology, and more specifically, relates to a semiconductor device measurement structure. Background Technology
[0002] In the manufacturing process of semiconductor devices, quality level checks (QLC) are required on wafers to monitor the stability of the wafer process. During the product development stage, QLC analysis can assist R&D units in improving the process; during the mass production stage, QLC analysis can monitor the stability of the wafer process.
[0003] A semiconductor device requires numerous quality control tests, potentially involving dozens of thickness measurements. Existing QLC test keys are distributed across different locations on the dicing runner. Each measurement requires delayering down to the target layer, resulting in a large number of layers being processed. For example, a semiconductor device might have 28 test items distributed across different dicing runners. Each of these 28 tests requires delayering down to its respective target layer for thickness measurement. Furthermore, the internal structure of the wafer is not visible from the top, making it difficult to accurately locate the dicing position. This process is time-consuming and consumes significant equipment resources. Utility Model Content
[0004] The purpose of this invention is to provide a semiconductor device measurement structure that at least solves the technical problem that existing QLC test structures cannot accurately determine the cutting position.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: A semiconductor device measurement structure, comprising: wafers; A positioning line is set on the top surface of the wafer; a plurality of semiconductor devices are arranged in the wafer along the length of the positioning line; a plurality of focused ion beam cutting positioning structures are arranged in the positioning line; the focused ion beam cutting positioning structures are set at the cutting detection positions of the corresponding semiconductor devices.
[0006] A further improvement of this utility model is that the positioning line is a wavy line.
[0007] A further improvement of this utility model is that the positioning line is a square wave line; it includes several first direction segments and several second direction segments that are connected to each other, and the first direction segments and the second direction segments are perpendicular to each other; the second direction segment serves as a focused ion beam cutting positioning structure.
[0008] A further improvement of this utility model is that the length of the first direction segment is greater than the length of the second direction segment.
[0009] A further improvement of this utility model is that the length of the first directional segment is 0.8-1.2 μm; and the length of the second directional segment is 0.3-0.7 μm.
[0010] A further improvement of this utility model is that the positioning line is a sine wave line; the vertex of the sine wave line serves as a focused ion beam cutting positioning structure. Alternatively, the positioning line can be a triangular wave line; the apex of the triangular wave line serves as the positioning structure for focused ion beam cutting.
[0011] A further improvement of this invention is that: a first pad and a second pad are spaced apart on the top of the wafer; and the plurality of semiconductor devices are arranged between the first pad and the second pad.
[0012] A further improvement of this invention is that: the plurality of semiconductor devices is N, where N is a natural number greater than or equal to 2; the number of focused ion beam cutting positioning structures set in the positioning line is less than or equal to N.
[0013] A further improvement of this invention is that: several semiconductor devices each include a top metal layer; the positioning line is disposed on the side of the top metal layer.
[0014] A further improvement of this utility model is that the positioning line is a metal line.
[0015] Compared with the prior art, this utility model has the following unexpected technical effects: This invention provides a semiconductor device measurement structure, comprising: a wafer; positioning lines disposed on the top surface of the wafer; a plurality of semiconductor devices disposed in the wafer along the length of the positioning lines; a plurality of focused ion beam (FIP) cutting positioning structures disposed in the positioning lines; and the FIP cutting positioning structures being disposed at the corresponding cutting detection positions of the semiconductor devices. In this invention, easily observable positioning lines are provided on the surface of the wafer, and the positioning lines contain a plurality of FIP cutting positioning structures. These FIP cutting positioning structures accurately identify and locate the positions to be cut by the focused ion beam, allowing for the acquisition of complete TEM samples through cutting at the FIP cutting positioning structures.
[0016] Furthermore, the positioning line described in this invention is a wavy line, which is easy to prepare and has easily identifiable peaks as a positioning structure for focused ion beam cutting, facilitating positioning for focused ion beam cutting.
[0017] Furthermore, the positioning line described in this invention is a square wave line, a sine wave line, or a triangular wave line, which is easy to prepare and has easily identifiable peak points as a focusing ion beam cutting positioning structure, facilitating positioning for focusing ion beam cutting.
[0018] Furthermore, in this invention, a first pad and a second pad are spaced apart on the top of the wafer; the plurality of semiconductor devices are arranged between the first pad and the second pad; by setting the first pad and the second pad, the area to be cut by the focused ion beam can be clearly displayed.
[0019] Furthermore, in this invention, the positioning line is located beside the top metal layer, which does not affect the structure of the device itself and serves only as an auxiliary positioning structure.
[0020] Furthermore, in this invention, a first pad and a second pad are set on the top of the wafer, and multiple devices are arranged between the two pads to form a measurement area. A top metal layer is set on the top of the measurement area, and a positioning line is set on the side of the top metal layer. The positioning line is rectangular and wave-shaped, including a first direction segment and a second direction segment. The second direction segment is set at the cutting position of the adjacent device for focused ion beam cutting positioning, thereby solving the problem of difficulty in accurately finding the cutting position from the top of the wafer in the prior art and improving the accuracy of quality level detection.
[0021] Furthermore, in this invention, by performing vertical cutting with a focused ion beam at the second direction segment position, and then processing according to the sample preparation requirements of a transmission electron microscope, samples of each device can be obtained. The thickness dimensions of all required layers can be obtained by measuring them separately. This solves the problem in the prior art that it is necessary to remove layers to the target layer for different test items to perform thickness testing, which involves processing a large number of layers, is time-consuming, and occupies a lot of equipment resources, thus improving the efficiency of quality level detection.
[0022] Furthermore, in this invention, the holes between the metal layers in each device are single holes, which is beneficial for taking transmission electron microscope images, thereby improving the reliability of the quality level detection results. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a top view of a semiconductor device measurement structure according to an embodiment of the present invention; Figure 2 This is a cross-sectional view of a semiconductor device measurement structure according to an embodiment of the present invention; Figure 3 This is a top view of another semiconductor device measurement structure according to an embodiment of the present invention; Figure 4This is a top view of another semiconductor device measurement structure according to an embodiment of the present invention.
[0025] Explanation of reference numerals in the attached figures: 100. Wafer; 101. First pad; 102. Second pad; 2. Top metal layer; 3. Positioning line; 31. First direction segment; 32. Second direction segment. Detailed Implementation
[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the drawings only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0028] In this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.
[0029] Please see Figures 1 to 2 As shown, this embodiment of the present invention provides a semiconductor device measurement structure, including: 100 wafers; A first pad 101 and a second pad 102 are spaced apart on the top of the wafer 100; in one specific embodiment, the first pad 101 and the second pad 102 are metal pads, such as copper pads; in this utility model, the first pad 101 and the second pad 102 are used for positioning.
[0030] N devices (DeviceX) are arranged horizontally along the wafer 100 between the first pad 101 and the second pad 102. iIn one specific embodiment, N is a natural number greater than or equal to 2, where 1 ≤ i ≤ N. In one specific embodiment, the N devices may have the same or different structures.
[0031] A measurement area is formed between the first pad 101 and the second pad 102. A top metal layer 2 is provided on the top of the measurement area. A positioning line 3 is provided on the side of the top metal layer 2. The positioning line 3 is a square wave line, including a first direction segment 31 and a second direction segment 32, which are perpendicular to each other. The second direction segment 32 is set at the cutting position of the adjacent device and is used for focused ion beam (FIB) cutting positioning. The focused ion beam is used to vertically cut at the position of the second direction segment 32, and then processed according to the sample preparation requirements of TEM (Transmission Electron Microscope) to obtain sample X1, sample X2...sample Xn. The thickness of all required layers can be obtained by measuring them respectively.
[0032] In one specific embodiment, the semiconductor device measurement structure provided by this utility model has a first direction segment 31 with a length of 1µm and a second direction segment 32 with a length of 0.5µm. The positioning line 3 is designed to accurately provide the position of the FIB cutting tool based on the position of the first second direction segment 32, the position of the second second direction segment 32, the position of the (n-1)th second direction segment 32, and the position of the (n-1)th second direction segment 32.
[0033] Please see Figure 2 As shown, in one specific embodiment, the semiconductor device measurement structure provided by this utility model includes a top metal layer 2 (Y). n The metal layers include multiple metal layers (including metal); the multiple metal layers are connected by connecting posts.
[0034] In one specific embodiment, the semiconductor device measurement structure provided by this utility model has a single-hole design between the metal layers in each device, which is beneficial for TEM image capture.
[0035] Please see Figure 3As shown, this utility model provides a semiconductor device measurement structure, including: a wafer 100; a first pad 101 and a second pad 102 are spaced apart on the top of the wafer 100, the first pad 101 and the second pad 102 are copper pads used for positioning; five devices (Device X1, Device X2, Device X3, Device X4, Device X5) are arranged between the first pad 101 and the second pad 102 along the horizontal direction of the wafer 100, the five devices have the same structure; a measurement area is formed between the first pad 101 and the second pad 102, and a top metal layer 2 is provided on the top of the measurement area; a positioning line 3 is provided on the side of the top metal layer 2, the positioning line 3 is a sine wave line, and the vertex of the sine wave line is used for focused ion beam cutting positioning; by vertical cutting at the vertex position of the sine wave line by focused ion beam, and then processing according to the sample preparation requirements of transmission electron microscopy, sample X1, sample X2, sample X3, sample X4, and sample X5 are obtained. X5, the thickness of all required layers can be obtained by measuring them separately; each device includes a layered metal layer including the top metal layer 2, and the holes between the metal layers in each device are designed as single holes, which is conducive to taking images with a transmission electron microscope.
[0036] Please see Figure 4 As shown, this utility model provides a semiconductor device measurement structure, including: an 8-inch wafer 100; a first pad 101 and a second pad 102 are spaced apart on the top of the wafer 100, the first pad 101 and the second pad 102 are copper pads used for positioning; three devices (Device X1, Device X2, Device X3) are arranged between the first pad 101 and the second pad 102 along the horizontal direction of the wafer 100, the three devices having different structures; a measurement area is formed between the first pad 101 and the second pad 102, and a top metal layer 2 is provided on the top of the measurement area; a positioning line 3 is provided on the side of the top metal layer 2, the positioning line 3 is a triangular wave line, the vertex of the triangular wave line is used for focused ion beam cutting and positioning; vertical cutting is performed through the vertex position of the focused ion triangular wave line, and then processed according to the sample preparation requirements of transmission electron microscopy to obtain sample X1, sample X2, and sample X3. X3, the thickness of all required layers can be obtained by measuring them separately; each device includes a layered metal layer including the top metal layer 2, and the holes between the metal layers in each device are designed as single holes, which is conducive to taking images with a transmission electron microscope.
[0037] As is known from common technical knowledge, this utility model can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this utility model or its equivalents are included in this utility model.
Claims
1. A semiconductor device metrology structure, characterized by, include: Wafer (100); Positioning line (3) is set on the top surface of wafer (100); a plurality of semiconductor devices are provided in wafer (100) along the length extension direction of the positioning line (3); a plurality of focused ion beam cutting positioning structures are provided in the positioning line (3); the focused ion beam cutting positioning structures are set at the cutting detection position of the corresponding semiconductor device.
2. The semiconductor device metrology structure of claim 1, wherein, The positioning line (3) is a wavy line.
3. The semiconductor device metrology structure of claim 2, wherein, The positioning line (3) is a square wave line; it includes several first direction segments (31) and several second direction segments (32) that are connected to each other. The first direction segments (31) and the second direction segments (32) are perpendicular to each other; the second direction segment (32) serves as a focused ion beam cutting positioning structure.
4. The semiconductor device metrology structure of claim 3, wherein, The length of the first direction segment (31) is greater than the length of the second direction segment (32).
5. The semiconductor device metrology structure of claim 3, wherein, The length of the first directional segment (31) is 0.8-1.2 μm; the length of the second directional segment (32) is 0.3-0.7 μm.
6. A semiconductor device measurement structure according to claim 1, characterized in that, The positioning line (3) is a sine wave line; the vertex of the sine wave line serves as the positioning structure for focused ion beam cutting. Alternatively, the positioning line (3) is a triangular wave line; the vertex of the triangular wave line serves as the positioning structure for focused ion beam cutting.
7. A semiconductor device measurement structure according to claim 1, characterized in that, A first pad (101) and a second pad (102) are spaced apart on the top of the wafer (100); the plurality of semiconductor devices are arranged between the first pad (101) and the second pad (102).
8. The semiconductor device metrology structure of claim 1, wherein, The number of semiconductor devices is N, where N is a natural number greater than or equal to 2; the number of focused ion beam cutting positioning structures set in the positioning line (3) is less than or equal to N.
9. A semiconductor device measurement structure according to claim 1, characterized in that, Several semiconductor devices include a top metal layer; the positioning line (3) is disposed on the side of the top metal layer.
10. A semiconductor device measurement structure according to claim 1, characterized in that, The positioning line (3) is a metal wire.