Semiconductor package structure

Abstract

The utility model relates to a semiconductor packaging structure, including lead frame, base plate, metal circuit layer and semiconductor assembly. Lead frame includes main part, connecting arm and frame part. Main part is placed in the frame part, and connecting arm is arranged at the diagonal of main part and frame part, and can form spacing area between opposite sides. The base plate is arranged on the upper end surface of main part and frame part and is partially filled in the spacing area, and a plurality of first through holes, a plurality of second through holes are distributed and arranged, in which a first conductive column connected with the main part and a second conductive column connected with the connecting arm and the frame part are formed respectively. The metal circuit layer is multiple and is distributed on the base plate and is connected with the first and second conductive columns. The semiconductor assembly is arranged on the metal circuit layer and is provided with a welding part connected with the metal circuit layer. The utility model can inhibit the deformation and warping of the base plate, and can help to solve the problem that the semiconductor assembly is prone to empty welding during packaging and welding operation, which adversely affects signal transmission.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor device packaging technology, and specifically relates to a semiconductor packaging structure. Background Technology

[0002] Existing semiconductor packaging structures, such as Figure 6 As shown, substrate 1 (substrate 1 is semi-solid and can be deformed when pressure is applied) is often used to complete the encapsulation. Figure 6 The package structure shown includes a multilayer substrate 1 and a multilayer metal circuit layer 2 stacked vertically, a semiconductor component 4 disposed on the upper part of the metal circuit layer 2, and a solder mask layer 3 disposed on the side. The substrate 1 is formed by sequentially stacking and bonding rigid insulating materials, with the metal circuit layer 2 disposed between adjacent layers. Through-holes are distributed on the substrate 1, penetrating the thickness direction of the substrate 1. After copper is injected into the through-holes, conductive pillars 5 are formed that are electrically connected to each metal circuit layer 2. The semiconductor component 4 is flip-chip mounted on the uppermost metal circuit layer 2, and an electrical connection is established between the two. The solder mask layer 3 partially covers the substrate 1. Some of the conductive pillars 5 (in the central region) are electrically connected to the semiconductor component 4, and some of the conductive pillars 5 (in the side region) are electrically connected to external devices, and there is also an electrical connection path between the two parts of the conductive pillars 5, thus enabling a signal connection between the semiconductor component 4 and the external device.

[0003] The above-mentioned semiconductor packaging structure adopts a combination of multiple stacked substrates 1 with corresponding metal circuit layers 2 between adjacent substrates 1. Because the more substrates 1 there are, the more likely the substrates 1 will bend during the heating and soldering process due to the difference in glass transition temperature of each substrate material. This can easily cause the solder joints of the semiconductor component 4 to have open solder joints, affecting signal transmission. Utility Model Content

[0004] To overcome the above-mentioned technical problems, this utility model provides a semiconductor packaging structure that uses a single-layer substrate and fills part of the substrate into the lead frame during the molding process, so that the two are firmly bonded together. After heating and welding, it can form a whole and suppress the problem of substrate deformation and warping. This helps to solve the problem that open solder joints are easy to occur in the packaging and welding operation of semiconductor components, which adversely affects signal transmission.

[0005] The technical solution adopted by this utility model to solve its technical problem is: a semiconductor packaging structure, including a lead frame, a substrate, a metal circuit layer, and a semiconductor component. The lead frame includes a main body, multiple connecting arms, and an outer frame.

[0006] The main body is placed inside the outer frame, and multiple connecting arms are respectively located at the diagonal points of the main body and the outer frame, which can connect the main body and the outer frame together; a gap area is formed between the four opposite sides of the main body and the outer frame.

[0007] A substrate is disposed on the upper surface of the main body and the outer frame, and a portion of the substrate is filled within the spacing area. Multiple first through holes and multiple second through holes, all extending vertically, are distributed on the substrate. A first conductive post electrically connected to the main body is formed within each of the first through holes. A second conductive post electrically connected to the connecting arm and the outer frame is formed within each of the second through holes.

[0008] There are multiple metal circuit layers, all distributed on the upper surface of the substrate, and each metal circuit layer is electrically connected to the corresponding first conductive post and second conductive post.

[0009] The semiconductor component is disposed on a metal circuit layer. Multiple solder joints are provided on the semiconductor component, and these solder joints are electrically connected to the corresponding metal circuit layers.

[0010] Optionally, there are four pairs of connecting arms, evenly distributed at the four opposite corners of the main body and the outer frame. The pair of connecting arms at the same opposite corner are arranged perpendicularly to each other, so as to make the connection between the main body and the outer frame more robust and reliable.

[0011] Optionally, the outer corners of the outer frame are formed as outer chamfered surfaces, and the inner corners are formed as inner chamfered surfaces, and the extension length of the inner chamfered surface is not greater than 1 / 2 of the extension length of the outer chamfered surface.

[0012] A strip-shaped inclined groove extending along its length is formed at the lower part of the outer chamfer surface, and a radial channel extending diagonally is formed at the lower part of the inner chamfer surface. At the same time, through holes extending vertically are formed at the four corners of the outer frame, and the lower ends of the through holes are connected to the strip-shaped inclined groove and the radial channel.

[0013] Optionally, a straight groove is formed at the center of the lower end face on each of the four sides / frame edges of the outer frame. The straight groove extends through the inner and outer sides of the outer frame.

[0014] Optionally, the thickness of the main body is the same as the thickness of the outer frame. The thickness of the connecting arm is no more than 1 / 2 of the thickness of the main body.

[0015] Optionally, a V-shaped groove is formed on the inner side of the outer frame portion at the middle position, and the V-shaped groove corresponds to the upper part of the connecting arm. The V-shaped groove can divide the inner side of the outer frame portion into an upper first surface and a lower second surface, with the first surface being more outward than the second surface.

[0016] Optionally, a solder resist layer is formed on the outer edge of the upper end face of the substrate, and the solder resist layer is exposed outward relative to the metal circuit layer.

[0017] Optionally, it also includes a molding compound. The molding compound covers the semiconductor components, metal circuit layers, and solder mask layers on the substrate, and exposes the lower end face of the main body, the lower end face of the connecting arm, and the lower surface of the outer frame to the outside.

[0018] The beneficial effects of this utility model are: This utility model adopts a single-layer substrate and fills part of the substrate into the lead frame during the molding process, so that the two are firmly bonded together. After heating and welding, it can form a whole, suppressing the problem of substrate deformation and warping. It helps to solve the problem that open solder joints are easy to occur in the packaging and welding operation of semiconductor components, which adversely affects signal transmission. Attached Figure Description

[0019] Figure 1 This is a top view of the conductor frame structure.

[0020] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure at point AA.

[0021] Figure 3 This is a schematic diagram of the conductor frame from below.

[0022] Figure 4 To Figure 1 A schematic diagram of the optimized structure of the cross-section at point AA.

[0023] Figure 5 for Figure 4 The diagram shows the structure when the scheme is combined with a substrate, etc.

[0024] Figure 6 This is a cross-sectional schematic diagram of an existing semiconductor packaging structure.

[0025] In the figure: 10 Leadframe, 11 Main body, 111 Outer side, 12 Connecting arm, 13 Outer frame, 131 Outer chamfer, 132 Inner chamfer, 1321 Radial channel, 133 Through hole, 134 Straight groove, 135 V-groove, 136 Second surface, 137 First surface, 14 Spacing area; 20, 1 Substrate, 21 First through hole, 22 First conductive post, 23 Second through hole, 24 Second conductive post; 30, 2 Metallic circuit layer; 40, 4 Semiconductor component; 50, 3 Solder mask layer; 60 Molded enclosure; 5 Conductive post. Detailed Implementation

[0026] The structures, proportions, and sizes shown in the accompanying drawings are merely for illustrative purposes and to aid those skilled in the art. They are not intended to limit the scope of this invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of this invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, terms such as "upper," "lower," "front," "rear," and "middle" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.

[0027] like Figures 1 to 5 The semiconductor packaging structure shown includes a lead frame 10, a substrate 20, a metal circuit layer 30, a semiconductor component 40, a solder mask layer 50, and a molding compound 60. The lead frame 10 includes a main body 11, four pairs of connecting arms 12, and an outer frame 13. The main body 11 is placed inside the outer frame 13, and the four pairs of connecting arms 12 are evenly distributed at four diagonal positions between the main body 11 and the outer frame 13, and can connect the main body 11 and the outer frame 13 together.

[0028] The two connecting arms 12 at opposite corners are arranged perpendicularly to each other, providing support in both directions. Spacing areas 14 are formed between the four opposite sides of the main body 11 and the outer frame 13.

[0029] The substrate 20 is disposed on the upper end surface of the main body 11 and the outer frame 13, and a portion of the substrate 20 is filled in the spacing area 14.

[0030] A plurality of first through holes 21 and a plurality of second through holes 23, all extending vertically, are distributed on the substrate 20. Both the first through holes 21 and the second through holes 23 are formed by laser drilling. A first conductive post 22, electrically connected to the main body 11, is formed within the first through hole 21. A second conductive post 24, electrically connected to the connecting arm 12, is formed within some of the second through holes 23, and a second conductive post 24, electrically connected to the outer frame 13, is also formed within some of the second through holes 23.

[0031] Multiple metal circuit layers 30 are distributed on the upper surface of the substrate 20, and each metal circuit layer 30 is electrically connected to a corresponding first conductive post 22 and second conductive post 24. The semiconductor component 40 is disposed on the metal circuit layers 30. Multiple solder joints are provided on the semiconductor component 40, and each solder joint is electrically connected to a corresponding metal circuit layer 30. Therefore, some first conductive posts 22 are configured corresponding to one metal circuit layer 30, establishing an electrical connection between that metal circuit layer 30 and the semiconductor component 40; other first conductive posts 22 are configured corresponding to another metal circuit layer 30, establishing an electrical connection between that metal circuit layer 30 and the semiconductor component 40; and so on, so that multiple metal circuit layers 30 are electrically connected to the semiconductor component 40 respectively. The aforementioned features can be implemented according to the integrated circuit layout design structure, and can be achieved with reference to existing technology; they are not considered technical innovations of this application.

[0032] The second conductive post 24 on the connecting arm 12 is configured corresponding to one or more of the metal circuit layers 30; the second conductive post 24 on the outer frame portion 13 is also configured corresponding to one or more of the metal circuit layers 30. Some of the metal circuit layers 30 may be configured corresponding to both the connecting arm 12 and the outer frame portion 13; alternatively, some of the metal circuit layers 30 may be configured separately on the connecting arm 12 and separately on the outer frame portion 13.

[0033] In summary, the number of metal line layers 30 corresponding to the main body 11, the number of metal line layers 30 corresponding to the connecting arms 12, and the number of metal line layers 30 corresponding to the outer frame 13 all need to be determined based on the actual circuit structure of the specifically designed semiconductor device. Furthermore, whether there is a situation where the metal line layers 30 corresponding to the main body 11, the connecting arms 12, and the outer frame 13 partially share a certain metal line layer 30 also needs to be determined based on the actual circuit structure of the specifically designed semiconductor device.

[0034] A solder resist layer 50 is formed on the outer edge of the upper surface of the substrate 20, and the solder resist layer 50 is exposed upwards / outwards relative to the metal circuit layer 30. The molding compound 60 covers the semiconductor component 40, the metal circuit layer 30, and the solder resist layer 50 on the substrate 20, and exposes the lower surface of the main body 11, the lower surface of the connecting arm 12, and the lower surface of the outer frame 13 to the outside.

[0035] like Figure 1 , Figure 3As shown, the outer corners of the outer frame portion 13 are formed as outer chamfered surfaces 131, and the inner corners are formed as inner chamfered surfaces 132, with the extension length of the inner chamfered surface 132 not exceeding half the extension length of the outer chamfered surface 131. Both the outer chamfered surface 131 and the inner chamfered surface 132 are vertical surfaces. A strip-shaped inclined groove 1311 extending in the same direction as its length extension is formed at the lower part of the outer chamfered surface 131, and a radial channel 1321 extending diagonally is formed at the lower part of the inner chamfered surface 132. Through holes 133 extending vertically are formed at the four corners of the outer frame portion 13, and the lower ends of the through holes 133 communicate with the strip-shaped inclined groove 1311 and the radial channel 1321. A straight recessed groove 134 is formed on the four sides of the outer frame portion 13, at the center of the lower end face. The straight groove 134 extends through the inner and outer sides of the outer frame 13.

[0036] like Figure 4 , Figure 5 As shown, the thickness of the main body 11 is the same as the thickness of the outer frame 13. The thickness of the connecting arm 12 is no greater than half the thickness of the main body 11. A V-shaped groove 135 is formed on the inner side surface of the outer frame 13 at the middle position, and the V-shaped groove 135 corresponds to the upper part of the connecting arm 12. The V-shaped groove 135 divides the inner side surface of the outer frame 13 into an upper first surface 137 and a lower second surface 136, and the first surface 137 is outward (i.e., to the left or right) relative to the second surface 136.

[0037] Compared with the prior art, this utility model uses a single-layer substrate 20 to match the lead frame 10. During the molding process, the substrate 20 is partially filled into the spacing area 14 formed on the lead frame 10, so that the substrate 20 is firmly bonded to the connecting arm 12, the outer frame 13, and the main body 11, and becomes a rigid whole after the heating and welding process. Because a single-layer substrate 20 is used, the substrate 20 will not deform or warp during the heating and welding process, which can effectively suppress the occurrence of open solder joints in the semiconductor component 40 during the packaging and welding operation, ensure the reliability and stability of signal transmission, and improve the yield of the packaging process.

[0038] By providing the strip-shaped inclined groove 1311 on the outer chamfered surface 131 and the radial channel 1321 on the inner chamfered surface 132, and connecting the two to the through hole 133 located at the corner of the outer frame portion 13, the tightness and firmness of the connection between the substrate 20 (in a semi-solid state) and the outer frame portion 13 at the four corners can be improved, which helps to effectively prevent cracking and bending of the substrate 20 and the outer frame portion 13 at the corners. Simultaneously, by matching the straight groove 134, on the one hand, the firmness and reliability of the connection between the substrate 20 and the four frame edges of the outer frame 13 can be improved, and the tightness and firmness of the connection between the substrate 20 (in a semi-solid state) and the outer frame 13 after pressure deformation can be further improved, making the connection between the substrate 20 and the outer frame 13 at the corner positions more firm and reliable; on the other hand, it can also effectively release the internal stress generated when the substrate 20 is pressure-flowed between the frame edge of the outer frame 13 and the outer surface 111 of the main body 11, and can effectively suppress the occurrence of large internal stress inside the lead frame 10 after heat welding, thus helping to ensure the yield of the package.

[0039] The design structure of the V-groove 135 can also improve the tightness and firmness of the connection between the substrate 20 (in a semi-solid state) and the outer frame 13 after being deformed by pressure, making the connection between the substrate 20 and the outer frame 13 more firm and reliable.

[0040] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit it. Many aspects of this utility model can be improved without departing from the overall concept. Those skilled in the art can modify or change the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A semiconductor packaging structure, comprising a substrate (20), a metal circuit layer (30), and a semiconductor component (40); the semiconductor component (40) is disposed on the metal circuit layer (30); a plurality of solder joints are provided on the semiconductor component (40), and the solder joints are electrically connected to the metal circuit layer (30); characterized in that: It also includes a conductor frame (10); the conductor frame (10) includes a main body (11), multiple connecting arms (12) and an outer frame (13); the main body (11) is placed inside the outer frame (13), and the multiple connecting arms (12) are respectively located at the diagonal positions of the main body (11) and the outer frame (13), which can connect the main body (11) and the outer frame (13) together; a spacing area (14) is formed between the four opposite sides of the main body (11) and the outer frame (13). A substrate (20) is provided on the upper end face of the main body (11) and the outer frame (13), and part of the substrate (20) is filled in the spacing area (14); a plurality of first through holes (21) and a plurality of second through holes (23) extending in the vertical direction are distributed on the substrate (20); a first conductive post (22) electrically connected to the main body (11) is formed in each of the plurality of first through holes (21); a second conductive post (24) electrically connected to at least part of the connecting arm (12) and the outer frame (13) is formed in each of the plurality of second through holes (23). There are multiple metal circuit layers (30) distributed on the upper surface of the substrate (20). Each metal circuit layer (30) is electrically connected to the corresponding first conductive post (22) and second conductive post (24). Each metal circuit layer (30) has a corresponding matching solder part and forms an electrical connection relationship.

2. The semiconductor packaging structure according to claim 1, characterized in that: There are four pairs of connecting arms (12), which are evenly distributed at the four opposite corners of the main body (11) and the outer frame (13); the arrangement direction between a pair of connecting arms (12) at the same opposite corner is relatively perpendicular.

3. The semiconductor packaging structure according to claim 1, characterized in that: The outer corner of the outer frame (13) is formed as an outer chamfered surface (131), and the inner corner is formed as an inner chamfered surface (132). The extension length of the inner chamfered surface (132) is not greater than 1 / 2 of the extension length of the outer chamfered surface (131). A strip-shaped inclined groove (1311) extending along its length direction is formed at the lower part of the outer chamfered surface (131), and a radial channel (1321) extending along the diagonal direction is formed at the lower part of the inner chamfered surface (132). Through holes (133) extending vertically are formed at the four corners of the outer frame (13), and the lower end of the through holes (133) is connected to the strip groove (1311) and the radial channel (1321).

4. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that: A straight groove (134) is formed on the four sides of the outer frame (13) at the center of the lower end face; the straight groove (134) penetrates the inner and outer sides of the outer frame (13).

5. The semiconductor packaging structure according to claim 1, characterized in that: The thickness of the main body (11) is the same as the thickness of the outer frame (13); the thickness of the connecting arm (12) is not greater than 1 / 2 of the thickness of the main body (11).

6. The semiconductor packaging structure according to claim 5, characterized in that: A V-shaped groove (135) is formed on the inner side of the outer frame (13) at the middle position; the V-shaped groove (135) can divide the inner side of the outer frame (13) into an upper first surface (137) and a lower second surface (136), and the first surface (137) is outward relative to the second surface (136).

7. The semiconductor packaging structure according to claim 1, characterized in that: A solder resist layer (50) is formed on the outer edge of the upper end face of the substrate (20) and the solder resist layer (50) is exposed relative to the metal circuit layer (30).

8. The semiconductor packaging structure according to claim 7, characterized in that: It also includes a molding compound (60); the molding compound (60) covers the semiconductor components (40), the metal circuit layer (30) and the solder mask layer (50) on the substrate (20), and exposes the lower end face of the main body (11), the lower end face of the connecting arm (12) and the lower surface of the outer frame (13) to the outside.

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