Multichannel signal acquisition device

Abstract

The utility model relates to signal acquisition technical field especially, it relates to a kind of multichannel signal acquisition equipment, through multichannel connecting plate integration multiple acquisition card, when needing to transmit multiple sensor data simultaneously, through the channel selection in acquisition card, signal amplification, filtering and ADC conversion etc. Circuit structure handles the data of acquisition, to improve the reliability of subsequent sensor data transmission and processing, improve the processing efficiency of multi-source data, avoid the technical problem that the acquisition processing mode of multiple parameters such as micro-strain, vibration signal, displacement and temperature of building in prior art is relatively single, and the expansion difficulty is greater.

Description

Technical Field

[0001] This utility model relates to the field of signal acquisition technology, and in particular to a multi-channel signal acquisition device. Background Technology

[0002] In bridge construction projects, it is necessary to capture the micro-strain and vibration characteristics of the structure in real time under loads (vehicles, wind vibration), temperature changes, etc. Traditional static sensors cannot meet the dynamic accuracy requirements. Moreover, during the monitoring process, multiple parameters such as strain, vibration, displacement, and temperature need to be collected simultaneously to comprehensively assess the health of the structure.

[0003] Existing dynamic signal monitoring equipment typically collects sensor data through motherboard cards. A single sensor only collects one or two data points, and the acquisition board is fixed in position and cannot be replaced. As a result, sensor expansion can only be achieved by external cascading to expand the acquisition channels. This method not only requires adding multiple monitoring devices, but also additional switches and clock synchronization boxes, which increases costs and maintenance difficulty.

[0004] The above content is only used to help understand the technical solution of this utility model and does not represent an admission that the above content is prior art. Utility Model Content

[0005] The main purpose of this utility model is to provide a multi-channel signal acquisition device, which aims to solve the technical problem that the existing technology has a relatively simple method for acquiring and processing various parameters such as micro-strain, vibration signals, displacement and temperature of buildings, and is difficult to expand.

[0006] To achieve the above objectives, this utility model provides a multi-channel signal acquisition device, specifically comprising: The system comprises a multi-channel connection board, at least one acquisition card, a switch, and a motherboard, wherein the acquisition card, the multi-channel connection board, the switch, and the motherboard are connected in sequence. The connection board has at least two sets of card slots. The first set of card slots is used to connect to the acquisition card, and the second set of card slots is used to connect to the motherboard. The connection board also has at least two sets of network ports. The first set of network ports is used to connect to the switch, and the second set of network ports is used to connect the switch and the motherboard.

[0007] Optionally, the acquisition card is used to acquire or receive valid sensing signals of at least one data dimension, and process the valid sensing signals to obtain strain data that the motherboard can process.

[0008] Optionally, the acquisition card includes at least a channel selection module, a signal amplification module, a filtering module, an adjustable amplification module, an ADC driver module, and an FPGA processing module, wherein the channel selection module, the signal amplification module, the filtering module, the ADC driver module, and the FPGA processing module are connected in sequence. The channel selection module is used to switch the bridge connection mode in order to receive valid sensing signals; The signal amplification module is used to amplify the effective sensing signal; The filtering module is used to filter the amplified effective sensing signal to obtain a sensing signal in a specific frequency band. The adjustable amplification module is used to adjust the signal amplitude of the sensing signal to obtain the target sensing signal; The ADC driving module is used to sample the target sensing signal to obtain target strain data; The FPGA processing module is used to drive at least one of the following modules: the channel selection module, the signal amplification module, the filtering module, and the ADC driving module.

[0009] Optionally, the channel selection module includes at least two TMUX4051PWR control chips, which are used to perform positive and negative voltage measurements to switch the bridge connection mode and determine the valid sensing signal. The bridge connection mode includes at least full-bridge input, half-bridge input and 1 / 4 bridge input. Accordingly, during full-bridge input, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_VI5 and ADC_N_IN are turned on. When the half-bridge input is active, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S3 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_REF and ADC_N_IN are turned on. When the 1 / 4 bridge input is connected, the FPGA processing module controls the S2 pin and D pin of the first TMUX4051PWR control chip to connect so that DQ_VI3 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect so that DQ_VI5 and ADC_N_IN are turned on.

[0010] Optionally, the signal amplification module includes at least: an INA821IDGKR control chip, a DAC7311IDGKR control chip, a first ADA4807 control chip, a first resistor, a second resistor, a first capacitor, and a second capacitor; The -IN pin of the INA821IDGKR control chip is connected to the D pin of the first TMUX4051PWR control chip, and the +IN pin of the INA821IDGKR control chip is connected to the D pin of the second TMUX4051PWR control chip. The DAC7311IDGKR control chip, the first ADA4807 control chip, the first resistor, the second resistor, the first capacitor, and the second capacitor together constitute the reference voltage output module of the signal amplification module. The reference voltage output module specifically includes: the first end of the first capacitor, the first end of the second capacitor, and the AVDD pin of the DAC7311IDGKR control chip are respectively connected to a preset power supply; the second ends of the first capacitor and the second end of the second capacitor are grounded; the AVDD pin of the DAC7311IDGKR control chip is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor and the -IN1 pin of the first ADA4807 control chip; the second end of the second resistor is connected to the VOUT1 pin and the +IN2 pin of the first ADA4807 control chip; the VOUT pin of the DAC7311IDGKR control chip is connected to the +IN1 pin of the first ADA4807 control chip; and the VOUT2 pin of the first ADA4807 control chip outputs the reference voltage of the signal amplification module.

[0011] Optionally, the filtering module includes at least: a second ADA4807 control chip, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; In this configuration, the first end of the third resistor is connected to the output of the signal amplification module; the second end of the third resistor is connected to the first end of the fourth resistor and the first end of the third capacitor; the second end of the fourth resistor is connected to the +IN1 pin of the second ADA4807 control chip and the second end of the fourth capacitor; the VOUT1 and -IN1 pins of the second ADA4807 control chip are both connected to the second end of the third capacitor and the first end of the fifth resistor; the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the fifth capacitor; the second end of the sixth resistor is connected to the +IN2 pin of the second ADA4807 control chip; the second end of the fifth capacitor is connected to the VOUT2 and -IN2 pins of the second ADA4807 control chip; the VOUT2 pin of the second ADA4807 control chip serves as the output of the filtering module; the +IN2 pin of the second ADA4807 control chip is connected to the first end of the sixth capacitor; and the second end of the sixth capacitor is grounded.

[0012] Optionally, the adjustable amplification module includes at least: an LTC6910 control chip, a seventh resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an eleventh capacitor; The IN pin of the LTC6910 control chip is connected to the output of the filter module. The first end of the seventh resistor and the first end of the seventh capacitor are grounded. The second end of the seventh resistor and the second end of the seventh capacitor are both connected to the AGND pin of the LTC6910 control chip. The V- pin of the LTC6910 control chip is grounded through the eighth and ninth capacitors connected in parallel. The V+ pin of the LTC6910 control chip is grounded through the tenth and eleventh capacitors connected in parallel. The OUT pin of the LTC6910 control chip serves as the output of the adjustable amplifier module.

[0013] Optionally, the ADC driver module includes at least: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a twelfth capacitor, a thirteenth capacitor, an operational amplifier, and an ADA4945 control chip; The output terminal of the adjustable amplifier module is connected to the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to the non-inverting input terminal of the operational amplifier, the first terminal of the ninth resistor, and the first terminal of the twelfth capacitor. The second terminals of the ninth resistor and the twelfth capacitor are connected to the +FB pin of the ADA4945 control chip. The inverting input terminal of the operational amplifier is connected to the second terminal of the tenth resistor, the first terminal of the eleventh resistor, and the first terminal of the thirteenth capacitor, respectively. The first terminal of the tenth resistor is grounded. The second terminals of the eleventh resistor and the thirteenth capacitor are connected to the -FB pin of the ADA4945 control chip. The first output terminal of the operational amplifier is connected to the first terminal of the twelfth resistor. The second terminal of the twelfth resistor serves as the cathode output terminal of the ADC driver module. The second output terminal of the operational amplifier is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor serves as the anode output terminal of the ADC driver module.

[0014] This invention integrates multiple acquisition cards through a multi-channel connection board. When multiple sensor data need to be transmitted simultaneously, the acquired data is processed through the channel selection, signal amplification, filtering, and ADC conversion circuits in the acquisition cards. This improves the reliability of subsequent sensor data transmission and processing, increases the processing efficiency of multi-source data, and avoids the technical problems of existing technologies where the acquisition and processing methods for multiple parameters such as micro-strain, vibration signals, displacement, and temperature of buildings are relatively simple and difficult to expand. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the main structure of the first embodiment of the multi-channel signal acquisition device of this utility model; Figure 2 This is a schematic diagram of the signal processing flow of this utility model; Figure 3 This is a schematic diagram showing the circuit structure and connection relationship of the channel selection module of this utility model; Figure 4 This is a schematic diagram of the circuit structure and electronic component connection relationship of the signal amplification module of this utility model; Figure 5 This is a schematic diagram of the circuit structure and electronic component connection relationship of the filter module of this utility model; Figure 6 This is a schematic diagram of the circuit structure and electronic component connection relationship of the adjustable amplification module of this utility model; Figure 7 This is a schematic diagram of the circuit structure and electronic component connection relationship of the ADC driver module of this utility model.

[0016] Explanation of icon numbers:

[0017] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] In this embodiment, the multi-channel signal acquisition device includes: A multi-channel signal acquisition device includes at least: a multi-channel connection board, at least one acquisition card, a switch, and a motherboard, with the acquisition card, multi-channel connection board, switch, and motherboard connected in sequence. The connection board has at least two sets of card slots. The first set of card slots is used to connect to the acquisition card, and the second set of card slots is used to connect to the motherboard. The connection board also has at least two sets of network ports. The first set of network ports is used to connect to the switch, and the second set of network ports is used to connect the switch and the motherboard.

[0020] It should be noted that the reference Figure 1 , Figure 1 This is a schematic diagram of the main structure of the multi-channel signal acquisition device in this embodiment. The acquisition card has an FPGA processor, supports 4 channels, and can be used simultaneously for the acquisition of multi-channel external high-speed dynamic signals. After circuit conditioning, the signals are converted into AD signals and finally sent out through the network port. Depending on the design circuit, the acquisition card can be divided into various types such as strain acquisition card, IEPE acquisition card, and analog acquisition card. The appropriate acquisition card can be selected according to the actual application scenario for signal acquisition, processing and transmission. This embodiment does not impose specific limitations on this.

[0021] The connection board has multiple card slots and a corresponding number of network ports. Each card slot is electrically connected to a data acquisition card. When dealing with multi-dimensional data parameters, different data acquisition cards and network ports can be adaptively selected for data processing and data transmission, improving the efficiency of building data processing. In this embodiment, a connection board with 9 card slots and 9 network ports is used as an example. Eight card slots can insert 8 data acquisition cards for network communication. This connection board allows for arbitrary mixing and matching of data acquisition cards from the dynamic monitoring data acquisition instrument, achieving the goal of simultaneous monitoring of multiple parameters. Eight network ports are used to connect to the switch's network port, one card slot is used to insert the motherboard, and one network port is used to connect the switch and the motherboard, thereby enabling data interaction between the motherboard and the data acquisition card.

[0022] Furthermore, the acquisition card includes at least a channel selection module, a signal amplification module, a filtering module, an adjustable amplification module, an ADC driver module, and an FPGA processing module, which are connected in sequence. The channel selection module is used to switch the bridge connection mode in order to receive valid sensing signals; The signal amplification module is used to amplify the effective sensing signal; The filtering module is used to filter the amplified effective sensing signal to obtain a sensing signal in a specific frequency band. An adjustable amplification module is used to adjust the amplitude of the sensing signal to obtain the target sensing signal; The ADC driver module is used to sample the target sensing signal to obtain the target strain data; The FPGA processing module is used to drive at least one of the following modules: the channel selection module, the signal amplification module, the filtering module, and the ADC driving module.

[0023] In practical implementation, taking a strain sensor as an example, after the dynamic signal is input, channel selection and positive / negative measurements are performed first. Channel selection involves switching between bridge modes (full-bridge, half-bridge, and 1 / 4-bridge). Positive and negative measurements eliminate interference and separate the effective signal direction, distinguishing whether the strain gauge is in a tensile or compressive state. The signal is then amplified by an instrumentation amplifier circuit, a precision circuit designed specifically for high-precision differential signal amplification. It can accurately extract weak signals through differential amplification and common-mode rejection. After amplification, the signal is conditioned by a fourth-order filter circuit, which allows signals of specific frequency bands to pass through while suppressing interference signals. More precise signal separation is achieved through high-selectivity frequency response. The signal is then passed through an adjustable amplifier circuit to achieve precise adaptation and control of the high-purity signal amplitude. Finally, high-precision sampling is achieved through an ADC driver circuit.

[0024] It is understandable that the output of a strain gauge bridge is a differential voltage signal, the polarity of which directly reflects the direction of strain. For example, when the strain gauge is stretched, the resistance increases, and the bridge output generates a positive voltage (or a negative voltage according to the wiring definition); when the strain gauge is compressed, the resistance decreases, and the bridge output generates a negative voltage (or a positive voltage). By measuring the sign of this differential signal, it is possible to clearly distinguish whether the building structure is in a state of tension or compression.

[0025] Furthermore, the channel selection module includes at least two TMUX4051PWR control chips. The two TMUX4051PWR control chips are used to perform positive and negative voltage measurements to switch the bridge connection mode and determine the valid sensing signal. The bridge connection mode includes at least full-bridge input, half-bridge input and 1 / 4 bridge input. Accordingly, during full-bridge input, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_VI5 and ADC_N_IN are turned on. When the half-bridge input is active, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S3 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_REF and ADC_N_IN are turned on. When the 1 / 4 bridge input is connected, the FPGA processing module controls the S2 pin and D pin of the first TMUX4051PWR control chip to connect so that DQ_VI3 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect so that DQ_VI5 and ADC_N_IN are turned on.

[0026] refer to Figure 2 , Figure 2 This is a schematic diagram of the signal processing flow in this embodiment. Figure 3 This is a schematic diagram of the circuit structure and connection relationship of the channel selection module in this embodiment.

[0027] Specifically, since the core of this embodiment is the setting of multiple acquisition cards, each of which supports 4 channels, synchronous processing is required at the data processing level with an accuracy of microseconds or even nanoseconds. Otherwise, it will affect the phase analysis of dynamic signals such as vibration and strain. Therefore, for different usage requirements, the FPGA processing module can selectively control the pin conduction of the TMUX4051PWR control chip to improve the data synchronization rate.

[0028] Further, refer to Figure 4 , Figure 4 This is a schematic diagram of the circuit structure and electronic component connection relationship of the signal amplification module in this embodiment. The signal amplification module includes at least: INA821IDGKR control chip, DAC7311IDGKR control chip, first ADA4807 control chip, first resistor R1, second resistor R2, first capacitor C1 and second capacitor C2. The -IN pin of the INA821IDGKR control chip is connected to the D pin of the first TMUX4051PWR control chip, and the +IN pin of the INA821IDGKR control chip is connected to the D pin of the second TMUX4051PWR control chip. The DAC7311IDGKR control chip, the first ADA4807 control chip, the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2 together constitute the reference voltage output module of the signal amplification module. The reference voltage output module specifically includes: the first end of the first capacitor C1, the first end of the second capacitor C2, and the AVDD pin of the DAC7311IDGKR control chip are respectively connected to a preset power supply; the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded; the AVDD pin of the DAC7311IDGKR control chip is connected to the first end of the first resistor R1; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the -IN1 pin of the first ADA4807 control chip; the second end of the second resistor R2 is connected to the VOUT1 pin and the +IN2 pin of the first ADA4807 control chip; the VOUT pin of the DAC7311IDGKR control chip is connected to the +IN1 pin of the first ADA4807 control chip; and the VOUT2 pin of the first ADA4807 control chip outputs the reference voltage of the signal amplification module.

[0029] Further, refer to Figure 5 , Figure 5 This is a schematic diagram of the circuit structure and electronic component connection relationship of the filtering module in this embodiment. The filtering module includes at least: a second ADA4807 control chip, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. In this circuit, the first end of the third resistor R3 is connected to the output of the signal amplification module. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the first end of the third capacitor C3. The second end of the fourth resistor R4 is connected to the +IN1 pin of the second ADA4807 control chip and the second end of the fourth capacitor C4. The VOUT1 and -IN1 pins of the second ADA4807 control chip are both connected to the second end of the third capacitor C3 and the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the first end of the fifth capacitor C5. The second end of the sixth resistor R6 is connected to the +IN2 pin of the second ADA4807 control chip. The second end of the fifth capacitor C5 is connected to the VOUT2 and -IN2 pins of the second ADA4807 control chip. The VOUT2 pin of the second ADA4807 control chip serves as the output of the filtering module. The +IN2 pin of the second ADA4807 control chip is connected to the first end of the sixth capacitor C6. The second end of the sixth capacitor C6 is grounded.

[0030] Further, refer to Figure 6 , Figure 6This is a schematic diagram of the circuit structure and electronic component connection relationship of the adjustable amplification module in this embodiment. The adjustable amplification module includes at least: LTC6910 control chip, seventh resistor R7, seventh capacitor C7, eighth capacitor C8, ninth capacitor C9, tenth capacitor C10, and eleventh capacitor C11. In this configuration, the IN pin of the LTC6910 control chip is connected to the output of the filter module. The first end of the seventh resistor R7 and the first end of the seventh capacitor C7 are grounded. The second end of the seventh resistor R7 and the second end of the seventh capacitor C7 are both connected to the AGND pin of the LTC6910 control chip. The V- pin of the LTC6910 control chip is grounded through the parallel eighth capacitor C8 and the ninth capacitor C9. The V+ pin of the LTC6910 control chip is grounded through the parallel tenth capacitor C10 and the eleventh capacitor C11. The OUT pin of the LTC6910 control chip serves as the output of the adjustable amplifier module.

[0031] Further, refer to Figure 7 , Figure 7 This is a schematic diagram of the circuit structure and electronic component connection relationship of the ADC driver module in this embodiment. The ADC driver module includes at least: eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, twelfth capacitor C12, thirteenth capacitor C13, operational amplifier, and ADA4945 control chip. The output of the adjustable amplifier module is connected to the first end of the eighth resistor R8. The second end of the eighth resistor R8 is connected to the non-inverting input of the operational amplifier, the first end of the ninth resistor R9, and the first end of the twelfth capacitor C12. The second ends of the ninth resistor R9 and the twelfth capacitor C12 are connected to the +FB pin of the ADA4945 control chip. The inverting input of the operational amplifier is connected to the second end of the tenth resistor R10, the first end of the eleventh resistor R11, and the first end of the thirteenth capacitor C13, respectively. The first end of the tenth resistor R10 is grounded. The second ends of the eleventh resistor R11 and the thirteenth capacitor C13 are connected to the -FB pin of the ADA4945 control chip. The first output of the operational amplifier is connected to the first end of the twelfth resistor R12. The second end of the twelfth resistor R12 serves as the cathode output of the ADC driver module. The second output of the operational amplifier is connected to the first end of the thirteenth resistor R13. The second end of the thirteenth resistor R13 serves as the anode output of the ADC driver module.

[0032] Understandably, the FPGA, as the core controller, coordinates multiple control processes, including control channel selection and bridge switching, management gain adjustment and filter configuration, receiving ADC data and timestamping it, and uploading packaged data via the network port. In addition, the aforementioned front-end analog circuits, such as the signal amplification module, filtering module, and adjustable amplification module, improve the fidelity and integrity of the initial input effective sensing signal and enhance the acquisition effect of dynamic strain signals.

[0033] This embodiment integrates multiple acquisition cards through a multi-channel connection board. When multiple sensor data need to be transmitted simultaneously, the acquired data is processed through the channel selection, signal amplification, filtering, and ADC conversion circuits in the acquisition cards. This improves the reliability of subsequent sensor data transmission and processing, increases the processing efficiency of multi-source data, and avoids the technical problems of the existing technology, which has relatively simple acquisition and processing of vibration signals of micro-strain in buildings and is difficult to expand.

[0034] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0035] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A multi-channel signal acquisition device, characterized in that, The multi-channel signal acquisition device includes at least: a multi-channel connection board, at least one acquisition card, a switch, and a motherboard, wherein the acquisition card, the multi-channel connection board, the switch, and the motherboard are connected in sequence; The connection board has at least two sets of card slots. The first set of card slots is used to connect to the acquisition card, and the second set of card slots is used to connect to the motherboard. The connection board also has at least two sets of network ports. The first set of network ports is used to connect to the switch, and the second set of network ports is used to connect the switch and the motherboard.

2. The multi-channel signal acquisition device as described in claim 1, characterized in that, The acquisition card is used to acquire or receive valid sensing signals of at least one data dimension, and process the valid sensing signals to obtain strain data that the motherboard can process.

3. The multi-channel signal acquisition device as described in claim 1, characterized in that, The acquisition card includes at least a channel selection module, a signal amplification module, a filtering module, an adjustable amplification module, an ADC driver module, and an FPGA processing module. The channel selection module, the signal amplification module, the filtering module, and the ADC driver module are all connected to the FPGA processing module. The channel selection module is used to switch the bridge connection mode in order to receive valid sensing signals; The signal amplification module is used to amplify the effective sensing signal; The filtering module is used to filter the amplified effective sensing signal to obtain a sensing signal in a specific frequency band. The adjustable amplification module is used to adjust the signal amplitude of the sensing signal to obtain the target sensing signal; The ADC driving module is used to sample the target sensing signal to obtain target strain data; The FPGA processing module is used to drive at least one of the following modules: the channel selection module, the signal amplification module, the filtering module, and the ADC driving module.

4. The multi-channel signal acquisition device as described in claim 3, characterized in that, The channel selection module includes at least two TMUX4051PWR control chips. The two TMUX4051PWR control chips are used to perform positive and negative voltage measurements to switch the bridge connection mode and determine the valid sensing signal. The bridge connection mode includes at least full-bridge input, half-bridge input and 1 / 4 bridge input. Accordingly, during full-bridge input, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_VI5 and ADC_N_IN are turned on. When the half-bridge input is active, the FPGA processing module controls the S1 pin and D pin of the first TMUX4051PWR control chip to connect, so that DQ_VI2 and ADC_P_IN are turned on, and controls the S3 pin and D pin of the second TMUX4051PWR control chip to connect, so that DQ_REF and ADC_N_IN are turned on. When the 1 / 4 bridge input is connected, the FPGA processing module controls the S2 pin and D pin of the first TMUX4051PWR control chip to connect so that DQ_VI3 and ADC_P_IN are turned on, and controls the S2 pin and D pin of the second TMUX4051PWR control chip to connect so that DQ_VI5 and ADC_N_IN are turned on.

5. The multi-channel signal acquisition device as described in claim 3, characterized in that, The signal amplification module includes at least: an INA821IDGKR control chip, a DAC7311IDGKR control chip, a first ADA4807 control chip, a first resistor, a second resistor, a first capacitor, and a second capacitor; The -IN pin of the INA821IDGKR control chip is connected to the D pin of the first TMUX4051PWR control chip, and the +IN pin of the INA821IDGKR control chip is connected to the D pin of the second TMUX4051PWR control chip. The DAC7311IDGKR control chip, the first ADA4807 control chip, the first resistor, the second resistor, the first capacitor, and the second capacitor together constitute the reference voltage output module of the signal amplification module. The reference voltage output module specifically includes: the first end of the first capacitor, the first end of the second capacitor, and the AVDD pin of the DAC7311IDGKR control chip are respectively connected to a preset power supply; the second ends of the first capacitor and the second end of the second capacitor are grounded; the AVDD pin of the DAC7311IDGKR control chip is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor and the -IN1 pin of the first ADA4807 control chip; the second end of the second resistor is connected to the VOUT1 pin and the +IN2 pin of the first ADA4807 control chip; the VOUT pin of the DAC7311IDGKR control chip is connected to the +IN1 pin of the first ADA4807 control chip; and the VOUT2 pin of the first ADA4807 control chip outputs the reference voltage of the signal amplification module.

6. The multi-channel signal acquisition device as described in claim 3, characterized in that, The filtering module includes at least: a second ADA4807 control chip, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; In this configuration, the first end of the third resistor is connected to the output of the signal amplification module; the second end of the third resistor is connected to the first end of the fourth resistor and the first end of the third capacitor; the second end of the fourth resistor is connected to the +IN1 pin of the second ADA4807 control chip and the second end of the fourth capacitor; the VOUT1 and -IN1 pins of the second ADA4807 control chip are both connected to the second end of the third capacitor and the first end of the fifth resistor; the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the fifth capacitor; the second end of the sixth resistor is connected to the +IN2 pin of the second ADA4807 control chip; the second end of the fifth capacitor is connected to the VOUT2 and -IN2 pins of the second ADA4807 control chip; the VOUT2 pin of the second ADA4807 control chip serves as the output of the filtering module; the +IN2 pin of the second ADA4807 control chip is connected to the first end of the sixth capacitor; and the second end of the sixth capacitor is grounded.

7. The multi-channel signal acquisition device as described in claim 3, characterized in that, The adjustable amplification module includes at least: an LTC6910 control chip, a seventh resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an eleventh capacitor; The IN pin of the LTC6910 control chip is connected to the output of the filter module. The first end of the seventh resistor and the first end of the seventh capacitor are grounded. The second end of the seventh resistor and the second end of the seventh capacitor are both connected to the AGND pin of the LTC6910 control chip. The V- pin of the LTC6910 control chip is grounded through the eighth and ninth capacitors connected in parallel. The V+ pin of the LTC6910 control chip is grounded through the tenth and eleventh capacitors connected in parallel. The OUT pin of the LTC6910 control chip serves as the output of the adjustable amplifier module.

8. The multi-channel signal acquisition device as described in claim 3, characterized in that, The ADC driver module includes at least: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a twelfth capacitor, a thirteenth capacitor, an operational amplifier, and an ADA4945 control chip; The output terminal of the adjustable amplifier module is connected to the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to the non-inverting input terminal of the operational amplifier, the first terminal of the ninth resistor, and the first terminal of the twelfth capacitor. The second terminals of the ninth resistor and the twelfth capacitor are connected to the +FB pin of the ADA4945 control chip. The inverting input terminal of the operational amplifier is connected to the second terminal of the tenth resistor, the first terminal of the eleventh resistor, and the first terminal of the thirteenth capacitor, respectively. The first terminal of the tenth resistor is grounded. The second terminals of the eleventh resistor and the thirteenth capacitor are connected to the -FB pin of the ADA4945 control chip. The first output terminal of the operational amplifier is connected to the first terminal of the twelfth resistor. The second terminal of the twelfth resistor serves as the cathode output terminal of the ADC driver module. The second output terminal of the operational amplifier is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor serves as the anode output terminal of the ADC driver module.

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