Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, and relates to the technical field of display, the array substrate comprises a substrate, a first metal layer, a first bottom metal layer and a second metal layer, the first metal layer is arranged on the substrate, the first bottom metal layer is arranged on the side of the first metal layer away from the substrate, the second metal layer is arranged on the side of the first bottom metal layer away from the substrate, the second metal layer is made of copper material, wherein the length of the orthographic projection of the first bottom metal layer on the substrate is greater than the length of the orthographic projection of the second metal layer on the substrate, and the risk of metal explosion is reduced through the above design.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the rapid development of technology, liquid crystal displays (LCDs) have emerged as a leader in the flat panel display field. Everyday devices such as mobile phones, computers, televisions, and watches widely utilize thin-film transistor (TFT) LCDs. TFT LCDs are widely used in various industries due to their advantages such as low radiation, low power consumption, low space occupation, and lightweight and aesthetically pleasing design.

[0003] For TFT array substrates, the first and second metal layers in the thin-film transistors are made of copper, which has low impedance and reduces the delay of resistance and capacitance, thereby improving the pixel charging rate and optimizing the display panel quality.

[0004] The crossover section formed by the cross arrangement of the first copper layer and the second metal layer is usually formed by stacking the bottom metal layer and the first copper layer to form an undercut structure. The phosphorus-doped silicon nitride (P-SiNx) at the undercut is thinner due to the influence of topography and interface, which can easily cause a semi-circular missing part of the first copper layer with the sharp corner apex as the center. At the same time, Cu ions will be deposited in the second copper layer. The gaps at the missing abnormal points are prone to charge accumulation and diffusion under the action of electric field. In severe cases, the insulation layer of the crossover section is prone to breakdown, causing metal damage between the first copper layer and the second metal layer below, resulting in a short circuit between the second metal layer and the first metal layer.

[0005] Therefore, the above problems urgently need to be solved. Utility Model Content

[0006] The purpose of this application is to provide an array substrate and display panel that reduce the risk of metal blast injuries.

[0007] This application discloses an array substrate, comprising: a substrate, a first metal layer, a first bottom metal layer, and a second metal layer. The first metal layer is disposed on the substrate, and the first bottom metal layer is disposed on the side of the first metal layer away from the substrate. The second metal layer is disposed on the side of the first bottom metal layer away from the substrate, wherein the length of the orthographic projection of the first bottom metal layer on the substrate is greater than the length of the orthographic projection of the second metal layer on the substrate.

[0008] Optionally, the first bottom metal layer is made of molybdenum-titanium alloy or molybdenum-titanium-nickel alloy.

[0009] Optionally, the two ends of the first bottom metal layer protrude from the second metal layer to form a first bottom metal portion and a second bottom metal portion, and the lengths of the first bottom metal portion and the second bottom metal portion are both 180nm-200nm.

[0010] Optionally, the array substrate further includes a spacer layer and a first insulating layer, wherein the first insulating layer is disposed between the first metal layer and the first bottom metal layer, and the spacer layer is disposed between the first insulating layer and the first bottom metal layer.

[0011] Optionally, the array substrate further includes a second insulating layer, which is disposed on the side of the second metal layer away from the substrate, and the thickness of the second insulating layer is [missing information].

[0012] Optionally, the array substrate further includes a third insulating layer and a transparent electrode layer. The third insulating layer is disposed above the second insulating layer, and a transfer hole is provided on the third insulating layer. The transfer hole penetrates the third insulating layer and a portion of the first insulating layer and a portion of the second insulating layer in a direction perpendicular to the substrate. The transparent electrode layer is disposed on the third insulating layer and covers the transfer hole. The thickness of the transparent electrode layer is [missing information].

[0013] Optionally, the array substrate further includes an isolation pillar disposed on the side of the transparent electrode layer away from the third insulating layer, and the isolation pillar covers the transfer hole.

[0014] Optionally, the transfer hole includes a plurality of sub-transfer holes, which are arranged in an array; wherein the isolation column covers the plurality of sub-transfer holes.

[0015] This application also discloses a display panel, including a color filter substrate and an array substrate as described above, wherein the color filter substrate and the array substrate are disposed opposite to each other.

[0016] Optionally, the display panel further includes a frame adhesive, the display panel is divided into a display area and a non-display area, the frame adhesive is disposed between the color filter substrate and the array substrate and is located in the non-display area, and the frame adhesive surrounds the display area; wherein, the width of the frame adhesive is 1000μm→1300μm.

[0017] Compared to existing technologies where the cross-line portion formed by the first copper layer and the second metal layer in thin-film transistors is typically constructed using a molybdenum layer and the first copper layer stacked together to form an undercut structure, which easily results in a semi-circular missing corner of the first copper layer at the cross-line portion, causing Cu ions to penetrate the insulating layer and cause metal damage, the array substrate of this application includes a substrate, a first metal layer, a first bottom metal layer, and a second metal layer. The first metal layer is disposed on the substrate, and the first bottom metal layer is disposed on the side of the first metal layer away from the substrate. The second metal layer is disposed on the side of the first bottom metal layer away from the substrate and is made of copper. The length of the orthographic projection of the first bottom metal layer on the substrate is greater than the length of the orthographic projection of the second metal layer on the substrate. This extends the diffusion path of Cu ions by the first bottom metal layer, effectively blocking Cu ions and making it less likely for Cu ions to cross the first bottom metal layer and contact the first metal layer below, thereby reducing the risk of metal damage. Attached Figure Description

[0018] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0019] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0020] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along section line A-A';

[0021] Figure 3 This is a schematic cross-sectional view of the array substrate cross-line portion provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the cross-sectional structure of the array substrate cross-line portion along the extension direction of the second metal layer provided in the embodiment of this application;

[0023] Figure 5 This is a top view of the cross-line portion of the array substrate provided in an embodiment of this application;

[0024] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure along section line B-B'.

[0025] Among them, 10 is a display panel; 11 is a display area; 12 is a non-display area; 100 is an array substrate; 110 is a substrate; 120 is a first bottom metal layer; 121 is a first bottom metal portion; 122 is a second bottom metal portion; 123 is a third bottom metal portion; 130 is a second metal layer; 140 is a first insulating layer; 150 is a first metal layer; 160 is a spacer layer; 170 is a second insulating layer; 180 is a third insulating layer; 190 is a transparent electrode layer; 200 is a transfer hole; 210 is a sub-transfer hole; 220 is a spacer post; 230 is a frame adhesive; and 200 is a color filter substrate. Detailed Implementation

[0026] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0027] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Furthermore, terms indicating orientation or positional relationships such as "upper," "lower," "left," "right," "second direction," and "first direction" are described based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0028] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0029] Example:

[0030] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along section line A-A'. Figure 3 This is a schematic cross-sectional view of the array substrate's cross-line portion provided in an embodiment of this application, combined with... Figures 1-3This application discloses a display panel 10, including a color filter substrate 200 and an array substrate 100. The color filter substrate 200 is disposed opposite to the array substrate 100. The array substrate 100 includes a substrate 110, a first metal layer 150, a first bottom metal layer 120, and a second metal layer 130. The first metal layer 150 is disposed on the substrate 110. The first bottom metal layer 120 is disposed on the side of the first metal layer 150 away from the substrate 110. The second metal layer 130 is disposed on the side of the first bottom metal layer 120 away from the substrate 110. The length of the orthographic projection of the first bottom metal layer 120 on the substrate 110 is greater than the length of the orthographic projection of the second metal layer 130 on the substrate 110.

[0031] Compared to existing technologies where the crossover portion formed by the first copper layer and the second metal layer 130 in thin-film transistors is typically constructed using a stacked bottom metal layer and a first copper layer to form an undercut structure, which easily results in a semi-circular missing corner of the first copper layer at the crossover portion, centered on the sharp point, leading to Cu ions breaking through the insulating layer and causing metal damage, the array substrate 100 of this application includes a substrate 110, a first metal layer 150, a first bottom metal layer 120, and a second metal layer 130. The first metal layer 150 is disposed on the substrate 110, and the first bottom metal layer 130... The first metal layer 150 is disposed on the side away from the substrate 110; the second metal layer 130 is disposed on the side away from the substrate 110 of the first bottom metal layer 120. The length of the orthogonal projection of the first bottom metal layer 120 on the substrate 110 is greater than the length of the orthogonal projection of the second metal layer 130 on the substrate 110. In this way, the diffusion path of Cu ions is extended by the first bottom metal layer 120, forming an effective barrier to Cu ions, making it difficult for Cu ions to cross the first bottom metal layer 120 and come into contact with the first metal layer 150 below, thereby reducing the risk of metal blasting.

[0032] The first bottom metal layer 120 can be used to enhance the adhesion between the upper and lower film layers. For example... Figure 3As shown, the first bottom metal layer 120 is formed by a first bottom metal portion 121, a second bottom metal portion 122, and a third bottom metal portion 123. The first bottom metal portion 121 and the second bottom metal portion 122 are respectively connected to the two ends of the third bottom metal portion 123. The length of the third bottom metal portion 123 is the same as the length of the second metal layer 130, that is, both the first bottom metal portion 121 and the second bottom metal portion 122 protrude from the second metal layer 130. The lengths of the first bottom metal portion 121 and the second bottom metal portion 122 are both 180nm-200nm. In this way, the first barrier portion and the second bottom metal portion 122 have sufficient length to extend the diffusion path of Cu ions in the second metal layer 130, further reducing the risk of blasting.

[0033] The second metal layer 130 is the source / drain metal layer. In addition, the elongated first bottom metal portion 121 and second bottom metal portion 122 can reduce the electric field strength at the sharp corners of the source / drain. Through experiments, the inventors found that the electric field strength at the sharp corners can be reduced by about 96% using the above structure, which can prevent Cu diffusion.

[0034] The first bottom metal layer 120 is made of molybdenum-titanium alloy or molybdenum-titanium-nickel alloy. Compared with a simple molybdenum material, the etching rate of the first bottom metal layer 120 is slower. In conjunction with the first bottom metal part 121 and the second bottom metal part 122 with extended ends, the risk of metal blasting is further avoided.

[0035] Figure 4 This is a schematic cross-sectional view of the array substrate's cross-line portion along the extension direction of the second metal layer 130, as provided in the embodiments of this application. Figure 4As shown, the array substrate 100 further includes a spacer layer 160 and a first insulating layer 140. The first insulating layer 140 is disposed between the first metal layer 150 and the first bottom metal layer 120, and the spacer layer 160 is disposed between the first insulating layer 140 and the first bottom metal layer 120. In this context, the first metal layer 150 is the gate metal layer. In the GDL gate drive circuit region, due to the presence of the second metal layer 130 and the second insulating layer 170, the slope of the second metal layer 130 climbing across the line is relatively large. At this time, the height difference between the second metal layer 130 and the first metal layer 150 is relatively large. When the first insulating layer 140 is too thin, the insulation performance deteriorates. If the Cu ions of the second metal layer 130 cross the first bottom metal layer 120, under continuous high voltage, the Cu ions of the second metal layer 130 are also prone to break down the first insulating layer 140 and come into contact with the first metal layer 150, causing metal damage. Thus, by placing a spacer layer 160AS under the second metal layer 130, the distance between the second metal layer 130 and the first metal layer 150 is further increased, and the breakdown resistance is enhanced.

[0036] The array substrate 100 also includes a second insulating layer 170, which is disposed on the side of the second metal layer 130 away from the substrate 110. Although the design with a spacer layer 160AS below the second metal layer 130 results in better yield and reliability, functional abnormalities due to diffusion of the second metal layer 130 still exist. Because Cu and Mo (molybdenum) have different work functions, a slight potential difference exists between Cu and Mo in alkaline stripping solutions or copper acid. A galvanic cell chemical reaction occurs at their interface, causing Mo to lose electrons and corrode. Therefore, both the stripping solution and copper acid contain copper-molybdenum corrosion inhibitors to reduce the potential difference between Cu and Mo. If the corrosion inhibitor content is too high, Cu corrosion will occur, and voids will be created at the sharp corners of the second metal layer 130. If the second insulating layer 170 is too thin, its barrier effect on Cu ion diffusion is weak, and Cu ions will break through the second insulating layer 170, posing a risk of metal explosion between it and the adjacent second metal layer 130. Therefore, the thickness of the second insulating layer 170 can be set to... In this way, the diffused Cu ions can be blocked inside by the thickened second insulating layer 170, preventing them from completely diffusing to the outside, thus avoiding damage between the diffused Cu ions and the signals in the same layer.

[0037] Figure 5 This is a top view of the cross-line portion of the array substrate provided in an embodiment of this application. Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure along section line B-B', combined with... Figures 5-6The array substrate 100 further includes a third insulating layer 180 and a transparent electrode layer 190. The third insulating layer 180 is disposed above the second insulating layer 170. A transfer hole 200 is provided on the third insulating layer 180, and the transfer hole 200 penetrates the third insulating layer 180 and a portion of the first insulating layer 140 and a portion of the second insulating layer 170 in a direction perpendicular to the substrate 110. The transparent electrode layer 190 is disposed on the third insulating layer 180 and covers the transfer hole 200. At the location corresponding to the first metal layer 150, the transfer hole 200 needs to be formed by penetrating the first insulating layer 140, the second insulating layer 170, and the third insulating layer 180 in a direction perpendicular to the substrate 110. At the location corresponding to the second metal layer 130, the transfer hole 200 only needs to be formed by penetrating the second insulating layer 170 and the third insulating layer 180 in a direction perpendicular to the substrate 110. Thus, the second metal layer 130 and the first metal layer 150 are connected by a transparent electrode, wherein the thickness of the transparent electrode layer 190 is...

[0038] Because moisture penetrates the transparent electrode layer 190 in the GDL region and enters the interface between the transparent electrode layer 190 and the underlying Mo metal, electrochemical corrosion occurs between the two conductive materials with different potential differences in the aqueous environment, leading to the deterioration of the interface between the transparent electrode layer 190 and Mo. During the energization process, Joule heating causes thermal motion of In in the transparent electrode layer 190, resulting in In aggregation and recrystallization, thus increasing the In content on the film surface. Simultaneously, moisture intrudes into the transparent electrode layer 190, causing an increase in O content. Furthermore, the interface deterioration caused by electrochemical corrosion increases the contact resistance, and the increased Joule heating causes the vias to burn out. This application addresses this issue by designing an increased thickness of the transparent electrode layer 190, which on the one hand prevents moisture intrusion, and on the other hand reduces the probability of electrochemical corrosion, thereby reducing resistance and improving pressure resistance.

[0039] Alternatively, an isolation post 220 can be provided on the transfer hole 200. The isolation post 220 is located on the side of the transparent electrode layer 190 away from the third insulating layer 180, and the isolation post 220 covers the transfer hole 200. That is, the isolation post 220 is made on the array substrate 100 side. In this way, on the one hand, the isolation post 220 can be made relatively shorter than the isolation post 220 on the color filter substrate 200 side. At this time, the amount of material used for the isolation post 220 is relatively small, and the loading within the array substrate 100 is also smaller, resulting in a higher charging rate. On the other hand, the isolation post 220 can be used as an insulating material to protect the transfer hole 200.

[0040] Furthermore, the transfer via 200 includes a plurality of sub-transfer vias 210, which are arranged in an array, and can be configured as three rows, six rows, or even more, to reduce the current density of the transfer vias 200 and the transparent electrode layer 190. The isolation pillar 220 covers the plurality of sub-transfer vias 210, and the area of ​​the orthographic projection of the isolation pillar 220 onto the substrate 110 is larger than the area of ​​the orthographic projection of the transparent electrode onto the substrate 110, further protecting the plurality of sub-transfer vias 210.

[0041] The display panel 10 also includes a frame adhesive 230. The display panel 10 is divided into a display area 11 and a non-display area 12. The frame adhesive 230 is disposed between the color filter substrate 200 and the array substrate 100, and is located in the non-display area 12. The frame adhesive 230 surrounds the display area 11 and serves as a sealing material around the display panel 10. The width of the frame adhesive 230 is 1000μm to 1300μm. By widening the width of the frame adhesive 230, its ability to block moisture is enhanced, thereby preventing moisture from invading the interior of the array substrate 100 and causing abnormal corrosion of the metal traces or transfer holes 200, thus ensuring the quality of the array substrate 100.

[0042] It should be noted that the utility model concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0043] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate, comprising: Substrate; A first metal layer is disposed on the substrate; A first bottom metal layer is disposed on the side of the first metal layer away from the substrate; The second metal layer is disposed on the side of the first bottom metal layer away from the substrate, characterized in that, The length of the orthographic projection of the first bottom metal layer on the substrate is greater than the length of the orthographic projection of the second metal layer on the substrate.

2. The array substrate as described in claim 1, characterized in that, The first bottom metal layer is made of molybdenum-titanium alloy or molybdenum-titanium-nickel alloy.

3. The array substrate as described in claim 2, characterized in that, The two ends of the first bottom metal layer protrude from the second metal layer to form a first bottom metal part and a second bottom metal part, and the lengths of the first bottom metal part and the second bottom metal part are both 180nm-200nm.

4. The array substrate as described in claim 3, characterized in that, The array substrate further includes a spacer layer and a first insulating layer, wherein the first insulating layer is disposed between the first metal layer and the first bottom metal layer, and the spacer layer is disposed between the first insulating layer and the first bottom metal layer.

5. The array substrate as described in claim 4, characterized in that, The array substrate further includes a second insulating layer, which is disposed on the side of the second metal layer away from the substrate, and the thickness of the second insulating layer is [missing information].

6. The array substrate as described in claim 5, characterized in that, The array substrate further includes a third insulating layer and a transparent electrode layer. The third insulating layer is disposed above the second insulating layer. A transfer hole is provided on the third insulating layer, and the transfer hole penetrates the third insulating layer and part of the first insulating layer and part of the second insulating layer in a direction perpendicular to the substrate. The transparent electrode layer is disposed on the third insulating layer and covers the transfer hole. Wherein, the thickness of the transparent electrode layer is 7. The array substrate as described in claim 6, characterized in that, The array substrate further includes isolation pillars disposed on the side of the transparent electrode layer away from the third insulating layer, and the isolation pillars cover the transfer hole.

8. The array substrate as claimed in claim 7, characterized in that, The transfer hole includes a plurality of sub-transfer holes, and the plurality of sub-transfer holes are arranged in an array; The isolation column covers multiple sub-layer holes.

9. A display panel, characterized in that, It includes a color filter substrate and an array substrate as described in any one of claims 1-8, wherein the color filter substrate and the array substrate are disposed opposite to each other.

10. The display panel as claimed in claim 9, characterized in that, The display panel further includes a frame adhesive, the display panel is divided into a display area and a non-display area, the frame adhesive is disposed between the color filter substrate and the array substrate, and is located in the non-display area, the frame adhesive is disposed around the display area; The width of the frame adhesive is 1000μm→1300μm.

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