Flash memory chip testing system

Abstract

The utility model discloses a flash memory chip test system, include: main control module, and main control module communication connection has host computer, signal processing module, signal processing module communication connection is in main control module, and signal processing module is provided with at least one test unit, and at least one test unit includes one ONFI interface and at least one SPI interface, and ONFI interface is connected with ONFI test seat, and at least one SPI interface is connected with SPI test seat, power module, and power module is connected with main control module and signal processing module. Through the test unit integration of signal processing module has ONFI interface and SPI interface, ONFI interface connects ONFI test seat, SPI interface connects SPI test seat, and different types of flash memory chips are placed in the corresponding test seat during testing, can test the flash memory chip of ONFI protocol and SPI protocol, improves the versatility and test ability of system, provides the test tool for more types of flash memory chips.

Description

Technical Field

[0001] This utility model relates to the field of flash memory chip technology, and in particular to a flash memory chip testing system. Background Technology

[0002] SLC NAND Flash is widely used in embedded memory and industrial control equipment due to its high reliability, low power consumption, and fast read / write performance. SHMOO testing, as a key performance evaluation method, tests the chip's functionality under different voltage, frequency, and timing conditions, generating SHMOO plots to visually demonstrate the chip's performance limits and reliability.

[0003] However, existing shmoo testing equipment has a single testing interface, supporting only ONFI or SPI interfaces, and cannot be compatible with both interfaces simultaneously, which limits the shmoo testing equipment's ability to test different NAND Flash types. Utility Model Content

[0004] The main purpose of this invention is to propose a flash memory chip testing system, which aims to solve the technical problem of the single interface of existing Shmoo testing equipment.

[0005] To achieve the above objectives, this utility model proposes a flash memory chip testing system, comprising:

[0006] The main control module is communicatively connected to a host computer and is used to control the operation of the flash memory chip testing system.

[0007] The signal processing module is communicatively connected to the main control module. The signal processing module is provided with at least one test unit. The at least one test unit includes an ONFI interface and at least one SPI interface. The ONFI interface is connected to an ONFI test socket, and the at least one SPI interface is connected to an SPI test socket.

[0008] A power supply module is connected to the main control module and the signal processing module, and is used to supply power to the main control module and the signal processing module.

[0009] In some embodiments, at least one of the test units includes two SPI interfaces, both of which are connected to the SPI test socket.

[0010] In some embodiments, the test unit is provided in four groups.

[0011] In some embodiments, the power module includes power chips in the same number as the ONFI test socket and the SPI test socket, and the power chips are respectively connected to the ONFI test socket and the SPI test socket.

[0012] In some embodiments, the power module further includes a microcontroller unit that is communicatively connected to the main control module, and any one of the power chips is electrically connected to the microcontroller unit. The microcontroller unit is used to drive the power chip to work under the control of the main control module.

[0013] In some embodiments, the power module further includes DAC units in the same number as the power chips, the DAC units being electrically connected to the microcontroller unit to perform digital-to-analog conversion on the output signal of the microcontroller unit.

[0014] In some embodiments, the flash memory chip testing system further includes a voltage regulation module, which includes multiple voltage acquisition chips. The multiple voltage acquisition chips are respectively disposed between the ONFI test socket and the power supply chip, and between the SPI test socket and the power supply chip. The voltage acquisition chips are used to acquire the voltage of the ONFI test socket and the SPI test socket.

[0015] In some embodiments, the flash memory chip testing system further includes an Ethernet module, the signal processing module is provided with a network interface, and the Ethernet module is communicatively connected to the host computer and the network interface to upload the test data of the signal processing module to the host computer.

[0016] In some embodiments, a storage medium is further included, which is connected to the main control module and is used to store test data.

[0017] In some embodiments, the signal processing module includes an FPGA logic unit, and the ONFI interface and the SPI interface are integrated on the FPGA logic unit.

[0018] The main control module of this utility model communicates with the host computer and can control the entire test process to achieve unified management. By integrating ONFI and SPI interfaces into the test unit of the signal processing module, the ONFI interface connects to the ONFI test socket and the SPI interface connects to the SPI test socket. During testing, different types of flash memory chips are placed in the corresponding test sockets, which can test flash memory chips with ONFI and SPI protocols, improve the system's versatility and testing capabilities, and provide testing tools for more types of flash memory chips. Attached Figure Description

[0019] Figure 1 This is a partial structural schematic diagram of an embodiment of the flash memory chip testing system of this utility model.

[0020] Explanation of icon numbers:

[0021] 100 Main control module 200 host computer 300 Signal processing module 310 ONFI test socket 320 SPI test socket 700 storage media 410 power chip 420 microcontroller 500 Voltage acquisition chip 600 Ethernet module Detailed Implementation

[0022] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0023] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0024] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0025] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0026] Please refer to Figure 1 This utility model provides a flash memory chip testing system, comprising:

[0027] The main control module 100 is connected to the host computer 200 for controlling the operation of the flash memory chip testing system.

[0028] The signal processing module 300 is communicatively connected to the main control module 100. The signal processing module 300 is provided with at least one test unit, which includes an ONFI interface and at least one SPI interface. The ONFI interface is connected to an ONFI test socket 310, and the at least one SPI interface is connected to an SPI test socket 320.

[0029] The power supply module is connected to the main control module 100 and the signal processing module 300, and is used to supply power to the main control module 100 and the signal processing module 300.

[0030] The flash memory chip testing system provided in this embodiment is mainly used for SHMO testing of flash memory chips. The main function of the main control module 100 is to communicate with the host computer 200, and is responsible for parsing SHMO test instructions and coordinating the overall SHMO test process. The main control module 100 can be an STM32 microcontroller or a PLC, etc. For example, the main control module 100 can use an STM32F4 series microcontroller. Of course, the above is only an example, and the specific model can be determined according to actual needs; this utility model does not impose any limitations.

[0031] In this embodiment, the main control module 100 can establish a communication connection with the host computer 200 via USB or Ethernet. For example, the main control module 100 establishes a communication connection with the host computer 200 via USB. On the one hand, USB is one of the most common interface standards in current electronic devices, and the host computer 200 is generally equipped with a USB interface, eliminating the need for additional dedicated communication hardware and lowering the connection threshold between the system and the host computer 200. On the other hand, whether it is an industrial-grade test computer or ordinary office equipment, it can be quickly connected to the test system via USB, improving the system's versatility and ease of use.

[0032] This invention's signal processing module 300 integrates a hybrid interface, including at least one set of test units. These test units, equipped with both ONFI and SPI interfaces, are compatible with both ONFI and SPI-protocol NAND Flash. The ONFI interface is connected to an ONFI test socket 310, and the SPI interface is connected to an SPI test socket 320. Through the ONFI test socket 310, this invention can test mainstream MLC / TLC NAND and enterprise-level SSD controllers, while through the SPI test socket 320, it can simultaneously test SLC NAND Flash and embedded NOR Flash, improving the system's versatility and testing capabilities. Furthermore, the system can test different types of flash memory chips without requiring additional interface types, reducing hardware costs and facilitating low-cost, wide-ranging applications.

[0033] The number of test units can be 1, 2, 3, or 4. For example, to simultaneously test more flash memory chips and improve testing efficiency, four groups of test units can be set up. Of course, the above is just an example, and the specific number can be determined according to actual needs. This utility model does not impose any limitations on this.

[0034] The main control module 100 of this invention communicates with the host computer 200, enabling control of the entire testing process and unified management. By integrating ONFI and SPI interfaces into the testing unit of the signal processing module 300, with the ONFI interface connected to the ONFI test socket 310 and the SPI interface connected to the SPI test socket 320, different types of flash memory chips can be placed in their corresponding test sockets during testing. This allows for testing of flash memory chips using both ONFI and SPI protocols, improving the system's versatility and testing capabilities, and providing testing tools for more types of flash memory chips. Furthermore, the integrated design of different interface types eliminates the need for additional equipment, enabling testing of different types of flash memory chips on a single system, reducing hardware costs and facilitating low-cost, wide-ranging applications.

[0035] In some embodiments, at least one test unit includes two SPI interfaces, both of which are connected to an SPI test socket 320, enabling simultaneous testing of two SPI protocol flash memory chips, thereby further improving the system's testing efficiency.

[0036] In this embodiment, four test units are provided. This can be understood as the present invention having four ONFI interfaces and eight SPI interfaces. Please refer to the relevant documentation for details. Figure 1 The ONFI test socket 310 is configured with 4 sockets, and the SPI test socket 320 is configured with 8 sockets, enabling parallel testing of 4 ONFI protocol flash memory chips or 8 SPI protocol flash memory chips.

[0037] This invention, by setting up four test units, enables batch testing of multiple flash memory chips and is compatible with different types of chips, improving synchronous testing capabilities and efficiency while reducing time costs. Furthermore, each test unit can have fixed voltage, frequency, timing, etc., to achieve multi-parameter cross-testing, expanding the system's SHMO testing dimensions.

[0038] This invention also features automatic interface type testing and driver switching capabilities. It automatically identifies the ONFI and SPI interfaces by detecting the pin level characteristics of the ONFI test socket 310 and SPI test socket 320. For example, when a K9F1G08U0E SLC NAND Flash (ONFI interface, 1Gb capacity) is inserted into the ONFI test socket 310, the CLE / ALE level of the ONFI test socket 310 changes, and the main control module 100 controls the signal processing module 300 to load the ONFI driver firmware for testing. Similarly, when testing SPI protocol type flash memory, identification is performed by detecting the MISO / MOSI signals of the SPI test socket 320.

[0039] Please refer to Figure 1The flash memory chip testing system provided in this embodiment also includes a storage medium 700, which is connected to the main control module 100 and is used to store test data. The storage medium 700 can be a QSPINOR Flash, and the stored data can be test data and bitstream files that drive different types of interfaces. After detecting the signal of the test socket to determine the interface type, the main control module 100 loads the corresponding bitstream file from the storage medium 700 to the signal processing module 300. The flash memory chip testing system automatically switches drivers, supporting parallel testing of 8-channel SPI NAND Flash or 4-channel ONFI NAND Flash, thus improving testing efficiency.

[0040] Please continue to refer to this. Figure 1 The power module includes power chips 410 in the same number as the ONFI test socket 310 and the SPI test socket 320, and the power chips 410 are connected to the ONFI test socket 310 and the SPI test socket 320 respectively.

[0041] The power chip 410 can be of type TITPS7A4700, which can output voltages from 1.5V to 3.6V. It also integrates overvoltage / overcurrent protection, automatically cutting off power if the voltage exceeds 3.5V or the current exceeds 500mA, to prevent system burnout or even explosion hazards, thereby improving system stability, safety and lifespan.

[0042] This invention features a separate power supply chip 410 for different interfaces, enabling independent power supply control for different types of flash memory chips under test. This precisely matches the power supply requirements of different types of flash memory chips, avoiding test errors or chip damage caused by power supply incompatibility. Furthermore, the core of SHMO testing is verifying the performance of flash memory chips under different voltage, frequency, and timing conditions. The independent power supply chip 410 can independently output voltage, applying different voltage stresses to the ONFI and SPI interface chips respectively. This allows for the simultaneous acquisition of voltage boundary data for different types of flash memory chips within the same test system, improving test efficiency. Finally, the independent power supply chip 410 isolates the power supply circuits of the two types of interface flash memory chips, reducing cross-interference and ensuring the accuracy of voltage and current measurements. This provides a reliable power supply foundation for the accurate generation of SHMO diagrams, improving test precision.

[0043] Please refer to Figure 1 The power module also includes a microcontroller unit 420 that is communicatively connected to the main control module 100. Any power chip 410 is electrically connected to the microcontroller unit 420, which is used to drive the power chip 410 to work under the control of the main control module 100.

[0044] The microcontroller unit 420, as the control core of the power module, undertakes the driving and management functions of the power chips 410 and communicates with the main control module 100 via a serial port. The microcontroller unit 420 manages 12 power chips 410 by running a 12-channel PID algorithm. The microcontroller unit 420 can be an NXP i.MX RT1170, which adopts a heterogeneous dual-core architecture with an Arm Cortex-M7 core clock speed of up to 1GHz, possessing powerful computing capabilities to handle complex tasks; it integrates rich communication interfaces to meet the communication needs between different devices. Of course, the above is only an example, and specific implementations can be determined according to actual needs; this utility model does not impose any limitations.

[0045] This invention utilizes a microcontroller unit 420 to monitor the output status of each power chip 410 in real time and respond quickly to abnormalities, such as cutting off the output of the corresponding power chip 410 to prevent damage to the chip under test. The microcontroller unit 420 can also record the operating parameters of each power chip 410, such as voltage output curves and current fluctuation data, and upload this data to the host computer 200 via communication with the main control module 100, providing power-level data support for SHMO test plotting. Furthermore, in SHMO testing, continuous scanning of parameters such as voltage and frequency is required. The microcontroller unit 420 can drive the power chips 410 to achieve smooth parameter switching according to instructions from the main control module 100, meeting the requirements of high-precision scanning tests. Finally, the microcontroller unit 420 can preset differentiated control logic for power chips 410 with different interfaces to ensure accurate matching of power supply parameters and interface types.

[0046] In some embodiments, the power module further includes DAC units in the same number as the power chip 410. The DAC units are electrically connected to the microcontroller unit 420 to perform digital-to-analog conversion on the output signal of the microcontroller unit 420.

[0047] The DAC unit can be a TIDAC8568. The microcontroller unit 420 drives a single power supply chip 410 by driving the independent DAC unit, isolating the control paths of each channel and ensuring that the power supply parameters of each test socket are independently adjustable, which is beneficial for multi-channel parallel testing.

[0048] The flash memory chip testing system provided in this embodiment also features PID voltage control to ensure high-precision adjustment and stability of the voltage dimension in the SHMOO test. Specifically, the flash memory chip testing system also includes a voltage regulation module; please refer to [link / reference needed]. Figure 1The voltage regulation module includes multiple voltage acquisition chips 500, which are respectively located between the ONFI test socket 310 and the power chip 410, and between the SPI test socket 320 and the power chip 410. The voltage acquisition chips 500 are used to acquire the voltage of the ONFI test socket 310 and the SPI test socket 320.

[0049] The voltage acquisition chip 500 can be a TI INA226, capable of sampling actual voltage with an accuracy of ±0.1mV and a sampling frequency of 1kHz to 10kHz, through multiple I / O channels. 2 The C bus operates in parallel to improve the overall sampling throughput.

[0050] In actual operation, the target voltage is first set by the host computer 200, ranging from 1.5V to 3.6V, with a typical step of 1mV (0.001V). This value is then sent to the main control module 100 via USB, and subsequently transmitted by the main control module 100 to the microcontroller unit 420. The voltage acquisition chip 500 samples the actual voltage in real time. The microcontroller unit 420 receives the sampled data and performs standard discrete PID control calculations, including error calculation and PID control output calculation. The microcontroller unit 420 ensures that the PID cycle of each test socket is precisely controllable, avoiding scheduling interference. Based on the PID control output calculation results, the microcontroller unit 420 outputs a signal to the DAC unit. The DAC unit performs digital-to-analog conversion, driving the power supply chip 410 to output voltage, achieving high-precision dynamic voltage regulation. The DAC unit uses DMA to ensure stable, low-latency response.

[0051] Please refer to Figure 1 The flash memory chip testing system also includes an Ethernet module 600. The signal processing module 300 is equipped with a network interface. The Ethernet module 600 is connected to the host computer 200 and the network interface to upload the test data of the signal processing module 300 to the host computer 200.

[0052] The Ethernet module 600 can be a PHY chip, which is electrically isolated and has strong anti-interference capabilities. It connects to the signal processing module 300 via a network interface and establishes a connection with the host computer 200 via a standard RJ45 Ethernet interface. The host computer 200 receives test data from the signal processing module 300 through the Ethernet module 600. The host computer 200 then performs real-time analysis, buffering, and processing of the data, generating two-dimensional or three-dimensional Shmoo plots to demonstrate the flash memory chip's response under different voltage, current, and frequency conditions.

[0053] In some embodiments, the signal processing module 300 includes an FPGA logic unit, with an ONFI interface and an SPI interface integrated on the FPGA logic unit. The FPGA logic unit has a high-performance logic architecture, capable of implementing various complex logic functions; it also has powerful digital signal processing capabilities; it integrates analog mixed-signal functions, providing greater flexibility for system integration; and it is programmed using the Verilog language to meet different testing requirements.

[0054] By implementing ONFI protocol logic, such as command decoding and data transmission timing control, within the FPGA logic unit, testing of ONFI interface flash memory chips is supported. Simultaneously, the FPGA logic unit can also implement SPI / QSPI protocol logic, supporting testing of SPI interface flash memory chips, thus enhancing the flexibility and versatility of this invention.

[0055] The above are only some or preferred embodiments of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the contents of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A flash memory chip testing system, characterized in that, include: The main control module is communicatively connected to a host computer. The signal processing module is communicatively connected to the main control module. The signal processing module is provided with at least one test unit. The at least one test unit includes an ONFI interface and at least one SPI interface. The ONFI interface is connected to an ONFI test socket, and the at least one SPI interface is connected to an SPI test socket. A power supply module is connected to the main control module and the signal processing module, and is used to supply power to the main control module and the signal processing module.

2. The flash memory chip testing system according to claim 1, characterized in that, At least one of the test units includes two SPI interfaces, and both SPI interfaces are connected to the SPI test socket.

3. The flash memory chip testing system according to claim 2, characterized in that, The test unit is set up with four groups.

4. The flash memory chip testing system according to claim 3, characterized in that, The power module includes power chips in the same number as the ONFI test socket and the SPI test socket, and the power chips are respectively connected to the ONFI test socket and the SPI test socket.

5. The flash memory chip testing system according to claim 4, characterized in that, The power module further includes a microcontroller unit connected to the main control module. Each of the power chips is electrically connected to the microcontroller unit, and the microcontroller unit is used to drive the power chip to work under the control of the main control module.

6. The flash memory chip testing system according to claim 5, characterized in that, The power module also includes DAC units in the same number as the power chips. The DAC units are electrically connected to the microcontroller unit to perform digital-to-analog conversion on the output signal of the microcontroller unit.

7. The flash memory chip testing system according to claim 6, characterized in that, The flash memory chip testing system further includes a voltage regulation module, which includes multiple voltage acquisition chips. The multiple voltage acquisition chips are respectively located between the ONFI test socket and the power supply chip, and between the SPI test socket and the power supply chip. The voltage acquisition chips are used to acquire the voltage of the ONFI test socket and the SPI test socket.

8. The flash memory chip testing system according to claim 1, characterized in that, The flash memory chip testing system also includes an Ethernet module. The signal processing module is equipped with a network interface. The Ethernet module is communicatively connected to the host computer and the network interface to upload the test data of the signal processing module to the host computer.

9. The flash memory chip testing system according to claim 1, characterized in that, It also includes a storage medium connected to the main control module, which is used to store test data.

10. The flash memory chip testing system according to any one of claims 1 to 9, characterized in that, The signal processing module includes an FPGA logic unit, and the ONFI interface and the SPI interface are integrated on the FPGA logic unit.

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