Access control system unlocking circuit, access controller and access control system

Abstract

The utility model relates to a kind of access control system unlocking circuit, access controller and access control system, wherein, the unlocking circuit includes detection circuit, trigger circuit and control circuit;Detection circuit is connected with the main control chip and control circuit of access control system, for receiving the input signal of main control chip, according to the level variation state of input signal, corresponding first level signal is output to control circuit;Trigger circuit is connected with control circuit, for according to the unlocking trigger signal received, corresponding second level signal is output to control circuit;Control circuit is used to export corresponding door lock control signal according to first level signal and second level signal, to control the door lock state of access control system, solved when access control hardware and software system occurs exception, easily lead to unlocking function failure, to avoid influence traffic, it is realized under the condition that access control hardware and software system occurs exception, ensure that can normally unlock.

Description

Technical Field

[0001] This utility model relates to the field of access control technology, and in particular to an access control system unlocking circuit, access control controller and access control system. Background Technology

[0002] Access control systems are systems that manage and control the entry and exit permissions of personnel or vehicles. Based on intelligent identification technology, they combine hardware and software such as electronic locks, controllers, and management software to achieve access control for specific areas (such as office buildings and residential communities). This prevents unauthorized personnel from entering and records entry and exit information, making it an important component of a security system.

[0003] However, the normal operation of existing access control systems relies heavily on the coordination of various hardware and software components. When the hardware and software systems malfunction (such as software crashes or hardware component damage), the unlocking function often fails, thus preventing normal passage.

[0004] There is currently no effective solution to the problem that when the access control software and hardware system malfunctions, the unlocking function may fail, thus preventing normal passage. Utility Model Content

[0005] Therefore, it is necessary to provide an access control system unlocking circuit, access control controller, and access control system to address the problem that when the access control software and hardware system malfunctions, the unlocking function is easily lost, thus preventing normal passage.

[0006] Firstly, this utility model provides an unlocking circuit for an access control system, the unlocking circuit including a detection circuit, a triggering circuit, and a control circuit;

[0007] The detection circuit is connected to the main control chip of the access control system and the control circuit, and is used to receive the input signal of the main control chip and output a corresponding first level signal to the control circuit according to the level change state of the input signal.

[0008] The trigger circuit is connected to the control circuit and is used to output a corresponding second-level signal to the control circuit according to the received unlocking trigger signal;

[0009] The control circuit is used to output a corresponding door lock control signal based on the first level signal and the second level signal, so as to control the door lock status of the access control system.

[0010] In some embodiments, the detection circuit includes a first charge / discharge circuit, a field-effect transistor Q1, and a resistor R1;

[0011] The first charging and discharging circuit is connected to the gate of the field-effect transistor Q1;

[0012] The drain of the field-effect transistor Q1 is connected to the control circuit and the resistor R1;

[0013] The source of the field-effect transistor Q1 is grounded.

[0014] In some embodiments, the first charging and discharging circuit includes a resistor R2, a capacitor C1, a diode D1, a resistor R3, and a capacitor C2;

[0015] One end of the capacitor C1 is connected to the resistor R2; the other end of the capacitor C1 is connected to one end of the diode D1.

[0016] The other end of the diode D1 is connected to the gate of the field-effect transistor Q1;

[0017] One end of the capacitor C2 is connected to the gate of the field-effect transistor Q1; the other end of the capacitor C2 is grounded.

[0018] One end of the resistor R3 is connected to the gate of the field-effect transistor Q1; the other end of the resistor R3 is grounded.

[0019] In some embodiments, the first charge-discharge circuit further includes a diode D2;

[0020] One end of the diode D2 is connected to the capacitor C1 and the diode D1; the other end of the diode D2 is grounded.

[0021] In some embodiments, the trigger circuit includes a trigger U1, a diode D3, a capacitor C3, and a resistor R4;

[0022] One end of the diode D3 is connected to the trigger U1; the other end of the diode D3 is connected to the control circuit.

[0023] One end of capacitor C3 is connected to the control circuit; the other end of capacitor C3 is grounded.

[0024] One end of the resistor R4 is connected to the control circuit; the other end of the resistor R4 is grounded.

[0025] In some embodiments, the door lock opening time of the access control system is determined based on the discharge curve characteristics of the capacitor C3 and the resistance value of the resistor R4.

[0026] In some embodiments, the trigger circuit further includes resistors R5 and R6;

[0027] One end of the resistor R5 is connected to the trigger U1; the other end of the resistor R5 is connected to the diode D3.

[0028] One end of the resistor R6 is connected to the diode D3; the other end of the resistor R6 is grounded.

[0029] In some embodiments, the unlocking circuit further includes a reset circuit; the reset circuit includes a second charging / discharging circuit, a trigger U2, and a third charging / discharging circuit.

[0030] The second charging and discharging circuit is connected to the input terminals of the detection circuit and the trigger U2;

[0031] The third charging and discharging circuit is connected to the output terminal of the trigger U2.

[0032] In some embodiments, the second charging and discharging circuit includes a resistor R7, a capacitor C4, a resistor R8, and a capacitor C5;

[0033] One end of the resistor R7 is connected to the detection circuit; the other end of the resistor R7 is connected to one end of the capacitor C4.

[0034] One end of the resistor R8 is connected to the other end of the capacitor C4; the other end of the resistor R8 is grounded.

[0035] One end of the capacitor C5 is connected to one end of the resistor R8 and the input terminal of the flip-flop U2; the other end of the capacitor C5 is connected to the other end of the resistor R8.

[0036] In some embodiments, the third charging and discharging circuit includes resistor R9, resistor R10, and capacitor C6;

[0037] One end of the resistor R10 is connected to the output terminal of the flip-flop U2;

[0038] One end of the resistor R9 is connected to the input voltage; the other end of the resistor R9 is connected to the other end of the resistor R10 and the capacitor C6.

[0039] The connection node of resistor R9, resistor R10 and capacitor C6 is used to output the reset signal of the main control chip.

[0040] In some embodiments, the control circuitry includes an AND gate logic controller;

[0041] The first input terminal of the AND gate logic controller is connected to the detection circuit;

[0042] The second input terminal of the AND gate logic controller is connected to the trigger circuit;

[0043] The output of the AND gate logic controller is connected to the door lock of the access control system.

[0044] Secondly, this utility model provides an access control controller, which includes a main control chip and the access control system unlocking circuit described in the first aspect.

[0045] Thirdly, this utility model provides an access control system, which includes the access controller described in the second aspect above.

[0046] Compared with related technologies, this utility model provides an access control system unlocking circuit, access control controller, and access control system. The unlocking circuit includes a detection circuit, a triggering circuit, and a control circuit. The detection circuit, connected to the main control chip and control circuit of the access control system, receives input signals from the main control chip and outputs a corresponding first-level signal to the control circuit based on the level changes of the input signals. The triggering circuit, connected to the control circuit, outputs a corresponding second-level signal to the control circuit based on the received unlocking trigger signal. The control circuit outputs a corresponding door lock control signal based on the first and second level signals to control the door lock status of the access control system. This solves the problem that when the access control hardware and software system malfunctions, the unlocking function easily fails, preventing normal passage. It ensures normal unlocking even when the access control hardware and software system malfunctions, thus avoiding disruption to passage.

[0047] Details of one or more embodiments of the present invention are set forth in the following drawings and description to make other features, objects and advantages of the present application more readily apparent. Attached Figure Description

[0048] Figure 1 This is a structural block diagram of an access control system unlocking circuit provided in one embodiment of this application;

[0049] Figure 2 This is a schematic diagram of a first charging and discharging circuit provided in an embodiment of this application;

[0050] Figure 3 This is a schematic diagram of a trigger circuit provided in an embodiment of this application;

[0051] Figure 4 This is a schematic diagram of a reset circuit provided in an embodiment of this application;

[0052] Figure 5 This is a schematic diagram of a control circuit provided in an embodiment of this application;

[0053] Figure 6 This is a schematic diagram of the unlocking circuit of an access control system provided in a preferred embodiment of this application;

[0054] Figure 7 This is a schematic diagram of the unlocking circuit of an access control system provided in one embodiment of this application.

[0055] Reference numerals: 100, unlocking circuit; 10, detection circuit; 11, first charging / discharging circuit; 20, trigger circuit; 30, control circuit; 40, reset circuit; 41, second charging / discharging circuit; 42, third charging / discharging circuit; 200, main control chip. Detailed Implementation

[0056] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0057] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] This utility model provides an unlocking circuit 100 for an access control system. Figure 1 This is a structural block diagram of the unlocking circuit 100 of the access control system according to an embodiment of the present invention, as shown below. Figure 1 As shown, the unlocking circuit 100 includes a detection circuit 10, a triggering circuit 20, and a control circuit 30;

[0060] The detection circuit 10 is connected to the main control chip and control circuit 30 of the access control system. It is used to receive the input signal from the main control chip and output the corresponding first level signal to the control circuit 30 according to the level change of the input signal.

[0061] The trigger circuit 20 is connected to the control circuit 30 and is used to output a corresponding second-level signal to the control circuit 30 according to the received unlocking trigger signal.

[0062] The control circuit 30 is used to output a corresponding door lock control signal based on the first level signal and the second level signal, so as to control the door lock status of the access control system.

[0063] Specifically, the detection circuit 10 is connected to the main control chip and control circuit 30 of the access control system, and its input terminal receives the input signal from the main control chip. This signal is output by the main control chip, which is the decision-making core of the access control system and typically undertakes functions such as signal processing, logic judgment, and communication scheduling. It changes the high and low level states of the signal every preset time interval (e.g., 10ms), i.e., toggles the signal once. A normal signal toggle indicates that the main control chip is in normal working condition, meaning the hardware and software system of the access control system is normal. Conversely, a faulty signal indicates an abnormality in the hardware and software system of the access control system.

[0064] When an input signal is received, the detection circuit 10 outputs a corresponding first-level signal to the control circuit 30 based on the level change of the input signal. Specifically, if the signal switching is detected as normal based on the level change of the input signal, that is, the input signal changes between high and low levels according to a preset time, the output first-level signal is low; if the signal switching is detected as abnormal based on the level change of the input signal, that is, the input signal switching stops (remaining in a high or low level state), the output first-level signal is high.

[0065] The trigger circuit 20 is connected to the control circuit 30. Its input terminal receives an unlocking trigger signal, which can be input via user operation buttons, remote terminal commands, etc., without specific limitations. When the trigger circuit 20 receives the unlocking trigger signal, it outputs a corresponding second-level signal to the control circuit 30. The second-level signal is high. It should be noted that when the trigger circuit 20 does not receive an unlocking trigger signal, the second-level signal remains low.

[0066] Furthermore, the control circuit 30 outputs corresponding door lock control signals based on the first level signal and the second level signal. This control circuit 30 is typically implemented using an AND gate circuit or an AND gate chip, but can also be equivalently implemented using a NAND gate logic circuit combined with an inverter; no specific limitation is made here.

[0067] When both the first and second level signals are high, the control circuit 30 outputs a door lock control signal to control the door lock of the access control system to open, allowing the user to pass normally; when either the first or second level signal is low, the control circuit 30 does not output a door lock control signal, and the door lock of the access control system will not be triggered to open by this circuit.

[0068] The normal operation of existing access control systems relies heavily on the coordination of various hardware and software components. When the hardware and software systems malfunction (such as software crashes or hardware component damage), the unlocking function often fails, thus preventing normal passage.

[0069] Compared to existing technologies, the unlocking circuit in this application includes a detection circuit, a triggering circuit, and a control circuit. The detection circuit is connected to the main control chip and control circuit of the access control system, receiving input signals from the main control chip and outputting a corresponding first-level signal to the control circuit based on the level changes of the input signals. The triggering circuit is connected to the control circuit, outputting a corresponding second-level signal to the control circuit based on the received unlocking trigger signal. The control circuit outputs a corresponding door lock control signal based on the first and second level signals to control the door lock state of the access control system. Based on this, by constructing an unlocking circuit independent of the main control chip, even when the main control chip malfunctions due to software crashes or hardware failures, the triggering circuit can still directly drive the door lock action through the logic of the control circuit. This solves the problem that unlocking functionality easily fails when the access control software and hardware system malfunctions, preventing normal passage. It ensures normal unlocking even when the access control software and hardware system malfunctions, thus avoiding disruption to passage.

[0070] In some embodiments, the detection circuit 10 includes a first charge / discharge circuit 11, a field-effect transistor Q1, and a resistor R1;

[0071] The first charging and discharging circuit 11 is connected to the gate of the field-effect transistor Q1;

[0072] The drain of the field-effect transistor Q1 is connected to the control circuit 30 and the resistor R1;

[0073] The source of the field-effect transistor Q1 is grounded.

[0074] Specifically, when the input signal flips normally, indicating that the hardware and software system is functioning correctly, the first charging and discharging circuit 11 remains nearly fully charged, the field-effect transistor Q1 is in the on state, and the first level signal output by the detection circuit 10 is low. At this time, if the trigger circuit 20 does not receive an unlocking trigger signal, the second level signal remains low, and the control circuit 30 does not output a door lock control signal; if the trigger circuit 20 receives an unlocking trigger signal, the second level signal it outputs is high, and the control circuit 30 also does not output a door lock control signal. This ensures that, under normal hardware and software system conditions, the circuit will not trigger the output of a door lock control signal.

[0075] When the input signal stops flipping, indicating a hardware / software system malfunction, the first charging / discharging circuit 11 remains in a discharging state. The field-effect transistor Q1 is cut off due to its gate voltage dropping below the turn-on threshold, and the first level signal output by the detection circuit 10 is high. At this time, if the trigger circuit 20 receives an unlocking trigger signal, its second level signal will be high, and the control circuit 30 will also not output a door lock control signal. This ensures normal unlocking even in the event of a hardware / software system malfunction.

[0076] In this embodiment, the detection circuit 10 includes a first charging and discharging circuit 11, a field-effect transistor Q1, and a resistor R1. The first charging and discharging circuit 11 is connected to the gate of the field-effect transistor Q1, the drain of the field-effect transistor Q1 is connected to the control circuit 30 and the resistor R1, and the source of the field-effect transistor Q1 is grounded. Thus, the detection circuit 10 adapts to the level change of the input signal and outputs a corresponding first level signal, thereby avoiding false triggering when the software and hardware are normal, while ensuring that normal unlocking can still be achieved when the system is abnormal.

[0077] In some of these embodiments, such as Figure 2 As shown, the first charging and discharging circuit 11 includes a resistor R2, a capacitor C1, a diode D1, a resistor R3, and a capacitor C2;

[0078] One end of capacitor C1 is connected to resistor R2; the other end of capacitor C1 is connected to one end of diode D1.

[0079] The other end of diode D1 is connected to the gate of field-effect transistor Q1;

[0080] One end of capacitor C2 is connected to the gate of field-effect transistor Q1; the other end of capacitor C2 is grounded.

[0081] One end of resistor R3 is connected to the gate of field-effect transistor Q1; the other end of resistor R3 is grounded.

[0082] Specifically, the first charging / discharging circuit 11 includes a resistor R2, a capacitor C1, a diode D1, a resistor R3, and a capacitor C2. Capacitor C1 is a DC blocking capacitor. When the input signal flips normally, the signal can be transmitted to subsequent circuits through capacitor C1. Diode D1 is forward-biased, and current flows through D1 to charge capacitor C2. After charging, capacitor C2 remains nearly fully charged. This charging causes the gate voltage of the field-effect transistor Q1 to rise and remain above its turn-on threshold voltage, thus turning on the field-effect transistor Q1. At this time, the output first-level signal is low.

[0083] When the input signal stops flipping, i.e., remains at a high or low level, capacitor C1 blocks the DC signal, effectively making capacitor C1 an open circuit, and capacitor C2 discharges through resistor R3. When capacitor C2 discharges, MOSFET Q1 is turned off because its gate voltage drops below the turn-on threshold, and the first level signal output by detection circuit 10 is high.

[0084] In this embodiment, the first charging and discharging circuit 11 is composed of resistor R2, capacitor C1, diode D1, resistor R3 and capacitor C2. It can charge and discharge according to the level change of the input signal, so as to change the state of the field-effect transistor Q1 accordingly and realize the accurate control of the first level signal.

[0085] In some of these embodiments, such as Figure 2 As shown, the first charging and discharging circuit 11 also includes a diode D2;

[0086] One end of diode D2 is connected to capacitor C1 and diode D1; the other end of diode D2 is grounded.

[0087] Specifically, the first charging and discharging circuit 11 also includes a diode D2. One end of diode D2 is connected to capacitor C1 and diode D1, and the other end of diode D2 is grounded. It can be understood that diode D2 prevents the gate of field-effect transistor Q1 from failing due to negative voltage breakdown by limiting the reverse voltage of capacitor C1.

[0088] In this embodiment, the first charging and discharging circuit 11 also includes a diode D2. One end of the diode D2 is connected to the capacitor C1 and the diode D1, and the other end of the diode D2 is grounded, which plays a clamping protection role and ensures the stability of the circuit.

[0089] In some of these embodiments, such as Figure 3 As shown, the trigger circuit 20 includes a trigger U1, a diode D3, a capacitor C3, and a resistor R4;

[0090] One end of diode D3 is connected to trigger U1; the other end of diode D3 is connected to control circuit 30.

[0091] One end of capacitor C3 is connected to control circuit 30; the other end of capacitor C3 is grounded.

[0092] One end of resistor R4 is connected to control circuit 30; the other end of resistor R4 is grounded.

[0093] Specifically, when trigger U1 does not capture the unlock trigger signal, the output of trigger U1 is in a low-level state, and diode D3 is in the off state. Correspondingly, due to the pull-down effect of resistor R4, the second-level signal output by trigger circuit 20 is low.

[0094] When trigger U1 captures the unlock trigger signal, trigger U1 outputs a high level, causing diode D3 to conduct in the forward direction. This charges capacitor C3 through diode D3, and at this time, the second level signal output by trigger circuit 20 is high.

[0095] It should be noted that when the input signal stops flipping, the first level signal output by the detection circuit 10 is high. At this time, if the trigger U1 captures the unlock trigger signal, the second level signal output is high, and the control circuit 30 will output a door lock control signal to control the door lock of the access control system to open.

[0096] In this embodiment, the trigger circuit 20 consists of a trigger U1, a diode D3, a capacitor C3, and a resistor R4. When an unlocking trigger signal is received, the capacitor C3 is charged to output a high level to the control circuit 30, thereby triggering the unlocking signal in the event of an abnormality in the access control software and hardware system.

[0097] In some embodiments, the door lock opening time of the access control system is determined based on the discharge curve characteristics of capacitor C3 and the resistance value of resistor R4.

[0098] Specifically, when the hardware and software system malfunctions and the input signal stops flipping, the first level signal output by the detection circuit 10 is low. At this time, if the trigger U1 captures the unlock trigger signal, the trigger U1 outputs a high level, causing the diode D3 to conduct in the forward direction. The capacitor C3 is charged through the diode D3, and the second level signal output by the trigger circuit 20 is high.

[0099] It should be noted that when capacitor C3 charges to near the high level of trigger U1, diode D3 is cut off, and capacitor C3 then discharges to ground through resistor R4, causing the second-level signal voltage output by trigger circuit 20 to continuously decrease. When this voltage drops to the low-level threshold set by control circuit 30, the access control system closes the door lock. The duration of the door lock's opening is determined by this discharge process, and its duration depends on the combination of the discharge characteristics of capacitor C3 and the resistance value of resistor R4.

[0100] In this embodiment, the access control system utilizes the discharge time characteristics of capacitor C3 and the resistance value of resistor R4 to control the door lock opening time in a coordinated manner, thereby enabling the system to quickly adapt to emergency opening needs in different scenarios and improve the customization capability of the strategy and the efficiency of emergency response.

[0101] In some of these embodiments, such as Figure 3 As shown, the trigger circuit 20 also includes resistors R5 and R6;

[0102] One end of resistor R5 is connected to flip-flop U1; the other end of resistor R5 is connected to diode D3.

[0103] One end of resistor R6 is connected to diode D3; the other end of resistor R6 is grounded.

[0104] Specifically, the trigger circuit 20 also includes a resistor R5. One end of the resistor R5 is connected to the trigger U1, and the other end of the resistor R5 is connected to the diode D3. When the trigger U1 outputs a high level, current flows through the resistor R5 and the diode D3 to charge the capacitor C3. The resistor R5 is used to limit the transient inrush current and keep the charging current within a safe range.

[0105] In addition, the trigger circuit 20 also includes a resistor R6, one end of which is connected to the diode D3, and the other end of which is grounded. When the trigger U1 outputs a low level, the resistor R6 ensures that the cathode node of the diode D3 is reliably pulled low to 0V, eliminating the risk of voltage floating caused by high impedance and avoiding false triggering.

[0106] In this embodiment, the trigger circuit 20 also includes resistors R5 and R6. One end of resistor R5 is connected to the trigger U1, and the other end of resistor R5 is connected to diode D3. One end of resistor R6 is connected to diode D3, and the other end is grounded, thereby ensuring the reliability of the circuit.

[0107] The following is combined with Figure 4 The reset process of the main control chip is explained in detail.

[0108] In some embodiments, the unlocking circuit further includes a reset circuit 40; the reset circuit 40 includes a second charging / discharging circuit 41, a trigger U2, and a third charging / discharging circuit 42.

[0109] The second charging and discharging circuit 41 is connected to the input terminals of the detection circuit 10 and the trigger U2;

[0110] The third charging and discharging circuit 42 is connected to the output terminal of the trigger U2.

[0111] Understandably, when an input signal is received, the detection circuit 10 outputs a corresponding first-level signal to the second charging / discharging circuit 41 based on the level change of the input signal. If the signal switching is detected as normal based on the level change of the input signal, i.e., the input signal changes between high and low levels according to a preset time, the output first-level signal is low. If the signal switching is detected as abnormal based on the level change of the input signal, i.e., the input signal switching stops (remaining in a high or low level state), the output first-level signal is high.

[0112] When the first level signal output by the detection circuit 10 is high, the second charging / discharging circuit 41 charges, causing the input pin (A2) of the trigger U2 to be pulled high. At this time, the output terminal (Y2) of the trigger U2 outputs a low level, causing the third charging / discharging circuit 42 to enter the discharging process. The output terminal of the third charging / discharging circuit 42 stably outputs the reset signal SOC_RSTn, thereby reliably triggering the main control chip to perform a reset operation. Conversely, when the first level signal output by the detection circuit 10 is low, the second charging / discharging circuit 41 discharges, pulling the input pin of the trigger U2 low, and the trigger U2 outputs a high level, causing the third charging / discharging circuit 42 to enter the charging process. In this case, the reset signal SOC_RSTn will not be triggered.

[0113] In practice, trigger U2 can be a Schmitt trigger.

[0114] The reset circuit 40 provided in this embodiment can reliably trigger the main control chip to perform a reset operation when an abnormal signal flip is detected, so as to quickly restore the normal working state of the main control chip and significantly improve the stability and reliability of the circuit.

[0115] In some embodiments, the second charging / discharging circuit 41 includes a resistor R7, a capacitor C4, a resistor R8, and a capacitor C5;

[0116] One end of resistor R7 is connected to the detection circuit; the other end of resistor R7 is connected to one end of capacitor C4.

[0117] One end of resistor R8 is connected to the other end of capacitor C4; the other end of resistor R8 is grounded.

[0118] One end of capacitor C5 is connected to one end of resistor R8 and the input terminal of flip-flop U2; the other end of capacitor C5 is connected to the other end of resistor R8.

[0119] When the first level signal output by the detection circuit 10 is high, capacitors C4 and C5 are charged, causing the input pin of trigger U2 to be pulled high. At this time, trigger U2 outputs a low level, causing the third charge-discharge circuit 42 to discharge. The output of the third charge-discharge circuit 42 stably outputs a reset signal SOC_RSTn, causing the main control chip to perform a reset operation.

[0120] When the first level signal output by the detection circuit 10 is low, capacitors C4 and C5 discharge, pulling down the input pin of trigger U2. Then, trigger U2 outputs a high level, causing the third charging and discharging circuit 42 to charge. At this time, the reset signal SOC_RSTn will not be triggered.

[0121] In specific implementation, the second charging / discharging circuit 41 also includes a clamping diode D4, a resistor R11, and a capacitor C7. The clamping diode D4 and resistor R11 are connected in series between capacitor C4 and trigger U2, with the clamping diode D4 grounded. This allows the clamping diode D4 to quickly respond to instantaneous overvoltage, preventing excessive voltage from damaging the input of trigger U2. Simultaneously, resistor R11 works with the clamping diode D4 to limit current, providing synergistic protection and improving circuit stability. Capacitor C7 is a filter capacitor connected to the VCC pin of the AND gate logic controller (connected to a 3.3V power supply).

[0122] In this embodiment, when an abnormal or normal signal flip is detected, the second charging and discharging circuit 41 ensures that the input pin level of the trigger U2 rises or falls steadily and gradually, thereby helping to reliably and accurately trigger the reset.

[0123] In some of these embodiments, the third charging / discharging circuit 42 includes resistors R9 and R10 and capacitor C6;

[0124] One end of resistor R10 is connected to the output of flip-flop U2;

[0125] One end of resistor R9 is connected to the input voltage; the other end of resistor R9 is connected to the other end of resistor R10 and capacitor C6.

[0126] The connection point of resistors R9 and R10 and capacitor C6 is used to output the reset signal of the main control chip.

[0127] When the first level signal output by the detection circuit 10 is high, the second charging and discharging circuit 41 charges, causing the input pin of the trigger U2 to be pulled high. At this time, the trigger U2 outputs a low level, causing the capacitor C6 to discharge. The connection node of resistors R9 and R10 and capacitor C6 stably outputs a reset signal SOC_RSTn, causing the main control chip to perform a reset operation.

[0128] When the first level signal output by the detection circuit 10 is low, the second charging and discharging circuit 41 discharges, pulling down the input pin of the trigger U2. Then the trigger U2 outputs a high level, causing the capacitor C6 to charge. At this time, the reset signal SOC_RSTn will not be triggered.

[0129] Thus, the third charging and discharging circuit 42 provided in this embodiment ensures accurate and effective output of the reset signal in case of abnormality.

[0130] In some of these embodiments, such as Figure 5 As shown, the control circuit 30 includes an AND gate logic controller;

[0131] The first input terminal of the AND gate logic controller is connected to the detection circuit 10;

[0132] The second input terminal of the AND gate logic controller is connected to the trigger circuit 20;

[0133] The output of the AND gate logic controller is connected to the door lock of the access control system.

[0134] In this embodiment, the control circuit 30 includes an AND gate logic controller. The first input terminal (A) of the AND gate logic controller is connected to the detection circuit 10, and the second input terminal (B) of the AND gate logic controller is connected to the trigger circuit 20.

[0135] Specifically, when the input signal flips normally, the detection circuit 10 outputs a first-level signal to the first input terminal of the AND gate logic controller, and the first-level signal is low. At this time, regardless of whether the trigger circuit 20 captures the unlock trigger signal, the output terminal (Y) of the AND gate logic controller will not output a door lock control signal.

[0136] When the input signal flips abnormally, i.e., the input signal flips stop (remaining in a high or low level state), the detection circuit 10 outputs to the first input terminal of the AND gate logic controller, and the first level signal is high. At this time, if the trigger circuit 20 captures the unlock trigger signal, it outputs a second level signal to the second input terminal of the AND gate logic controller, and the second level signal is high. Then, the AND gate logic controller outputs a door lock control signal to control the door lock to open.

[0137] In this embodiment, an AND gate logic controller is used to output corresponding door lock control signals based on the first level signal and the second level signal to control the door lock status of the access control system. This can avoid false triggering when the hardware and software are normal, while ensuring that normal unlocking can still be achieved when the system is abnormal.

[0138] The present embodiment will now be described and illustrated through preferred embodiments.

[0139] Figure 6 This is a schematic diagram of the unlocking circuit of an access control system provided in a preferred embodiment of this application, as shown below. Figure 6 As shown, the access control system's unlocking circuit includes a detection circuit 10, a trigger circuit 20, a control circuit 30, and a reset circuit 40; wherein, the detection circuit 10 is connected to the access control system's main control chip, the control circuit 30, and the reset circuit 40; and the trigger circuit 20 is connected to the control circuit 30.

[0140] Specifically, the input terminal of the detection circuit 10 receives the input signal DOOR_FEED_SIG from the main control chip. This signal is output by the main control chip, which changes its high and low level states every preset time interval (e.g., 10ms), i.e., toggles the signal once. If the signal toggles normally, it indicates that the main control chip is in normal working condition, meaning that the access control system's hardware and software are functioning normally. Conversely, if the signal toggles abnormally, it indicates that the access control system's hardware and software are malfunctioning.

[0141] The detection circuit 10 includes a first charging / discharging circuit 11, a field-effect transistor (FET) Q1, and a resistor R1. The first charging / discharging circuit 11 consists of a resistor R2, a capacitor C1, a diode D1, a resistor R3, and a capacitor C2. Capacitor C1 is a DC blocking capacitor. When the input signal flips normally, diode D1 conducts forward, and current flows through D1 to charge capacitor C2. After charging, capacitor C2 remains nearly fully charged, causing the gate voltage of FET Q1 to rise and remain above its turn-on threshold voltage. At this time, FET Q1 is turned on, and the first level signal output by the detection circuit 10 is low. When the input signal stops flipping, i.e., remains at a high or low level, capacitor C1 blocks the DC signal, effectively acting as an open circuit. Capacitor C2 discharges through resistor R3. When capacitor C2 discharges, FET Q1 is turned off because its gate voltage drops below the turn-on threshold, and the first level signal output by the detection circuit 10 is high.

[0142] The first charging and discharging circuit 11 also includes a diode D2. The diode D2 limits the reverse voltage of the capacitor C1 to prevent the gate of the field-effect transistor Q1 from failing due to negative voltage breakdown.

[0143] The trigger circuit 20 includes a trigger U1, a diode D3, a capacitor C3, and a resistor R4. When the input terminal (A1) of the trigger U1 does not capture the unlock trigger signal CON_EXIT_IN1, the output terminal (Y1) of the trigger U1 is in a low-level state, and the diode D3 is in a cutoff state. At this time, due to the pull-down effect of the resistor R4, the second-level signal output by the trigger circuit 20 is low-level. When the trigger U1 captures the unlock trigger signal CON_EXIT_IN1, the trigger U1 outputs a high-level signal, which makes the diode D3 forward conduction, charging the capacitor C3 through the diode D3. At this time, the second-level signal output by the trigger circuit 20 is high-level.

[0144] The trigger circuit 20 also includes resistors R5 and R6. When the output of trigger U1 is high, current flows through resistor R5 and diode D3 to charge capacitor C3. Resistor R5 is used to limit transient inrush current and keep the charging current within a safe range. When trigger U1 is low, resistor R6 ensures that the cathode node of diode D3 is reliably pulled down to 0V, eliminating the risk of voltage floating caused by high impedance and avoiding false triggering.

[0145] The trigger circuit 20 also includes a resistor R12, a capacitor C8, a clamping diode D5, and a capacitor C9. Resistor R12, capacitor C8, and clamping diode D5 are all connected to the input terminal of trigger U1. Capacitor C9 is connected to the VCC pin (connected to a 5V power supply). Clamping diode D5 is used to protect the input voltage of trigger U1. Capacitors C8 and C9 are both filter capacitors.

[0146] The control circuit 30 includes an AND gate logic controller. The first input (A) of the AND gate logic controller is connected to the detection circuit 10, and the second input (B) is connected to the trigger circuit 20. When the input signal flips normally, the detection circuit 10 outputs a first-level signal to the first input of the AND gate logic controller. Since the first-level signal is low, the AND gate logic controller will not output a door lock control signal regardless of whether the trigger circuit 20 captures the unlock trigger signal. Simultaneously, because the first-level signal output by the detection circuit 10 is high, capacitors C4 and C5 are charged, causing the input pin of trigger U2 to be pulled high. This results in trigger U2 outputting a low level, causing capacitor C6 to discharge and stably outputting a reset signal SOC_RSTn, enabling the main control chip to perform a reset operation.

[0147] It should be noted that the reset circuit 40 also includes a clamping diode D4, a resistor R11, and a capacitor C7. The clamping diode D4 and resistor R11 are connected in series between capacitor C4 and flip-flop U2, with the clamping diode D4 grounded. This allows the clamping diode D4 to quickly respond to transient overvoltages, preventing excessive voltage from damaging the input of flip-flop U2. Simultaneously, resistor R11 works with the clamping diode D4 to limit current, providing synergistic protection and improving circuit stability. Capacitor C7 is a filter capacitor, connected to the VCC pin of the AND gate logic controller (connected to a 3.3V power supply).

[0148] When the input signal flips abnormally, i.e., the input signal flips stop (remaining in a high or low level state), the detection circuit 10 outputs to the first input terminal of the AND gate logic controller, and the first level signal is high. At this time, if the trigger circuit 20 captures the unlock trigger signal, it outputs a second level signal to the second input terminal of the AND gate logic controller, and the second level signal is high. Consequently, the output terminal (Y) of the AND gate logic controller outputs the door lock control signal EXIT1_CTR_EN to control the door lock to open. Simultaneously, since the first level signal output by the detection circuit is low, capacitors C4 and C5 discharge, pulling down the input pin of trigger U2. Then, trigger U2 outputs a high level, causing capacitor C6 to charge. At this time, the reset signal SOC_RSTn will not be triggered.

[0149] The control circuit 30 also includes a capacitor C9 and a resistor R13. The capacitor C10 is a filter capacitor, which is connected to the VCC pin of the AND gate logic controller (connected to a 3.3V power supply); one end of the resistor R13 is connected to the output terminal of the AND gate logic controller, and the other end of the resistor R10 is grounded to ensure stable grounding when the output of the AND gate logic controller is low.

[0150] In this embodiment, when the main control chip malfunctions due to software crash or hardware failure, the trigger circuit 20 can drive the door lock action through the logic of the control circuit 30. This solves the problem that when the access control software and hardware system malfunctions, the unlocking function is easily rendered ineffective, thus preventing normal passage. It ensures normal unlocking even when the access control software and hardware system malfunctions, so as to avoid affecting passage.

[0151] This embodiment also provides an access control controller, such as Figure 7 As shown, the access control controller includes a main control chip 200 and the access control system unlocking circuit 100 of the above embodiments.

[0152] This embodiment also provides an access control system, which includes the access control controller described in the above embodiments.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. An unlocking circuit for an access control system, characterized in that, The unlocking circuit includes a detection circuit, a triggering circuit, and a control circuit; The detection circuit is connected to the main control chip of the access control system and the control circuit, and is used to receive the input signal of the main control chip and output a corresponding first level signal to the control circuit according to the level change state of the input signal. The trigger circuit is connected to the control circuit and is used to output a corresponding second-level signal to the control circuit according to the received unlocking trigger signal; The control circuit is used to output a corresponding door lock control signal based on the first level signal and the second level signal, so as to control the door lock status of the access control system.

2. The access control system unlocking circuit according to claim 1, characterized in that, The detection circuit includes a first charging and discharging circuit, a field-effect transistor Q1, and a resistor R1; The first charging and discharging circuit is connected to the gate of the field-effect transistor Q1; The drain of the field-effect transistor Q1 is connected to the control circuit and the resistor R1; The source of the field-effect transistor Q1 is grounded.

3. The access control system unlocking circuit according to claim 2, characterized in that, The first charging and discharging circuit includes a resistor R2, a capacitor C1, a diode D1, a resistor R3, and a capacitor C2; One end of the capacitor C1 is connected to the resistor R2; the other end of the capacitor C1 is connected to one end of the diode D1. The other end of the diode D1 is connected to the gate of the field-effect transistor Q1; One end of the capacitor C2 is connected to the gate of the field-effect transistor Q1; the other end of the capacitor C2 is grounded. One end of the resistor R3 is connected to the gate of the field-effect transistor Q1; the other end of the resistor R3 is grounded.

4. The unlocking circuit of the access control system according to claim 3, characterized in that, The first charging and discharging circuit also includes diode D2; One end of the diode D2 is connected to the capacitor C1 and the diode D1; the other end of the diode D2 is grounded.

5. The unlocking circuit of the access control system according to claim 1, characterized in that, The trigger circuit includes a trigger U1, a diode D3, a capacitor C3, and a resistor R4; One end of the diode D3 is connected to the trigger U1; the other end of the diode D3 is connected to the control circuit. One end of capacitor C3 is connected to the control circuit; the other end of capacitor C3 is grounded. One end of the resistor R4 is connected to the control circuit; the other end of the resistor R4 is grounded.

6. The unlocking circuit of the access control system according to claim 5, characterized in that, The door lock opening time of the access control system is determined based on the discharge curve characteristics of the capacitor C3 and the resistance value of the resistor R4.

7. The unlocking circuit of the access control system according to claim 5, characterized in that, The trigger circuit also includes resistors R5 and R6; One end of the resistor R5 is connected to the trigger U1; the other end of the resistor R5 is connected to the diode D3. One end of the resistor R6 is connected to the diode D3; the other end of the resistor R6 is grounded.

8. The unlocking circuit of the access control system according to claim 1, characterized in that, The unlocking circuit also includes a reset circuit; the reset circuit includes a second charging / discharging circuit, a trigger U2, and a third charging / discharging circuit. The second charging and discharging circuit is connected to the input terminals of the detection circuit and the trigger U2; The third charging and discharging circuit is connected to the output terminal of the trigger U2.

9. The unlocking circuit of the access control system according to claim 8, characterized in that, The second charging and discharging circuit includes a resistor R7, a capacitor C4, a resistor R8, and a capacitor C5; One end of the resistor R7 is connected to the detection circuit; the other end of the resistor R7 is connected to one end of the capacitor C4. One end of the resistor R8 is connected to the other end of the capacitor C4; the other end of the resistor R8 is grounded. One end of the capacitor C5 is connected to one end of the resistor R8 and the input terminal of the flip-flop U2; the other end of the capacitor C5 is connected to the other end of the resistor R8.

10. The unlocking circuit of the access control system according to claim 8, characterized in that, The third charging and discharging circuit includes resistor R9, resistor R10, and capacitor C6; One end of the resistor R10 is connected to the output terminal of the flip-flop U2; One end of the resistor R9 is connected to the input voltage; the other end of the resistor R9 is connected to the other end of the resistor R10 and the capacitor C6. The connection node of resistor R9, resistor R10 and capacitor C6 is used to output the reset signal of the main control chip.

11. The access control system unlocking circuit according to any one of claims 1 to 10, characterized in that, The control circuit includes an AND gate logic controller; The first input terminal of the AND gate logic controller is connected to the detection circuit; The second input terminal of the AND gate logic controller is connected to the trigger circuit, and the output terminal of the AND gate logic controller is connected to the door lock of the access control system.

12. An access control controller, characterized in that, The access control controller includes a main control chip and an access control system unlocking circuit as described in any one of claims 1 to 11.

13. An access control system, characterized in that, The access control system includes the access controller as described in claim 12.

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