Screenless test system based on a timing control board

Abstract

The embodiment of the application relates to a screen-free test system based on a timing control board, which comprises a host computer, a signal source, a comparison engine and at least one standard timing control board; the host computer is connected with the input end of the signal source; the signal source comprises at least one group of output interfaces, each group of output interfaces comprises two output interfaces with the same specification, a first output interface is connected with the input end of the standard timing control board, and a second output interface is used for connecting the input end of at least one timing control board to be tested with the same specification as the standard timing control board; the comparison engine comprises at least one group of input interfaces, each group of input interfaces comprises a first input interface and at least one second input interface, the first input interface is connected with the output end of the standard timing control board, and each second input interface is used for connecting the output end of a corresponding timing control board to be tested. The technical scheme of the application does not need to use an FPGA chip to simulate the function of a test item of the timing control board to be tested, and the test is simple.

Description

Technical Field

[0001] This application relates to the technical field of timing control board testing, and in particular to a screenless testing system based on a timing control board. Background Technology

[0002] In the LCD manufacturing process, the timing control board (also known as the TCON board) is the core control component that drives the screen to light up, and its functionality determines the display effect. Traditional timing control board testing often relies on actual LCD panels to build the test environment, requiring the use of corresponding LCD panels. Different models of timing control boards require different LCD panels, and the panels are expensive and easily damaged. Therefore, screenless testing of timing control boards has been developed.

[0003] However, screenless testing in related technologies, such as the patent application with publication number CN118762625A, constructs a virtual testing environment using a host computer, image signal generator, and FPGA, eliminating the reliance on physical LCD panels. However, it is limited to single-channel testing, allowing only one timing control board to be tested at a time. For large-scale production scenarios, the testing cycle is long, making it difficult to meet production capacity requirements. Utility Model Content

[0004] In view of this, the present application provides a screenless testing system based on a timing control board to solve at least one problem existing in the background art. It eliminates the need to use an FPGA chip to simulate the function of the test items of the timing control board under test, and the testing is simple.

[0005] In a first aspect, embodiments of this application provide a screenless testing system based on a timing control board, including a host computer, a signal generator, a comparison engine, and at least one standard timing control board, wherein the standard timing control board is a timing control board that has passed the test. The host computer is connected to the input terminal of the signal generator; The signal generator includes at least one set of output interfaces. Each set of output interfaces includes two output interfaces of the same specifications. The first output interface is connected to the input terminal of the standard timing control board, and the second output interface is used to connect to the input terminal of at least one timing control board under test with the same specifications as the standard timing control board. The comparison engine includes at least one set of input interfaces. Each set of input interfaces includes a first input interface and at least one second input interface. The first input interface is connected to the output terminal of the standard timing control board, and each second input interface is used to connect to the output terminal of the corresponding timing control board under test.

[0006] In conjunction with the first aspect of this application, in an alternative embodiment, the signal generator includes at least two sets of output interfaces.

[0007] In conjunction with the first aspect of this application, in an alternative embodiment, different groups of output interfaces support timing control boards of the same and / or different specifications.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, the signal generation source includes a first image signal generator and a second image signal generator, the first image signal generator including the first output interface, and the second image signal generator including the second output interface; or, The signal source is an image signal generator, which includes the first output interface and the second output interface.

[0009] In conjunction with the first aspect of this application, in an alternative embodiment, the comparison engine includes at least one comparison unit, the comparison unit including a first input interface and a second input interface.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, it further includes a first expansion dock with one-to-many conversion, wherein the input terminal of the first expansion dock is connected to the second output interface, and each output terminal is used to connect to the input terminal of the corresponding timing control board under test.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, when a second output interface is used to connect the input terminals of at least two timing control boards under test via the first expansion dock, the comparison engine includes at least two second comparison units, each second comparison unit including a first input interface and a second input interface, wherein each first input interface is connected to the output terminal of the same standard timing control board, and each second input interface is used to connect to the output terminal of the corresponding timing control board under test.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, the comparison engine is integrated into the host computer or the signal generator; or, The comparison engine is an independent device, and its output is connected to the host computer.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, a storage medium is further included for storing screen drive signals generated by the standard timing control board.

[0014] Secondly, this application also provides a screenless testing system based on timing control boards, including a host computer, a signal generator, a comparison engine, and at least one set of timing control boards; each set of timing control boards includes a standard timing control board and at least one timing control board under test, wherein the standard timing control board is a qualified timing control board and has the same specifications as each of the timing control boards under test; The host computer is connected to the input terminal of the signal generator; The signal generator includes at least one set of output interfaces, each set of output interfaces includes two output interfaces, the first output interface is connected to the input terminal of the standard timing control board, and the second output interface is connected to the input terminal of each timing control board under test respectively. The comparison engine includes at least one set of input interfaces. Each set of input interfaces includes a first input interface and at least one second input interface. The first input interface is connected to the output terminal of the standard timing control board, and the second input interface is connected to the output terminal of each timing control board under test.

[0015] The technical solution of this application uses a standard timing control board as the test benchmark for the timing control board under test. It eliminates the need to simulate the input / output format conversion of the timing control board under test. The comparison engine performs a consistency comparison between the outputs of the standard timing control board and the timing control board under test, thereby determining whether the function of the test item of the timing control board under test is qualified. The test is simple. Furthermore, this application is not limited to testing a single timing control board under test. When the signal source is connected to multiple timing control boards under test, multiple timing control boards under test can be tested simultaneously, improving test efficiency.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A first structural block diagram of a screenless testing system based on a timing control board provided in an embodiment of this application; Figure 2 A second structural block diagram of a screenless testing system based on a timing control board provided in an embodiment of this application; Figure 3 A third structural block diagram of a screenless testing system based on a timing control board provided in an embodiment of this application; Figure 4 A fourth structural block diagram of a screenless testing system based on a timing control board provided in an embodiment of this application; Figure 5 The fifth structural block diagram of the screenless testing system based on a timing control board provided in the embodiments of this application; Figure 6 The sixth structural block diagram of the screenless testing system based on a timing control board provided in the embodiments of this application; Figure 7 The seventh structural block diagram of the screenless testing system based on a timing control board provided in the embodiments of this application. Detailed Implementation

[0018] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0019] This application provides a screenless testing system based on a timing control board for functional testing of at least one timing control board under test (hereinafter referred to as the board under test). Functional testing of the board under test refers to verifying whether the board under test can complete the normal input-to-output format conversion. The system includes a host computer, a signal generator, a comparison engine, and at least one standard timing control board (hereinafter referred to as the standard board), which is a qualified timing control board. The host computer is connected to the input terminal of the signal generator. The signal generator includes at least one set of output interfaces, each set including two identical output interfaces. One output interface connects to the input terminal of the standard timing control board, referred to as the first output interface, and the other output interface connects to the input terminal of at least one timing control board under test with the same specifications as the standard timing control board, referred to as the second output interface. The comparison engine includes at least one set of input interfaces, each set including a first input interface and at least one second input interface. The first input interface connects to the output terminal of the standard timing control board, and each second input interface connects to the output terminal of the corresponding timing control board under test.

[0020] like Figure 1 As shown, taking an example with only one standard board and one board under test (DUT), the user selects the standard board that matches the DUT as the reference. The signal generator includes a first output interface and a second output interface, and the comparison engine includes a first input interface and a second output interface. The first output interface is connected to the first input interface through the standard board, and the second output interface is connected to the second input interface through the DUT. The system has two test channels: one for the standard board and the other for the DUT.

[0021] Under user instructions, the host computer begins testing the board under test (DUT). The host computer sends test parameters stored in its memory to the signal generator. These parameters include test image materials and channel configuration parameters. The channel configuration parameters include the input format corresponding to the test function of each timing control board. The signal generator loads the test parameters according to the channels corresponding to the first and second output interfaces, generating test image signals corresponding to the input formats of the standard board and the DUT, respectively. For example, the signal generator generates a test image signal A conforming to the input format of the channel configuration parameters corresponding to test channel A and sends it to timing control board A. The standard board and the DUT process their respective test image signals to generate corresponding screen drive signals. Regardless of whether it's the DUT or the standard board, the timing control board processes the received test image signal to generate a screen drive signal conforming to its output format. The standard board outputs a standard screen drive signal based on its own function, and the DUT outputs a screen drive signal based on its own function. The comparison engine acquires the standard screen drive signal and the screen under test drive signal through the first input interface and the second input interface, respectively, and performs a consistency comparison between the standard screen drive signal and the screen under test drive signal to determine whether the board under test is qualified.

[0022] It should be noted that the host computer includes testing software. Users can select various test channels through the software's interface and configure corresponding test parameters for each channel, such as configuring test items and selecting test image materials. The test items correspond to the functions of the board under test (BUT). The testing software stores the test parameters, thereby determining the timing control board corresponding to each test channel. In essence, the test parameters include test image materials and channel configuration parameters. Channel configuration parameters include the input format corresponding to the test item functions of each timing control board. For example, users can select the input format corresponding to multiple timing control boards, choosing from several pre-stored formats in the testing software, such as LVDS. Users can configure the specific output interface uniquely corresponding to the signal source in the test software according to the input format of the timing control board at a specific workstation. The specific workstation and the corresponding specific output interface are in the same test channel. The workstations include test workstations and standard workstations. The test workstation is the position of the board under test during testing, and the standard workstation is the position of the standard board during testing. Each workstation corresponds to a single timing control board for a single test. If a single timing control board supports two output formats, then the two functional tests corresponding to these two output formats are defined as a single test.

[0023] In this embodiment, the input format supported by the timing control board is configured in the host computer. The standard board and the board under test have the same function, and the data output by the same output interface of the two timing control boards is the same. Therefore, the consistency of the output data can be directly compared. There is no need to simulate the format conversion function of the board under test, nor is it necessary to configure the output format of the timing control board in the host computer, which can simplify the test operation.

[0024] Furthermore, the comparison engine includes a comparison unit, which comprises a first input interface and a second input interface. The comparison unit is the specific execution unit for comparing the standard board and the board under test (DUT). Each comparison unit can compare the data consistency between a specific DUT and its corresponding standard board. When there is only one DUT, there can also be only one comparison unit. The comparison unit determines whether the DUT's drive signal is valid, i.e., whether the corresponding test item has passed, or whether the DUT is qualified, by judging whether the deviation of the acquired DUT drive signal relative to the acquired standard drive signal is within the allowable deviation range. The screen drive signal is the output data of the timing control board, and the standard screen drive signal serves as the reference signal for the DUT's drive signal.

[0025] The embodiments of this application are not limited to testing a single board under test. When the signal generator is connected to multiple timing control boards under test, multiple timing control boards under test can be tested simultaneously, thereby improving testing efficiency.

[0026] In some embodiments, the signal generator includes at least two sets of output interfaces. For example... Figure 2 As shown, taking a signal generator with two sets of output interfaces as an example, each set of output interfaces includes a first output interface and a second output interface. The first output interface and the second output interface are used to connect a standard timing control board and a timing control board under test, respectively. Among them, the standard timing control board 1 and the timing control board under test 1 have the same specifications and are in the same group of timing control boards. The standard timing control board corresponding to the timing control board under test 2 is the standard timing control board 2.

[0027] In the same set of output interfaces, the first output interface and the second output interface have the same interface format, which means that the input format of the two timing control boards is the same. When the specifications of the two timing control boards are the same, the output format of the two timing control boards is naturally the same. Based on this, by matching the board under test with a qualified standard board, the board under test can be determined to be qualified by using the standard board.

[0028] It should be noted that two test image signals output from the same set of output interfaces are the same set of test image signals. Similarly, the same set of test images are processed by the board under test and the corresponding standard board and converted into the same set of screen drive signals.

[0029] Furthermore, different groups of output interfaces support timing control boards of the same and / or different specifications. Within different groups of output interfaces, the interface formats between any two first output interfaces can be the same or different. If they are the same, it indicates that the signal generator supports test boards with the same input format. Specifically, when the specifications of the two test boards are the same, it indicates that the signal generator supports testing multiple timing control boards of the same specification; when the specifications of the two test boards are different, it indicates that the signal generator supports testing timing control boards of different specifications. If they are different, it indicates that the signal generator can support test boards of different specifications and can simultaneously test different types of test boards. In other words, different groups of output interfaces of the signal generator support timing control boards of the same and / or different specifications, meaning the signal generator supports multiple or various timing control boards. This embodiment supports simultaneous testing of multiple timing control boards and is also compatible with simultaneous testing of multiple types of timing control boards, improving the scalability of timing control boards.

[0030] like Figure 3 As shown, the comparison engine further includes two comparison units, such as comparison unit 1 and comparison unit 2. Comparison unit 1 is connected to the output terminals of the timing control board under test 1 and the standard timing control board 1, and comparison unit 2 is connected to the output terminals of the timing control board under test 2 and the standard timing control board 2. It can be seen that each comparison unit corresponds one-to-one with the test channel of each board under test and also one-to-one with the test channel of each standard board. For example, comparison unit 1 is connected to both standard board 1 and board under test 1 to determine the consistency of the output data of standard board 1 and board under test 1. Each comparison unit can be configured to acquire the drive signal of the screen under test and the standard screen drive signal in the corresponding group of screen drive signals, and compare the consistency between the drive signal of the screen under test and the standard screen drive signal. Considering that the comparison engine processes multiple groups of screen drive signals, multiple comparison units can be designed in the comparison engine. The two output terminals of each comparison unit correspond to the first output interface and the second output interface in the same group, thus ensuring that each comparison unit can process the corresponding group of screen drive signals and simultaneously execute multiple comparison tasks.

[0031] When the number of boards under test (DUTs) being tested simultaneously is small, for example, a single image signal generator can connect all standard boards and DUTs at the same time. Optionally, the signal source is an image signal generator, which includes a first output interface and a second output interface. Both output interfaces are on a single image signal generator, eliminating the need to increase the number of image signal generators and avoiding increased costs.

[0032] Obviously, the screenless testing system of this embodiment has multiple test channels, and each test channel is one of multiple parallel test branches. For example, on the test channels of the board under test and the standard board, the signal generator generates a first test image signal A and a second test image signal A that match the format of the first output interface A and the second output interface A, respectively. The first test image signal A and the second test image signal A are sent to the standard board A and the board under test A, respectively, via the first output interface A and the second output interface A, respectively. The standard board A and the board under test A process the first test image signal A and the second test image signal A, respectively, and generate a standard screen driving signal A and a screen under test driving signal A, respectively. The standard screen driving signal A and the screen under test driving signal A are transmitted to the same comparison unit A via the first input interface A and the second input interface A, respectively, so that the comparison unit A can perform data consistency comparison on the standard screen driving signal A and the screen under test driving signal A.

[0033] The embodiments of this application use a standard board as the test benchmark for the board under test, eliminating the need for an additional FPGA chip to simulate the input / output format conversion function of the board under test, thus reducing testing costs and simplifying the testing process.

[0034] like Figure 4 As shown, in some embodiments, the signal generation source includes a first image signal generator and a second image signal generator. The first image signal generator includes a first output interface, and the second image signal generator includes a second output interface. The input interfaces of each of the first and second image signal generators are connected to a host computer. The n1 first output interfaces of the first image signal generator can connect to at most n1 or n1 types of standard boards. The first image signal generator generates a first test image signal (input data of the standard board) according to a configured input format and inputs the first test image signal to a standard board that supports the input format through the first output interface for processing, so that the standard board outputs display drive data, i.e., screen drive signal, which can also be called the output data of the standard board. Correspondingly, the second image signal generator has n1 second output interfaces, supporting direct connection to at most n1 or n1 types of boards under test. The second image signal generator performs the same configuration processing as the first image signal generator, sending the generated second test image signal conforming to the input format of the test board to the board under test through the second output interface, so that the board under test outputs display drive data based on its own functions.

[0035] like Figure 5As shown, in some embodiments, a first expansion dock (one-to-many) is also included. The input end of the first expansion dock is connected to a second output interface, and each output end is used to connect to the input end of the corresponding timing control board under test. Each second output interface can also connect to multiple boards under test of the same type through the first expansion dock. Multiple boards under test of the same type connected to the same first expansion dock correspond to the same standard board. For example, boards under test 4-1, 4-2, and 4-3 all correspond to standard board 4. Board under test 4-1 and standard board 4 form one group, boards under test 4-2 and standard board 4 form another group, and boards under test 1 and standard board 1 form yet another group. The number of output interfaces of the image signal generator is limited. In order to test more boards under test, an expansion dock can be used to increase the number of boards under test being measured simultaneously, thereby meeting the requirements for high concurrency.

[0036] Furthermore, when a second output interface is used to connect the input terminals of at least two timing control boards under test via a first expansion dock, the comparison engine includes at least two second comparison units. Each second comparison unit includes a first input interface and a second input interface. Each first input interface is connected to the output terminal of the same standard timing control board, and each second input interface is used to connect to the output terminal of the corresponding timing control board under test. The second comparison unit is... Figure 5 The comparison engine comprises comparison units 4-1, 4-2, and 4-3. In this embodiment, the comparison engine includes comparison units 1, 2, 3, 4-1, 4-2, and 4-3. Each comparison unit is connected to a test board (TBD). Since the specifications of TBDs 4-1, 4-2, and 4-3 connected to the same second output interface are identical, a standard board 4 can be used as a reference for TBDs 4-1, 4-2, and 4-3. The specifications of TBDs 1, 2, 3, and 4-1 are not limited to being identical. If all are different, the system can support six TBDs of four different types.

[0037] like Figure 6As shown, further, it also includes a multi-to-one second expansion dock. Each input terminal of the second expansion dock is used to connect to the output terminal of the corresponding timing control board under test, and the output terminal is connected to the second input interface. When the test quantity of the board under test is expanded using the first expansion dock, and the second input interface of the comparison engine is insufficient, a multi-to-one second expansion dock can be used to connect all the output data of boards under test 4-1, 4-2, and 4-3 to the comparison unit 4 through the same second input interface. The comparison unit 4 then compares the output data of boards under test 4-1, 4-2, and 4-3. The output data of boards under test 4-1, 4-2, and 4-3 to the comparison engine carries the second output interface identifier and the expansion dock interface identifier, allowing the comparison engine to identify the output data of each board under test. However, the second expansion dock may cause congestion in the comparison unit 4, affecting the test results. For cases with expansion docks, the number of comparison units can be appropriately increased to match the testing of more boards under test and meet high concurrency requirements.

[0038] In some embodiments, the comparison engine is integrated into the host computer or signal generator; alternatively, the comparison engine is a standalone device, with its output connected to the host computer. The comparison engine, acting as a device for comparing the consistency of output data from the board under test (DUT), can be integrated into the host computer, the signal generator, or a standalone device parallel to the host computer. If the comparison engine is integrated into the host computer, the output data from each timing control board can be sent back to the host computer. The host computer identifies the same group of output data based on the serial number and device serial code, performs a consistency comparison of the same group of output data, and records the test results for each DUT. If the comparison engine is a standalone device, its input pins are connected to the outputs of each timing control board to obtain the output data from the standard board and the DUT within the same group, performing a consistency comparison of the same group of output data. The comparison results can then be sent back to the host computer.

[0039] In some embodiments, a storage medium is also included for storing the screen drive signals generated by the standard timing control board. The storage medium is integrated into the comparison engine, the host computer, or the signal generator. In practice, the display drive data output by the standard board for the same input data is largely consistent, resulting in a low bit error rate. In extreme cases, the standard board only needs to perform one input / output format conversion signal processing operation. The output data of the standard board can be cached in the storage medium, which could be in the comparison engine, the host computer, or even the image generator. Therefore, once the comparison engine obtains the output data of the current board under test (i.e., the screen drive signal under test), it no longer needs to obtain the output data of the corresponding standard board. It only needs to retrieve the corresponding standard screen drive signal from the storage medium to perform a consistency comparison of the output data of the current board under test, thereby determining whether the current board under test is qualified.

[0040] Furthermore, after the first signal processing on the standard board, the standard screen drive signal is stored as a reference signal, and the standard board does not need to perform further signal processing, so the first output interface can be left idle. Once the output data of the standard board has been stored and fixed, the corresponding first output interface can be released, its nature changed to a second output interface, and it can be connected to the board under test, thereby increasing the number of parallel tests.

[0041] If the first output interface is always connected to the standard board, the host computer does not need to release the first output interface. The standard board can repeatedly perform format conversion processing and store and back up the output data of each processing. The comparison engine can then perform a consistency comparison on the current output data of the same group under test. Based on this, it will also perform a consistency comparison on the current output data of the board under test with the historical output data of the corresponding standard board. The comparison result when the two types of comparison results of the current output data of the board under test are consistent is used as the basis for determining whether the board under test is qualified. If the two types of comparison results of the current output data of the board under test are inconsistent, it can be determined that the standard board has an anomaly during the current test, thus preventing a single erroneous output from the standard board from affecting the test results of the board under test and improving test accuracy.

[0042] However, when the number of boards under test exceeds the number of comparator units, the current operating mode of the comparator unit cannot process the outputs of all boards under test, such as... Figure 7As shown. Preferably, the comparison engine includes a comparison task scheduling module and multiple comparison units, each with only one input, and all comparison units are connected to the comparison task scheduling module. A comparison task scheduling module is set between the comparison units and the output of the timing control board. The comparison task scheduling module allocates all acquired screen group drive signals to the comparison units, not limiting specific comparison units to process specific screen group drive signals, thereby meeting the needs of larger-scale testing. The comparison task scheduling module can monitor the idle state of each comparison unit and receive the output data of each timing control board. It packages the output data of the standard board and the board under test in the same group and sends them to the idle comparison units for comparison, thereby enabling fewer comparison units to perform orderly testing of more boards under test, thus improving testing efficiency.

[0043] The embodiments of this application can support simultaneous testing of multiple boards under test and are compatible with multiple types of boards under test, thereby improving testing efficiency. By using a standard board to replace the FPGA chip that converts the input and output formats of the simulated board under test, there is no need to configure a separate FPGA chip to simulate the board under test, thus reducing the cost of the testing system.

[0044] This application also provides a screenless testing system based on timing control boards, including a host computer, a signal generator, a comparison engine, and at least one set of timing control boards. Each set of timing control boards includes a standard timing control board and at least one timing control board under test. The standard timing control board is a qualified timing control board and has the same specifications as each timing control board under test. The host computer is connected to the input terminal of the signal generator. The signal generator includes at least one set of output interfaces, each set of output interfaces including two output interfaces. The first output interface is connected to the input terminal of the standard timing control board, and the second output interface is connected to the input terminal of each timing control board under test. The comparison engine includes at least one set of input interfaces, each set of input interfaces including a first input interface and at least one second input interface. The first input interface is connected to the output terminal of the standard timing control board, and the second input interface is connected to the output terminal of each timing control board under test.

[0045] It should be noted that the screenless testing system provided in this application embodiment differs from the aforementioned system embodiment in that it also includes a test board, representing two states of the screenless testing system with and without a test board. The specific embodiments of this are described in detail in the aforementioned system embodiment and will not be repeated here.

[0046] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A screenless testing system based on a timing control board, characterized in that, It includes a host computer, a signal generator, a comparison engine, and at least one standard timing control board, wherein the standard timing control board is a qualified timing control board; The host computer is connected to the input terminal of the signal generator; The signal generator includes at least one set of output interfaces. Each set of output interfaces includes two output interfaces of the same specifications. The first output interface is connected to the input terminal of the standard timing control board, and the second output interface is used to connect to the input terminal of at least one timing control board under test with the same specifications as the standard timing control board. The comparison engine includes at least one set of input interfaces. Each set of input interfaces includes a first input interface and at least one second input interface. The first input interface is connected to the output terminal of the standard timing control board, and each second input interface is used to connect to the output terminal of the corresponding timing control board under test.

2. The screenless testing system based on a timing control board according to claim 1, characterized in that, The signal generator includes at least two sets of output interfaces.

3. The screenless testing system based on a timing control board according to claim 2, characterized in that, Different output interfaces support timing control boards of the same and / or different specifications.

4. The screenless testing system based on a timing control board according to claim 1 or 2, characterized in that, The signal generation source includes a first image signal generator and a second image signal generator, wherein the first image signal generator includes the first output interface, and the second image signal generator includes the second output interface; or... The signal source is an image signal generator, which includes the first output interface and the second output interface.

5. The screenless testing system based on a timing control board according to claim 1, characterized in that, The comparison engine includes at least one comparison unit, which includes a first input interface and a second input interface.

6. The screenless testing system based on a timing control board according to claim 1, characterized in that, It also includes a first expansion dock with one-to-many conversion, the input end of the first expansion dock is connected to the second output interface, and each output end is used to connect to the input end of the corresponding timing control board under test.

7. The screenless testing system based on a timing control board according to claim 6, characterized in that, When a second output interface is used to connect the input terminals of at least two timing control boards under test via the first expansion dock, the comparison engine includes at least two second comparison units. Each second comparison unit includes a first input interface and a second input interface. Each first input interface is connected to the output terminal of the same standard timing control board, and each second input interface is used to connect to the output terminal of the corresponding timing control board under test.

8. The screenless testing system based on a timing control board according to claim 1, characterized in that, The comparison engine is integrated into the host computer or the signal generator; or... The comparison engine is an independent device, and its output is connected to the host computer.

9. The screenless testing system based on a timing control board according to claim 8, characterized in that, It also includes a storage medium for storing screen drive signals generated by the standard timing control board.

10. A screenless testing system based on a timing control board, characterized in that, It includes a host computer, a signal generator, a comparison engine, and at least one set of timing control boards; each set of timing control boards includes a standard timing control board and at least one timing control board under test, wherein the standard timing control board is a qualified timing control board and has the same specifications as each timing control board under test; The host computer is connected to the input terminal of the signal generator; The signal generator includes at least one set of output interfaces, each set of output interfaces includes two output interfaces, the first output interface is connected to the input terminal of the standard timing control board, and the second output interface is connected to the input terminal of each timing control board under test respectively. The comparison engine includes at least one set of input interfaces. Each set of input interfaces includes a first input interface and at least one second input interface. The first input interface is connected to the output terminal of the standard timing control board, and the second input interface is connected to the output terminal of each timing control board under test.

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