High bandwidth flash memory devices and storage systems

Abstract

The utility model discloses a high bandwidth's flash memory device and storage system, this high bandwidth's flash memory device, including logic chip and with the logic chip stacked setting's flash memory chip, the flash memory chip includes a plurality of flash memory array, a plurality of flash memory array respectively with logic chip communication connection, logic chip synchronous control a plurality of flash memory array carries out parallel data read-write operation. Through integrating a plurality of flash memory array in single flash memory chip, and adopting the architecture that logic chip and flash memory chip stacked setting, realized a plurality of flash memory array and the direct communication connection of logic chip, make logic chip can synchronous control a plurality of flash memory array carries out parallel data read-write operation, to improve data transmission bandwidth and overall storage performance.

Description

Technical Field

[0001] This utility model relates to the field of storage technology, and in particular to a high-bandwidth flash memory device and storage system. Background Technology

[0002] With the rapid development of artificial intelligence technology, especially the widespread deployment of large-scale model applications, unprecedented challenges have been posed to the data transfer rates of storage systems. Traditional flash memory storage technology has gradually revealed its insufficient bandwidth when facing the computing power demands of AI, urgently requiring new technological breakthroughs to meet the high-speed data transfer requirements at the TB / s level. Against this backdrop, high-bandwidth flash memory (HBF) chip technology has emerged as a key technological direction for solving the storage bottleneck of large AI models.

[0003] Currently, flash memory chips in the industry generally adopt the ONFI (Open NAND Flash Interface) protocol, with a transmission rate of approximately 3Gb / s. Existing mainstream storage products such as eMMC, UFS, and SSD all employ similar design architectures, namely a package structure consisting of one controller chip and 1 to 16 stacked flash memory chips. In this architecture, the controller chip is responsible for converting the ONFI interface of the flash memory chips into the user-facing eMMC, UFS, or SSD standard interface. This design performs well in meeting the needs of ordinary applications and is generally capable of handling routine data access tasks.

[0004] However, existing technical architectures have significant shortcomings when facing high-performance computing applications such as large AI models. In traditional architectures, a single chip contains only one flash memory array, while other functional modules occupy most of the chip's area. This design results in poor storage density and bandwidth utilization, ultimately leading to a severe lack of data throughput, which cannot meet the urgent demand for high-speed data transmission in AI computing power. Utility Model Content

[0005] The main objective of this invention is to propose a high-bandwidth flash memory device, which aims to solve the problem of low bandwidth utilization in existing technology architectures.

[0006] To achieve the above objectives, this utility model proposes a high-bandwidth flash memory device, which includes a logic chip and flash memory chips stacked with the logic chip. The flash memory chips include multiple flash memory arrays, which are respectively communicatively connected to the logic chip. The logic chip synchronously controls the multiple flash memory arrays to perform parallel data read and write operations.

[0007] In this embodiment, multiple flash memory chips are stacked on top of the logic chip.

[0008] In this embodiment, the flash memory chip and the logic chip are packaged in TSV.

[0009] In this embodiment, the flash memory chip further includes: A high-voltage analog circuit, used to generate a working voltage; A high-voltage controller is provided, and there are multiple high-voltage controllers, each corresponding to one of the multiple flash memory arrays. Each high-voltage controller is used to control the operating voltage of the corresponding flash memory array.

[0010] In this embodiment, the flash memory chip further includes a decoder; the logic chip includes a flash data processor and an ECC scheduler, the ECC scheduler being electrically connected to the decoder and the flash data processor respectively.

[0011] In this embodiment, the logic chip further includes a low-voltage sensor, which is electrically connected to the flash memory data processor and the plurality of high-voltage controllers respectively. The low-voltage sensor acquires and feeds back the operating voltage parameters of the plurality of flash memory arrays to the flash memory data processor.

[0012] In this embodiment, the logic chip further includes a data exchange module that is communicatively connected to the flash memory data processor. The data exchange module interacts with the ECC scheduler through the flash memory data processor.

[0013] In this embodiment, the logic chip further includes a flash memory state manager, which is electrically connected to the flash memory data processor, the high voltage controller, and the low voltage sensor, respectively. The flash memory state manager is used to control the state transitions and timing management of the multiple flash memory arrays.

[0014] In this embodiment, the logic chip further includes an address mapping controller, which is electrically connected to the flash memory data processor.

[0015] This invention further proposes a storage system including the high-bandwidth flash memory device of the aforementioned embodiments.

[0016] The beneficial effects of this utility model's technical solution are as follows: By integrating multiple flash memory arrays within a single flash memory chip and adopting an architecture that stacks logic chips and flash memory chips, direct communication connections between multiple flash memory arrays and the logic chip are achieved. This allows the logic chip to synchronously control multiple flash memory arrays to perform parallel data read and write operations, thereby significantly improving data transmission bandwidth and overall storage performance. Compared to the traditional architecture where a single chip contains only one flash memory array, this technical solution effectively solves the problems of insufficient data throughput, poor storage density, and poor bandwidth utilization in existing technologies through the parallel operation of multiple arrays. It can meet the high-performance computing application requirements of TB / s-level high-speed data transmission, such as large AI models. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of an embodiment of the high-bandwidth flash memory device of the present invention; Figure 2 This is a schematic diagram of the structure of an embodiment of the high-bandwidth flash memory device of this utility model.

[0018] Explanation of icon numbers: 10. High-bandwidth flash memory devices; 100. Logic chip; 101. Flash memory data processor; 102. ECC scheduler; 103. Low voltage sensor; 104. Data exchange module; 105. Flash memory status manager; 106. Address mapping controller; 200. Flash memory chip; 201. Multiple flash memory arrays; 202. High voltage analog circuit; 203. High voltage controller; 204. Decoder.

[0019] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0021] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0022] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0023] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0024] The high-bandwidth flash memory (HBF) device in this embodiment is mainly applied to the field of AI computing power support. Existing flash memory devices typically include multiple flash memory chips and corresponding main control chips. Each flash memory chip integrates only a single flash memory array, with the majority of the remaining area occupied by peripheral circuits such as high-voltage control circuits, low-voltage sensing circuits, logic control circuits, ECC error correction modules, low-voltage analog circuits, high-voltage analog circuits, decoders, and ONFI interfaces. This architecture results in a relatively small proportion of the flash memory array within the entire chip, and some functional modules are redundantly configured with the main control chip, leading to resource redundancy. Furthermore, the bandwidth limitations and low storage density utilization of traditional architectures ultimately result in insufficient data throughput, failing to meet the urgent need for high-speed data transmission in AI large-scale model training and inference. Therefore, this embodiment proposes a high-bandwidth flash memory device that integrates multiple flash memory arrays within a single flash memory chip and employs an innovative architecture of stacked logic chips and flash memory chips. This enables direct communication between multiple flash memory arrays and the logic chip, allowing the logic chip to synchronously control multiple flash memory arrays for parallel data read and write operations. See details... Figure 1 and Figure 2 This utility model embodiment proposes a high-bandwidth flash memory device, including a logic chip 100 and a flash memory chip 200 stacked with the logic chip 100. The flash memory chip 200 includes multiple flash memory arrays 201, which are respectively communicatively connected to the logic chip 100. The logic chip 100 synchronously controls the multiple flash memory arrays 201 to perform parallel data read and write operations.

[0025] In this embodiment, the high-bandwidth flash memory device (HBF) is a novel storage solution specifically designed for AI computing needs, with its core being to overcome the bandwidth bottleneck of traditional flash memory architecture. The logic chip 100, as the control core of the entire device, undertakes key functions such as data scheduling, parallel control, error correction, and interface management. It is essentially an upgraded version of the main control chip in a traditional architecture, but achieves a tighter physical and electrical connection with the flash memory chip 200 through 3D stacking technology.

[0026] Specifically, the flash memory chip 200 integrates multiple flash memory arrays 201, which can be two, four, eight, or more. Each flash memory array is an independent storage unit with autonomous read and write capabilities. These flash memory arrays can use the same NAND Flash technology (such as 3D NAND), or they can use a combination of different types of flash memory technologies depending on the application requirements. For example, some may use high-speed SLC (single-level storage cell) for caching hot data, while others may use high-density QLC (four-level storage cell) for large-capacity storage.

[0027] The communication connection between logic chip 100 and flash memory chip 200 is achieved through through-silicon via (TSV) technology or micro bump technology, forming a high-density interconnect channel. This connection method offers lower latency, higher bandwidth, and better signal integrity compared to traditional package-level interconnects. Logic chip 100 can be manufactured using advanced process technologies (such as 7nm or 5nm) to achieve stronger computing power and lower power consumption, while flash memory chip 200 uses a process node suitable for memory manufacturing.

[0028] By incorporating multiple flash memory arrays 201 within a single flash memory chip 200, this embodiment demonstrates superior parallel data processing capabilities in AI model computing applications. During the training or inference of large AI models, when the system needs to load a large amount of model parameters, weight data, or process batch input data, the logic chip 100 can intelligently decompose the data request into multiple parallel tasks and simultaneously issue read and write commands to multiple flash memory arrays 201.

[0029] The specific working process is as follows: First, the logic chip 100 receives data access requests from the AI ​​processor and maps the requests to different flash memory arrays according to the logical address and access mode of the data. Second, through the built-in scheduling algorithm, the logic chip 100 ensures load balancing among the flash memory arrays to avoid any array becoming a performance bottleneck. Then, multiple flash memory arrays 201 perform read and write operations simultaneously, with each array independently processing the data blocks allocated to it. Finally, the logic chip 100 merges and sorts the data returned by each array and returns it to the AI ​​processor in the format of the original request.

[0030] This parallel processing mechanism enables a multiple increase in data transmission bandwidth. For example, if the bandwidth of a single flash array is 1GB / s, then an HBF device integrating eight arrays can theoretically achieve a bandwidth of 8GB / s. More importantly, this architecture is particularly suitable for scenarios in AI computing that require massive parallel data access, such as matrix operations and convolution operations, effectively reducing the waiting time of AI processors and improving overall computing power utilization. When processing large-scale language models or computer vision models, multiple flash arrays 201 can simultaneously provide model parameters at different levels, achieving true parallel data supply.

[0031] The beneficial effects of this utility model's technical solution are as follows: By integrating multiple flash memory arrays 201 within a single flash memory chip 200 and adopting an architecture where the logic chip 100 and the flash memory chip 200 are stacked, direct communication connections between the multiple flash memory arrays 201 and the logic chip 100 are achieved. This allows the logic chip 100 to synchronously control the multiple flash memory arrays 201 to perform parallel data read and write operations, thereby significantly improving data transmission bandwidth and overall storage performance. Compared to the traditional architecture where a single chip contains only one flash memory array, this technical solution effectively solves the problems of insufficient data throughput, poor storage density, and poor bandwidth utilization in existing technologies by using a multi-array parallel operation method. It can meet the high-speed data transmission requirements of TB / s level for high-performance computing applications such as large AI models.

[0032] The stacked architecture design significantly shortens the data transmission path, reduces signal latency and power loss. Compared with the traditional discrete architecture, data access latency can be reduced by 30-50%, and overall power efficiency can be improved by 20-40%.

[0033] Furthermore, the parallel operation mode of multiple flash arrays provides better reliability and redundancy protection. When one flash array fails, the system can dynamically adjust the load distribution and utilize the remaining normal arrays to continue working, ensuring high system availability.

[0034] Finally, this technical solution achieves higher storage density within the same package size by optimizing chip area utilization, providing strong support for the miniaturization and integration of AI computing devices. It is particularly suitable for space-sensitive application scenarios such as edge AI devices, autonomous vehicle systems, and smartphones.

[0035] Continue reading Figure 2 In this embodiment, multiple flash memory chips 200 are stacked on top of the logic chip 100.

[0036] This embodiment further extends the aforementioned technical solution by integrating multiple flash memory arrays 201 within a single flash memory chip 200, and by using vertical stacking technology to place multiple flash memory chips 200 above the logic chip 100, forming a multi-level storage architecture. Specifically, the logic chip 100 serves as the underlying control core, with two, four, eight, or more layers of flash memory chips 200 stacked sequentially above it, and each flash memory chip 200 containing multiple independent flash memory arrays.

[0037] This multi-layer stacking design enables a significant increase in storage capacity and processing power. For example, if a single flash memory chip 200 contains eight flash memory arrays, and four layers of flash memory chips 200 are stacked, the entire device contains a total of 32 flash memory arrays. The logic chip 100 establishes electrical connections with each layer of flash memory chips 200 through three-dimensional through-silicon via (3D TSV) technology, enabling simultaneous control of all flash memory arrays at all levels to perform parallel data read and write operations.

[0038] In practical applications of large-scale AI models, this multi-layer, multi-array architecture provides extremely high data parallelism. When the AI ​​processor needs to access large-scale parameter matrices or process batches of data, the logic chip 100 can intelligently allocate data requests to different flash memory arrays at different levels, achieving true three-dimensional parallel processing. The stacked configuration of multiple flash memory chips 200 not only significantly improves storage density but also increases the number of parallel channels, enabling the overall data throughput to reach tens of times that of traditional single-chip architectures. This meets the stringent requirements of large-scale AI models such as GPT and BERT for rapid access to massive amounts of data.

[0039] Furthermore, the multi-layer stacked architecture provides flexible storage hierarchical management capabilities. Logic chip 100 can store hot data in the flash memory chip 200 closer to the bottom layer for faster access speeds, and store cold data in the upper-layer chip for high-density storage, thereby optimizing overall power consumption and cost while ensuring high performance.

[0040] See Figure 1 and Figure 2 In this embodiment, the flash memory chip 200 and the logic chip 100 are packaged using TSV (Through Silicon Via). This embodiment employs Through Silicon Via (TSV) packaging technology to achieve the electrical connection between the flash memory chip 200 and the logic chip 100. TSV technology is a three-dimensional packaging process that forms vertical interconnect channels by drilling holes in a silicon wafer and filling them with conductive material (such as copper), enabling direct electrical communication between chips.

[0041] In this technical solution, TSV structures are fabricated on the contact surfaces of the logic chip 100 and the flash memory chip 200. When the two chips are stacked, the corresponding TSV holes are precisely aligned and reliably connected through processes such as thermoforming. The diameter of each TSV channel can be between 5 and 50 micrometers, and the spacing can be less than 20 micrometers, thereby achieving high-density signal interconnection within a limited chip area.

[0042] TSV connection paths are extremely short. Compared with traditional wire bonding or flip chip packaging, the signal transmission distance can be shortened from the millimeter level to the micrometer level, which greatly reduces signal delay and transmission loss, thereby improving the communication speed between the logic chip 100 and the flash memory array. Secondly, TSV technology provides higher interconnect density. The number of signal channels that can be accommodated per unit area is more than 10 times that of traditional packaging, providing sufficient bandwidth channels for the parallel control of multiple flash memory arrays 201.

[0043] See Figure 1 In this embodiment, the flash memory chip 200 further includes: High voltage analog circuit 202 is used to generate working voltage; High voltage controller 203, multiple high voltage controllers 203 are provided, and each high voltage controller 203 corresponds to a flash memory array 201. Each high voltage controller 203 is used to control the operating voltage of the corresponding flash memory array.

[0044] In this embodiment, the high-voltage analog circuit 202 and the corresponding high-voltage controller 203 are based on the physical working principle of flash memory. Flash memory cells employ a floating-gate transistor structure, requiring different high-voltage levels to perform data writing, erasing, and reading operations. In traditional architectures, multiple flash arrays 201 sharing a high-voltage circuit can easily lead to voltage interference and control conflicts, affecting the accuracy and parallel performance of data operations.

[0045] The high-voltage analog circuit 202, acting as a voltage generation module, incorporates a built-in charge pump circuit. It can boost externally supplied low voltages (e.g., 3.3V or 1.8V) to various operating voltages required for flash memory operation, including programming voltage (approximately 20V), erase voltage (approximately 20V), and read voltage (approximately 5V). This circuit can employ a multi-stage cascaded charge pump design to ensure output voltage stability and ripple control.

[0046] Each high-voltage controller 203 forms a one-to-one control relationship with its corresponding flash memory array. The core advantage of this design is that it enables independent voltage control. Each high-voltage controller 203 contains a voltage regulator, a timing controller, and protection circuitry, which can accurately adjust and output the required operating voltage according to the specific operational needs of the corresponding flash memory array.

[0047] In the actual operation, the logic chip 100 acts as the main controller, sending control commands and timing signals to each high-voltage controller 203. When a write operation is required on a flash memory array, the logic chip 100 instructs the corresponding high-voltage controller 203 to obtain the programming voltage from the high-voltage analog circuit 202 and precisely control the timing and amplitude of the voltage application. When reading data, the high-voltage controller 203 provides a relatively low read voltage to ensure the accuracy of data reading without affecting the data integrity of the storage unit. During the erase operation, the high-voltage controller 203 provides the erase voltage and strictly controls the erase timing.

[0048] Thus, the one-to-one high-voltage control architecture enables multiple flash arrays 201 to truly achieve independent parallel operation. Different arrays can perform different types of operations simultaneously (such as one array reading and another array writing), which greatly improves the parallelism and overall performance of data processing, making it suitable for AI computing applications that require frequent large-scale parallel data reading and writing.

[0049] Continue reading Figure 1 In this embodiment, the flash memory chip 200 further includes a decoder 204; the logic chip 100 includes a flash memory data processor 101 and an ECC scheduler 102, with the ECC scheduler 102 electrically connected to the decoder 204 and the flash memory data processor 101 respectively.

[0050] In this embodiment, the ECC scheduler 102 (Error Correction Code Scheduler), as the core module of the logic chip 100, is responsible for the unified management and scheduling of error detection and correction functions of the entire high-bandwidth flash memory device. Since this technical solution adopts an architecture where multiple flash memory arrays 201 operate in parallel, traditional distributed ECC processing methods cannot meet the requirements of efficient parallel data processing; therefore, centralized ECC scheduling and management are necessary.

[0051] The ECC scheduler 102 operates based on a centralized error management strategy. When the flash data processor 101 reads data from multiple flash arrays 201 in parallel, this data is initially processed by the decoder 204 and then transmitted to the ECC scheduler 102. The ECC scheduler 102 incorporates high-performance error detection algorithms, such as BCH codes and LDPC codes, and can simultaneously process data streams from multiple flash arrays 201 (the ECC scheduler 102 can be configured with multiple corresponding flash arrays) and detect bit errors. For detectable correctable errors, the ECC scheduler 102 immediately executes the error correction algorithm and returns the corrected data to the flash data processor 101; for uncorrectable errors, the ECC scheduler 102 triggers a reread mechanism or initiates a backup data recovery process.

[0052] Thus, the accuracy of data read from the flash array is ensured through the ECC algorithm, which is crucial for the parameter accuracy requirements in AI computing. Secondly, scheduling is optimized. The ECC scheduler 102 can intelligently allocate ECC processing resources and prioritize error correction of critical data channels to ensure the data integrity of high-priority AI tasks. Finally, performance is balanced. Unified ECC scheduling avoids the performance bottleneck caused by uneven ECC processing capabilities of different arrays in traditional architectures.

[0053] In large-scale AI model applications, the ECC scheduler 102, decoder 204, and flash data processor 101 form a highly efficient data processing pipeline. Decoder 204 is responsible for address decoding and data format conversion, ECC scheduler 102 ensures data accuracy, and flash data processor 101 performs the final data integration and output. This architecture design ensures data reliability and system stability even in high-concurrency multi-array data read / write scenarios, meeting the stringent requirements of AI computing for data accuracy and reliability.

[0054] Continue reading Figure 1 In this embodiment, the logic chip 100 also includes a low-voltage sensor 103, which is electrically connected to the flash memory data processor 101 and multiple high-voltage controllers 203 respectively. The low-voltage sensor 103 acquires and feeds back the operating voltage parameters of the multiple flash memory arrays 201 to the flash memory data processor 101.

[0055] In this embodiment, the low-voltage sensor 103 serves as a voltage monitoring and feedback module, playing a crucial role in the reliable operation of the high-bandwidth flash memory device. Since multiple flash memory arrays 201 operate in parallel simultaneously, the operating voltage state of each array directly affects the accuracy of data reading and writing and the system stability; therefore, real-time monitoring and dynamic adjustment are necessary.

[0056] The primary function of the low-voltage sensor 103 is voltage monitoring and feedback control. This sensor incorporates a sophisticated voltage detection circuit, enabling it to acquire voltage signals from multiple high-voltage controllers 203 in real time, including the actual operating voltage values ​​of each flash memory array during read, write, and erase operations. Through a high-precision analog-to-digital converter (ADC), the low-voltage sensor 103 converts the analog voltage signals into digital signals and transmits these voltage parameter data to the flash memory data processor 101.

[0057] After receiving voltage parameter feedback, the flash memory data processor 101 can determine the operating status and health of each flash memory array based on the voltage condition. When the operating voltage of a certain array deviates from the normal range, the flash memory data processor 101 can adjust the operating strategy of that array in a timely manner, or notify the corresponding high-voltage controller 203 to perform voltage correction. This closed-loop feedback mechanism ensures that multiple flash memory arrays 201 always operate under optimal voltage conditions.

[0058] The AI ​​model requires extremely high parameter accuracy; any data errors caused by voltage fluctuations can affect model performance. Through real-time monitoring by the low-voltage sensor 103, the system can intervene in the early stages of voltage anomalies, preventing data corruption or loss. Simultaneously, voltage parameter feedback can be used for power consumption optimization and thermal management. The flash memory data processor 101 can dynamically adjust workload allocation based on the voltage status of each array, achieving more efficient energy management and more stable system operation.

[0059] See Figure 1 In this embodiment, the logic chip 100 also includes a data exchange module 104 that is communicatively connected to the flash memory data processor 101. The data exchange module 104 interacts with the ECC scheduler 102 through the flash memory data processor 101.

[0060] In this embodiment, the data exchange module 104, as the core communication hub of the logic chip 100, is responsible for the unified management and scheduling of data streams from multiple flash memory arrays 201, realizing efficient data routing and exchange functions. In the architecture of multiple arrays working in parallel, a large number of data streams need to be transmitted quickly and accurately between different modules. Traditional point-to-point connection methods cannot meet the requirements of high bandwidth and low latency data exchange.

[0061] The data exchange module 104 operates based on a high-speed data exchange network architecture. This module incorporates a multi-port high-speed switching matrix, capable of simultaneously processing parallel data streams from multiple flash memory arrays 201. After each flash memory array completes its data read operation, the data is first aggregated to the flash memory data processor 101 for initial integration and formatting, and then transmitted to the data exchange module 104 via a dedicated high-speed data bus. The data exchange module 104 dynamically routes the data to the appropriate processing unit based on the data's destination address and priority.

[0062] Specifically, the data exchange module 104 employs a packet switching operation. Incoming data is segmented into fixed-size data packets, each carrying a destination address and control information. The routing engine within the exchange module quickly determines the data forwarding path based on the packet header information. For data requiring ECC verification, the exchange module routes the data packet to the ECC scheduler 102; for data that has already undergone verification, it routes it directly to an external interface or other processing modules.

[0063] The data exchange module 104 also features flow control and congestion management. In high-load AI computing scenarios, different flash arrays may generate sudden surges in data flow. The exchange module, through its built-in cache queue and priority scheduling algorithm, ensures the priority transmission of critical data streams while preventing system performance degradation due to data congestion. The module also supports multiple data exchange protocols, adapting to the data transmission needs of different types of AI applications.

[0064] Through the unified scheduling of the data exchange module 104, the entire high-bandwidth flash memory device achieves true parallel data processing. Data from multiple flash memory arrays 201 can be efficiently aggregated, routed, and distributed, significantly improving data processing throughput and providing strong data transmission support for the rapid training and inference of large AI models.

[0065] See Figure 1 In this embodiment, the logic chip 100 also includes a flash memory state manager 105, which is electrically connected to the flash memory data processor 101, the high voltage controller 203 and the low voltage sensor 103 respectively. The flash memory state manager 105 is used to control the state transitions and timing management of multiple flash memory arrays 201.

[0066] In this embodiment, the flash memory state manager 105, as the core control module of the logic chip 100, is responsible for the unified management and coordination of the working states of multiple flash memory arrays 201, ensuring that each array can perform orderly and efficient state switching and timing synchronization in a complex parallel operation environment. Since flash memory has multiple working states such as read, write, erase, and standby, and the transition between different states requires strict timing control, traditional distributed state management methods are difficult to meet the needs of multi-array collaborative work.

[0067] The flash memory state manager 105 operates based on a centralized state machine control architecture. This manager incorporates a finite state machine (FSM) to track and manage the current state of each flash memory array in real time, including idle, read, program, erase, and check states. The state manager obtains operation instructions and task queue information for each array through communication with the flash memory data processor 101; monitors the voltage supply status of each array through connection with the high-voltage controller 203; and obtains real-time voltage feedback information from each array through interaction with the low-voltage sensor 103. All of this information is used to determine the timing and method of state transitions for each array.

[0068] In terms of state transition control, the flash state manager 105 employs an intelligent scheduling algorithm that dynamically optimizes the state switching order of each array based on the priority of AI computing tasks and data access patterns. For example, when an array completes a data read operation and prepares to enter standby mode, the state manager checks if there are other high-priority tasks that the array needs to execute immediately, thus avoiding unnecessary state switching overhead. Simultaneously, the manager can predictively control array states, proactively waking up arrays that are about to be accessed from standby to ready mode, reducing task execution waiting time.

[0069] In the timing management function, the flash state manager 105 maintains a precise global clock reference to ensure the timing synchronization of operations across multiple arrays. For example, when performing complex AI computing tasks that require multiple arrays to work together, the state manager can precisely control the start time, operation duration, and completion time of each array, achieving true parallel processing. The manager also has abnormal state detection and recovery capabilities. When an array experiences an abnormal state or timing error, it can promptly reset the state and correct the timing to ensure the stable operation of the entire system.

[0070] Through the unified control of the flash state manager 105, multiple flash arrays 201 can work in parallel in a highly coordinated state, maximizing the performance advantages of the multi-array architecture and providing reliable state management guarantees for efficient data processing of large AI models.

[0071] See Figure 1 In this embodiment, the logic chip 100 further includes an address mapping controller 106, which is electrically connected to the flash memory data processor 101.

[0072] In this embodiment, the address mapping controller 106 is responsible for managing and converting the address mapping relationships in the high-bandwidth flash memory device, realizing efficient conversion and allocation from logical addresses to physical addresses. Since this technical solution employs an architecture where multiple flash memory arrays 201 operate in parallel, traditional linear address mapping methods cannot fully leverage the parallel advantages of multiple arrays. Therefore, a dedicated address mapping control mechanism is needed to optimize data distribution and access efficiency.

[0073] The address mapping controller 106 operates based on dynamic address allocation and load balancing strategies. This controller can have a built-in address mapping algorithm that intelligently distributes address requests to different flash memory arrays. For example, it maintains a dynamic address mapping table, recording detailed information such as the physical flash memory array location, page address, and block address corresponding to each logical address block. When the flash data processor 101 receives a data access request, the address mapping controller 106 quickly queries the mapping table to determine the specific flash memory array and physical location of the target data.

[0074] Regarding address allocation strategies, the address mapping controller 106 can employ a combination of striping and interleaving. For large, continuous blocks of data, the address mapping controller 106 can distribute the data across multiple flash arrays 201 in fixed-size stripes, enabling parallel access across multiple arrays when reading large amounts of continuous data and significantly improving data transmission bandwidth. For small, random blocks of data, the address mapping controller 106 can use an interleaved allocation method, mapping adjacent logical addresses to different physical arrays to avoid hotspot concentration and access conflicts.

[0075] The address mapping controller 106 can also have dynamic remapping and wear leveling functions. During AI computing, some data may be accessed frequently. The controller can monitor the access frequency and wear level of each flash array in real time, dynamically adjust the address mapping relationship, and redistribute hot data to different arrays to achieve load balancing and lifespan optimization.

[0076] This utility model further proposes a storage system including the high-bandwidth flash memory device 10 of the foregoing embodiments. The specific structure of the high-bandwidth flash memory device 10 is as described in the above embodiments. Since this storage system uses all the technical solutions of all the above embodiments, it has at least all the technical effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0077] In this embodiment, the storage system, as the core storage solution of the AI ​​computing platform, integrates the aforementioned high-bandwidth flash memory device, forming a complete high-performance storage system. This storage system is suitable for application scenarios with extremely high storage performance requirements, such as large-scale AI model training, inference acceleration, and edge computing.

[0078] The storage system connects to AI processors, GPU clusters, or other computing units through standardized interfaces (such as PCIe, NVMe, CXL, etc.), providing TB / s-level data transfer capabilities for the entire AI computing platform. The high-bandwidth flash memory devices inside the system employ the aforementioned multi-array parallel architecture, TSV packaging technology, centralized ECC scheduling, intelligent state management, and other innovative technologies to ensure stable and reliable operation under high-concurrency data access scenarios.

[0079] In practical applications, this storage system can significantly improve the training efficiency and inference speed of AI models. When dealing with deep learning models with a large number of parameters, its ultra-high data throughput and low latency characteristics can effectively alleviate the I / O bottleneck problem of traditional storage systems, providing strong data support for AI computing.

[0080] The above description is only a part or preferred embodiment of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the content of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A high-bandwidth flash memory device, characterized in that, The system includes a logic chip and a flash memory chip stacked with the logic chip. The flash memory chip includes multiple flash memory arrays, each of which is communicatively connected to the logic chip. The logic chip synchronously controls the multiple flash memory arrays to perform parallel data read and write operations.

2. The high-bandwidth flash memory device according to claim 1, characterized in that, Multiple flash memory chips are stacked on top of the logic chip.

3. The high-bandwidth flash memory device according to claim 1 or 2, characterized in that, The flash memory chip and the logic chip are packaged in TSV.

4. The high-bandwidth flash memory device according to claim 2, characterized in that, The flash memory chip also includes: A high-voltage analog circuit, used to generate a working voltage; A high-voltage controller is provided, and there are multiple high-voltage controllers, each corresponding to one of the multiple flash memory arrays. Each high-voltage controller is used to control the operating voltage of the corresponding flash memory array.

5. The high-bandwidth flash memory device according to claim 4, characterized in that, The flash memory chip also includes a decoder; the logic chip includes a flash data processor and an ECC scheduler, the ECC scheduler being electrically connected to the decoder and the flash data processor respectively.

6. The high-bandwidth flash memory device according to claim 5, characterized in that, The logic chip also includes a low-voltage sensor, which is electrically connected to the flash memory data processor and multiple high-voltage controllers respectively. The low-voltage sensor acquires and feeds back the operating voltage parameters of the multiple flash memory arrays to the flash memory data processor.

7. The high-bandwidth flash memory device according to claim 5, characterized in that, The logic chip also includes a data exchange module that is communicatively connected to the flash memory data processor. The data exchange module interacts with the ECC scheduler through the flash memory data processor.

8. The high-bandwidth flash memory device according to claim 5, characterized in that, The logic chip also includes a flash memory state manager, which is electrically connected to the flash memory data processor, the high voltage controller, and the low voltage sensor, respectively. The flash memory state manager is used to control the state transitions and timing management of the multiple flash memory arrays.

9. The high-bandwidth flash memory device according to claim 5, characterized in that, The logic chip also includes an address mapping controller, which is electrically connected to the flash data processor and the data interface.

10. A storage system, characterized in that, Includes the high-bandwidth flash memory device as described in any one of claims 1 to 9.

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