High power soa epitaxial structure and chip

Abstract

The utility model relates to a kind of high-power SOA epitaxial structure and chip, the epitaxial structure sequentially includes substrate from bottom to top, N-InP buffer layer, multilayer alternately appearing InGaAsP high fold layer and N-InP buffer layer, N-InP layer, InGaAsP SCH layer, MQW layer, InGaAsP SCH layer, high-doped P-InP layer, InGaAs ohmic contact layer;In multilayer alternately appearing InGaAsP high fold layer and N-InP buffer layer, N-InP buffer layer is provided between the two InGaAsP high fold layers of adjacent layer.The high-power SOA chip of this patent is designed by epitaxial structure of low light field restriction factor, combined with BH waveguide structure, and saturation output power is significantly improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a high-power SOA epitaxial structure and chip. Background Technology

[0002] Semiconductor optical amplifiers (SOAs) are core devices in fields such as optical communication, lidar, and quantum computing, and their saturated output power (P) is crucial. sat (P) is a key performance indicator. High P sat SOA can significantly reduce the number of relay amplification nodes in optical systems, effectively reducing system complexity and cost, and has become an important path to break through the current performance bottleneck of optical systems.

[0003] The current mainstream high-power optimization strategies include: (1) increasing the volume of the active region to improve the carrier storage capacity; (2) adopting a multi-stage cascade structure to amplify and reduce the single-stage load in stages; (3) setting up a quantum dot active layer to achieve high differential gain and low transparent current density; (4) reducing the optical field confinement factor (Γ) to reduce the overlap between the optical field and the active region.

[0004] However, the above-mentioned high-power optimization strategies all have certain limitations: increasing the volume of the active region can easily lead to a decrease in response speed and difficulty in mode control; multi-level cascaded structures increase device complexity and coupling loss; quantum dot active layer fabrication is difficult and costly; reducing the optical field confinement factor (Γ) requires optimization of waveguide structure design.

[0005] In view of this, this utility model proposes a high-power SOA epitaxial structure and chip. Utility Model Content

[0006] The purpose of this invention is to provide a high-power SOA epitaxial structure and chip, which significantly improves saturated output power by designing an epitaxial structure with a low optical field confinement factor and combining it with a BH waveguide structure.

[0007] To achieve the above objectives, the technical solution of this utility model is as follows:

[0008] This invention proposes a high-power SOA epitaxial structure, which, from bottom to top, includes a substrate, an N-InP buffer layer, multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP layer, an InGaAsP SCH layer, an MQW layer, an InGaAsP SCH layer, a highly doped P-InP layer, and an InGaAs ohmic contact layer; among the multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP buffer layer is disposed between two adjacent InGaAsP high-fold layers.

[0009] Preferably, the thickness of the N-InP buffer layer located above the substrate is 0.8~1.2μm, the thickness of the two InGaAsP SCH layers is 70~110 nm, the thickness of the MQW layer is 40~60 nm, the thickness of the highly doped P-InP layer is 2~3μm, and the thickness of the InGaAs ohmic contact layer is 300~500 nm.

[0010] Preferably, the multiple alternating InGaAsP high-fold layers and N-InP buffer layers specifically include 6 InGaAsP high-fold layers and 5 N-InP buffer layers.

[0011] Preferably, the thickness of each of the five N-InP buffer layers ranges from 190 to 230 nm.

[0012] Preferably, the thickness of each of the six InGaAsP high-refractive-index layers ranges from 50 to 100 nm.

[0013] Preferably, the thickness of the N-InP layer is in the range of 450~550 nm.

[0014] Preferably, it also includes an InP protective layer located above the ohmic contact layer InGaAs.

[0015] Preferably, the thickness of the InP protective layer ranges from 10 to 30 nm.

[0016] This invention proposes a high-power SOA chip, which is based on any of the above-mentioned high-power SOA epitaxial structures and is implemented using a buried heterojunction structure.

[0017] Preferably, the ridge corrosion depth of the buried heterojunction structure is set to be such that the ridge corrosion extends from the upper surface of the epitaxial structure downwards to the second or third layer of the high-fold layer.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This invention uses a multi-layer high-fold epitaxial design to expand the optical field range; by designing an epitaxial structure with a low optical field confinement factor Γ, combined with a BH waveguide structure, the saturated output power is significantly improved. Attached Figure Description

[0020] Figure 1 This is an extensional structure with Γ=0.02 in one embodiment of the present invention;

[0021] Figure 2 This is an epitaxial structure with Γ=0.06 in one embodiment of the present invention;

[0022] Figure 3This is a process diagram illustrating the fabrication method of a high-power SOA chip in one embodiment of this utility model;

[0023] Figure 4 This is an FDTD simulation diagram of two epitaxial structures with low optical field confinement factors in one embodiment of this utility model;

[0024] Figure 5 These are SEM images of two epitaxial structures with low optical field confinement factors in one embodiment of this utility model;

[0025] Figure 6 This is a graph showing the magnified test and saturated output power test data in one embodiment of this utility model. Detailed Implementation

[0026] The following is in conjunction with the appendix Figure 1-6 The technical solution of this utility model will be described in detail below.

[0027] This invention proposes a high-power SOA epitaxial structure, which, from bottom to top, includes a substrate, an N-InP buffer layer, multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP layer, an InGaAsP SCH layer, an MQW layer, an InGaAsP SCH layer, a highly doped P-InP layer, and an InGaAs ohmic contact layer. Among the multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP buffer layer is disposed between two adjacent InGaAsP high-fold layers. In addition, it also includes an InP protective layer located above the InGaAs ohmic contact layer, which is removed first during chip fabrication.

[0028] This invention proposes a high-power SOA chip, which is based on the above-mentioned high-power SOA epitaxial structure and is implemented using a buried heterojunction structure.

[0029] refer to Figure 3 The chip fabrication process is as follows:

[0030] The surface InP of the epitaxial wafer is removed using HCl, followed by SiO2 deposition through a ridge waveguide mask, ridge waveguide photolithography, etching of the exposed SiO2, removal of the photoresist, and ridge etching. The ridge etching depth needs to be controlled to the second or third high-fold layer to avoid being too shallow or too deep. Then, the first BH (Browser-Head) mask is performed, followed by removal of the SiO2 mask to obtain the PNP structure. A second BH mask is then performed, followed by deposition of a 100-200 nm SiO2 mask, double-groove photolithography and double-groove etching, and finally removal of the mask. Then, a 300-400 nm growth is performed. After applying a SiO2 passivation layer, photolithography and etching are performed on the ridge waveguide opening and scribe lines to obtain the scribe lines and exposed ohmic contact layer. Next, photolithography is performed on the ID and pads, followed by thin gold deposition on the P-side. After the gold layer is removed, a relatively thin gold electrode and metal ID are obtained. Electroplating 1 is then performed to increase the gold layer thickness in areas other than the ID. Electroplating 2 is then performed to raise the pad area to prevent damage to the ridges. The substrate is then thinned, followed by N-side metal deposition to obtain the preliminary uncleaved chip array. Bar cleaving is then performed, antireflection coatings are deposited on both sides, preliminary LIV testing is conducted, and cleaving is performed to obtain the desired chip.

[0031] refer to Figure 1 and Figure 2 Below are examples of epitaxial structures with low optical field confinement factors of Γ=0.02 and Γ=0.06:

[0032] Γ=0.02: From bottom to top, the layers are: substrate, N-InP buffer layer (0.8~1.2μm), high-refractive-index InGaAsP layer (50~100 nm), N-InP buffer layer (190~230 nm), high-refractive-index InGaAsP layer (50~100 nm), N-InP buffer layer (190~230 nm), high-refractive-index InGaAsP layer (50~100 nm), N-InP buffer layer (190~230 nm), high-refractive-index InGaAsP layer (50~100 nm), N-InP buffer layer (190~230 nm), high-refractive-index InGaAsP layer (50~100 nm), N-InP layer (450~550 nm), InGaAsP layer. SCH layer (70~110nm), MQW layer (40~60 nm), InGaAsP SCH layer (70~110 nm), highly doped P-InP layer (2~3μm), ohmic contact layer InGaAs (300~500nm), and finally InP protective layer (10~30nm, which is removed first during chip fabrication).

[0033] Γ=0.06: From bottom to top, the layers are: substrate, N-InP buffer layer (0.8~1.2μm), high-refractive-index InGaAsP layer (50~100 nm), N-InP buffer layer (190~230nm), high-refractive-index InGaAsP layer (50~100 nm), N-InP layer (1450~1550nm), InGaAsP SCH layer (70~110 nm), MQW layer (40~60 nm), InGaAsP SCH layer (70~110 nm), highly doped P-InP layer (2~3μm), ohmic contact layer InGaAs (300~500nm), and finally InP protective layer (10~30nm, which is removed first during chip fabrication).

[0034] The optical path and steps for amplification power testing are as follows:

[0035] ;

[0036] Saturated output power test: Controlling the current and temperature, the injected optical power was increased from -30dBm. For every 1dB increase, output and gain data were obtained. These corresponded one-to-one; the output power corresponding to a 3dB decrease in gain was the saturated output power. Analysis showed that the saturated output power Psat = 15.9 dBm @ 500mA for Γ = 0.06 and Psat = 17.06 dBm @ 500mA for Γ = 0.02.

[0037] Output power test at different currents: By controlling the injected optical power and setting the injected current to 100~1200 mA, data is recorded at 100mA intervals to obtain the output power under different currents. Analysis shows that Γ=0.06 results in an output power of 227mW@1200mA; Γ=0.02 results in an output power of 270mW@1200mA.

[0038] Related test results are attached. Figure 4-6 .

[0039] The above are preferred embodiments of this utility model. Any changes made to the technical solution of this utility model that do not exceed the scope of the technical solution of this utility model shall be protected within the scope of this utility model.

Claims

1. A high-power SOA epitaxial structure, characterized in that, From bottom to top, the layers consist of a substrate, an N-InP buffer layer, multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP layer, an InGaAsP SCH layer, an MQW layer, an InGaAsP SCH layer, a highly doped P-InP layer, and an InGaAs ohmic contact layer. Among the multiple alternating InGaAsP high-fold layers and N-InP buffer layers, an N-InP buffer layer is disposed between two adjacent InGaAsP high-fold layers.

2. The high-power SOA epitaxial structure according to claim 1, characterized in that, The thickness of the N-InP buffer layer located above the substrate ranges from 0.8 to 1.2 μm, the thickness of the two InGaAsP SCH layers ranges from 70 to 110 nm, the thickness of the MQW layer ranges from 40 to 60 nm, the thickness of the highly doped P-InP layer ranges from 2 to 3 μm, and the thickness of the InGaAs ohmic contact layer ranges from 300 to 500 nm.

3. The high-power SOA epitaxial structure according to claim 1, characterized in that, The multiple alternating InGaAsP high-fold layers and N-InP buffer layers specifically include 6 InGaAsP high-fold layers and 5 N-InP buffer layers.

4. The high-power SOA epitaxial structure according to claim 3, characterized in that, The thickness of each of the five N-InP buffer layers ranges from 190 to 230 nm.

5. A high-power SOA epitaxial structure according to claim 3, characterized in that, The thickness of each of the six InGaAsP high-refractive-index layers ranges from 50 to 100 nm.

6. A high-power SOA epitaxial structure according to claim 3, characterized in that, The thickness of the N-InP layer ranges from 450 to 550 nm.

7. A high-power SOA epitaxial structure according to claim 1, characterized in that, It also includes an InP protective layer located above the ohmic contact layer InGaAs.

8. A high-power SOA epitaxial structure according to claim 7, characterized in that, The thickness of the InP protective layer ranges from 10 to 30 nm.

9. A high-power SOA chip, characterized in that, The chip is based on the high-power SOA epitaxial structure described in any one of claims 1-6 and is implemented using a buried heterojunction structure.

10. A high-power SOA chip according to claim 9, wherein the ridge etching depth of the buried heterojunction structure is set to be such that the ridge etching extends downward from the upper surface of the epitaxial structure to the second or third high-fold layer.

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