A multi-path controlled direct current power supply display system

Abstract

The utility model provides a kind of multi-path program-controlled DC power display system, comprising: control storage module, power module, communication control module and display module;Control storage module includes: main control processor unit, coprocessor unit, software storage unit and record storage unit;Communication control module includes: control platform, control platform communication unit and reset control unit;The communication end of main control processor unit is connected with the communication end of coprocessor unit;The reset end of main control processor unit is connected with the reset end of coprocessor unit;The data end of coprocessor unit is connected with the data end of software storage unit and the data end of record storage unit;Control platform is connected with main control processor by control platform communication unit;Power module is powered for each unit;Support remote control power state, can receive remote control instruction by control platform communication unit, realize remote operation to power supply.

Description

Technical Field

[0001] This utility model relates to the field of power supply equipment technology, specifically a multi-path controllable DC power supply display system. Background Technology

[0002] With the rapid development of science and technology, power supplies, as fundamental electronic instruments, play a vital role in various industries. To adapt to different applications and customer requirements, their functions are becoming more diversified and intelligent. Traditional power supplies mostly offer only a fixed voltage output, which has the disadvantage of being unable to manually change the output voltage, resulting in low output accuracy and stability. With the rapid development of science and technology, the requirements for power supply reliability, output accuracy, and stability are becoming increasingly stringent, making the research and improvement of power supply structures imperative. Programmable DC power supplies are ideal devices for providing bias and excitation to components or final products in automated testing environments. They are widely used in measurement and control systems, marine systems, industrial inspection and control, integrated circuit testing, PC motherboard testing, and other complex testing systems. During product development, production, and testing, there is an urgent need for products that can provide stable output and fast dynamic response, simplify power supply configuration, and shorten development cycles. Utility Model Content

[0003] This utility model aims to at least solve the technical problems existing in the prior art, and in particular, it innovatively proposes a multi-path controllable DC power supply display system.

[0004] To achieve the above-mentioned objectives of this utility model, this utility model provides a multi-path controlled DC power supply display system, comprising:

[0005] Control storage module, power supply module, communication control module, and display module;

[0006] The control storage module includes: a main control processor unit, a coprocessor unit, a software storage unit, and a record storage unit;

[0007] The communication control module includes: a control platform, a control platform communication unit, and a reset control unit;

[0008] The communication terminal of the main control processor unit is connected to the communication terminal of the coprocessor unit;

[0009] The reset terminal of the main control processor unit is connected to the reset terminal of the coprocessor unit;

[0010] The data terminal of the coprocessor unit is connected to the data terminal of the software storage unit and the data terminal of the record storage unit;

[0011] The control platform and the main control processor are connected through the control platform communication unit;

[0012] The voltage output terminal of the power module is connected to the voltage input terminals of the main control processor unit, coprocessor unit, software storage unit, and record storage unit;

[0013] The display module is connected to the display signal terminal of the main control processor to display the current operation interface;

[0014] In a preferred embodiment of this utility model, the main control processor unit includes: the main control processor MCU serial port 1 data transmitting terminal UART1_TX is connected to the first end of resistor R110, and the second end of resistor R110 is connected to the coprocessor U1A data receiving terminal GPIO0_C0_d;

[0015] The main control processor MCU serial port 1 data receiver UART1_RX is connected to the first end of resistor R111, and the second end of resistor R111 is connected to the coprocessor U1A data transmitter GPIO0_C1_d;

[0016] The main control processor MCU serial port 2 data transmitter UART2_TX is connected to the first end of resistor R141, and the second end of resistor R141 is connected to the coprocessor U1A data receiver GPIO0_A0_u;

[0017] The main control processor MCU serial port 2 data receiving terminal UART2_RX is connected to the first end of resistor R142, and the second end of resistor R142 is connected to the coprocessor U1A data transmitting terminal GPIO0_A2_u;

[0018] The main control processor MCU serial port 3 data transmitter UART3_TX is connected to the first end of resistor R143, and the second end of resistor R143 is connected to the coprocessor U1A data receiver GPIO0_B7_d.

[0019] The main control processor MCU serial port 3 data receiving terminal UART3_RX is connected to the first end of resistor R144, and the second end of resistor R144 is connected to the communication coprocessor U1A data transmitting terminal GPIO0_B6_d;

[0020] In a preferred embodiment of this utility model, the reset control unit includes: a reset chip U2 with a manual reset terminal. Connect the first terminal of capacitor C17 to the first terminal of resistor R3, and connect the second terminal of resistor R3 to the power supply VCC3V3_PMUIO;

[0021] The ground terminal GND of the reset chip U2 is connected to the second terminal of capacitor C17 and the first terminal of capacitor C18 and grounded.

[0022] Reset chip U2 reset output terminal Connect the first end of resistor R4, the first end of resistor R5, and the reset terminal NPOR of coprocessor U1A. Connect the second end of resistor R4 to the power supply VCC3V3_PMUIO.

[0023] The second end of resistor R5 is connected to the digital signal terminal GPIO0_C5_Z of coprocessor U1A;

[0024] The power supply terminal VCC of the reset chip U2 is connected to the second terminal of capacitor C18 and the power supply VCC3V3_PMUIO;

[0025] In a preferred embodiment of this utility model, the coprocessor unit includes: the oscillator output terminal OSC_XOUT of the coprocessor U1A is connected to the first terminal of resistor R1 and the first terminal of resistor R2;

[0026] The oscillator input terminal OSC_XIN of the coprocessor U1A is connected to the second terminal of resistor R2, the first terminal of capacitor C15, and the crystal output terminal X1 of crystal oscillator Y1;

[0027] The second terminal of capacitor C15 is grounded, and the second terminal of resistor R1 is connected to the first terminal of capacitor C16 and the crystal input terminal X2 of crystal oscillator Y1.

[0028] The second terminal of capacitor C16 is grounded, and the ground terminal GND of crystal oscillator Y1 is grounded.

[0029] The power supply terminal ASYS_PLL_AVDD1V8 of the coprocessor U1A is connected to the power supply VCC_1V8 and the first terminal of capacitor C19, and the second terminal of capacitor C19 is grounded.

[0030] The reset signal terminal NPOR of the coprocessor U1A is connected to the first terminal of capacitor C10, and the second terminal of capacitor C10 is grounded.

[0031] In a preferred embodiment of this invention, the software storage unit includes: the coprocessor U1C digital signal terminal GPIO2_A0_u connected to the SPI Flash chip U3 chip select signal.

[0032] The digital signal terminal GPIO2_A1_d of the coprocessor U1C is connected to the first end of resistor R12, and the second end of resistor R12 is connected to the clock signal terminal C of the SPI Flash chip U3.

[0033] The coprocessor U1C's digital signal terminal GPIO2_A2_u is connected to the SPI Flash chip U3's data communication terminal DQ0;

[0034] The coprocessor U1C's digital signal terminal GPIO2_A3_u is connected to the SPI Flash chip U3's data communication terminal DQ1;

[0035] The coprocessor U1C's digital signal terminal GPIO2_A4_u connects to the SPI Flash chip U3's data communication terminal. and the first terminal of resistor R14;

[0036] The coprocessor U1C's digital signal terminal GPIO2_A5_u connects to the SPI Flash chip U3's data communication terminal. and the first terminal of resistor R15;

[0037] The power supply terminal VCCIO2_VCC of the coprocessor U1C is connected to the first terminal of capacitor C23, the first terminal of resistor R13, and the power supply VCCIO_FLASH.

[0038] The second terminal of resistor R13 is connected to power supply VCC_3V3, and the second terminal of capacitor C23 is grounded.

[0039] The second end of resistor R14 is connected to the positive terminal of the power supply VCC of SPI Flash chip U3, the first end of capacitor C24, the first end of capacitor C25, power supply VCC_3V3, and the second end of resistor R15.

[0040] The second terminal of capacitor C24 is connected to the second terminal of capacitor C25 and grounded;

[0041] The power supply ground terminal VSS of the SPI Flash chip U3 is grounded.

[0042] In a preferred embodiment of this utility model, the recording and storage unit includes: the reset terminal RST_N of the eMMC chip U9A is connected to the first terminal of the resistor R65, and the second terminal of the resistor R65 is connected to the power supply VCC_1V8.

[0043] The data terminal GPIO3_A0_d of the coprocessor U1E is connected to the first end of resistor R28, and the second end of resistor R28 is connected to the clock output terminal CLK of the eMMC chip U9A and the first end of capacitor C75.

[0044] The second terminal of capacitor C75 is grounded;

[0045] The data terminal GPIO3_A1_d of the coprocessor U1E is connected to the first terminal of resistor R59 and the instruction terminal CMD of the eMMC chip U9A;

[0046] The data terminal GPIO3_A2_d of the coprocessor U1E is connected to the first end of resistor R63 and the data transmission terminal DAT0 of the eMMC chip U9A.

[0047] The data terminal GPIO3_A3_d of the coprocessor U1E is connected to the first end of resistor R62 and the data transmission terminal DAT1 of the eMMC chip U9A;

[0048] The data terminal GPIO3_A4_d of the coprocessor U1E is connected to the first end of resistor R61 and the data transmission terminal DAT2 of the eMMC chip U9A;

[0049] The data terminal GPIO3_A5_d of the coprocessor U1E is connected to the first end of resistor R60 and the data transmission terminal DAT3 of the eMMC chip U9A.

[0050] The second terminal of resistor R59 is connected to the second terminals of resistors R63, R62, R61, and R60, and the power supply VCC_1V8.

[0051] The eMMC chip U9A's data strobe terminal DS is connected to the first terminal of resistor R64, and the second terminal of resistor R64 is grounded.

[0052] Connect the power ground terminal VSS of the eMMC chip U9A to the interface ground terminal VSSQ of the eMMC chip U9A and ground it;

[0053] The power supply terminal VSSIM of the eMMC chip U9A circuit is connected to the first terminal of resistor C79, and the second terminal of resistor C79 is grounded.

[0054] The power supply terminal VCCQ of the eMMC chip U9A interface is connected to the first terminals of resistors R72, R73, and R74, and the power supply VCC_1V8.

[0055] The second terminal of resistor R72 is grounded, the second terminal of resistor R73 is grounded, and the second terminal of resistor R74 is grounded.

[0056] The power supply terminal VCC of the eMMC chip U9A is connected to the first terminals of resistors R76, R77, and R78, and the power supply VCC_3V3.

[0057] The second terminal of resistor R76 is grounded, the second terminal of resistor R77 is grounded, and the second terminal of resistor R78 is grounded.

[0058] In a preferred embodiment of this utility model, the control platform communication unit includes: the first end of the data interface connected to the signal output terminal RXD of the isolation transceiver chip U11;

[0059] The signal input terminal TXD of the isolated transceiver chip U11 is connected to the second end of the data interface;

[0060] The power supply terminal VCC of the isolated transceiver chip U11 is connected to the first terminal of capacitor C102 and the 3.3V power supply VCC3V3_ISO, and the second terminal of capacitor C102 is grounded.

[0061] The grounding terminal GND of the isolated transceiver chip U11 is grounded;

[0062] The high-level signal terminal CANH of the isolation transceiver chip U11 is connected to the first terminal of resistor R61 and the signal B input terminal B1 of the signal surge suppression chip U12.

[0063] The low-level signal terminal CANL of the isolation transceiver chip U11 is connected to the second terminal of resistor R61 and the signal A input terminal A1 of the signal surge suppression chip U12;

[0064] The isolated transceiver chip U11's isolated output ground terminal CANG is connected to the ground terminal GND1 and GND2 of the signal surge suppression chip U12, the first terminal of resistor R183, and the first terminal of capacitor C90.

[0065] The signal surge suppression chip U12's signal B output terminal B2 is connected to the first terminal of resistor R184 and the first terminal of the CAN bus interface;

[0066] The ground terminal PE1 of the signal surge suppression chip U12 is connected to the ground terminal PE2 of the signal surge suppression chip U12, the second terminal of resistor R183, the second terminal of capacitor C90, and grounded.

[0067] The signal surge suppression chip U12 connects the signal A output terminal A2 to the second terminal of resistor R184 and the second terminal of the CAN bus interface.

[0068] In a preferred embodiment of this utility model, the power supply module includes:

[0069] The first regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R38, the first terminal of the capacitor C45, the first terminal of the capacitor C46, ​​the power input terminal VIN1 of the regulator U4, and the power input terminal VIN2 of the regulator U4.

[0070] The second terminal of capacitor C45 is grounded, and the second terminal of capacitor C46 is grounded.

[0071] The second terminal of resistor R38 is connected to the first terminal of capacitor C47 and the enable terminal EN of voltage regulator U4;

[0072] The power status indicator terminal PG of voltage regulator U4 is connected to the first terminal of resistor R53, and the second terminal of resistor R53 is connected to the second terminal of resistor R41.

[0073] The second terminal of capacitor C47 is grounded;

[0074] The power output terminal VOUT1 of voltage regulator U4 is connected to the power output terminal VOUT2 of voltage regulator U4, the first terminal of capacitor C48, the first terminal of capacitor C49 and the first terminal of capacitor C50, and outputs a 0.9V power supply VDD_0V9.

[0075] The second terminal of capacitor C48 is grounded, the second terminal of capacitor C49 is grounded, and the second terminal of capacitor C50 is grounded.

[0076] The output voltage fine-tuning terminal VOS of voltage regulator U4 is connected to the first terminal of resistor R39;

[0077] The second end of resistor R39 is connected to the feedback terminals FB1 and FB2 of voltage regulator U4 and the first end of resistor R40;

[0078] The second end of resistor R40 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U4 and then grounded.

[0079] The second regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R54, the first terminal of the capacitor C66, the first terminal of the capacitor C67, the power input terminal VIN1 of the regulator U8, and the power input terminal VIN2 of the regulator U8.

[0080] The second terminal of capacitor C66 is grounded, and the second terminal of capacitor C67 is grounded.

[0081] The second terminal of resistor R54 is connected to the first terminal of capacitor C68 and the enable terminal EN of voltage regulator U8.

[0082] The second terminal of capacitor C68 is grounded;

[0083] The power output terminal VOUT1 of voltage regulator U8 is connected to the power output terminal VOUT2 of voltage regulator U8, the first terminal of capacitor C69, the first terminal of capacitor C70, and the first terminal of capacitor C71, and outputs a 3.3V power supply VCC_3V3.

[0084] The second terminal of capacitor C69 is grounded, the second terminal of capacitor C70 is grounded, and the second terminal of capacitor C71 is grounded.

[0085] The output voltage fine-tuning terminal VOS of voltage regulator U8 is connected to the first terminal of resistor R55.

[0086] The second end of resistor R55 is connected to the feedback terminals FB1 and FB2 of voltage regulator U8 and the first end of resistor R58.

[0087] The second end of resistor R58 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U8 and then grounded.

[0088] The third regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R44, the first terminal of the capacitor C57, the first terminal of the capacitor C58, the power input terminal VIN1 of the regulator U6, and the power input terminal VIN2 of the regulator U6.

[0089] The second terminal of capacitor C57 is grounded, and the second terminal of capacitor C58 is grounded.

[0090] The second terminal of resistor R44 is connected to the first terminal of capacitor C59 and the enable terminal EN of voltage regulator U6, and the second terminal of capacitor C59 is grounded.

[0091] The power status indicator terminal PG of voltage regulator U6 is connected to the first terminal of resistor R56, and the second terminal of resistor R56 is connected to the second terminal of resistor R41.

[0092] The power output terminal VOUT1 of voltage regulator U6 is connected to the power output terminal VOUT2 of voltage regulator U6, the first terminal of capacitor C60, the first terminal of capacitor C61, the first terminal of capacitor C62, and outputs the CPU power supply VDD_CPU.

[0093] The second terminal of capacitor C60 is grounded, the second terminal of capacitor C61 is grounded, and the second terminal of capacitor C62 is grounded.

[0094] The voltage regulator U6 output voltage fine-tuning terminal VOS is connected to the first terminal of resistor R45. The second terminal of resistor R45 is connected to the first terminal of resistor R46, the feedback terminal FB1 of voltage regulator U6, the feedback terminal FB2 of voltage regulator U6, and the first terminal of resistor R51.

[0095] The second end of resistor R46 is connected to the grounding terminals GND2 and GND1 of voltage regulator U6 and then grounded.

[0096] The second terminal of resistor R51 is connected to the first terminal of capacitor C65, the first terminal of resistor R52, and the first terminal of resistor R50.

[0097] The second terminal of capacitor C65 is grounded, and the second terminal of resistor R52 is grounded.

[0098] The second end of resistor R50 is connected to the first end of resistor R48 and the PWM signal output terminal of coprocessor U1A. The second end of resistor R48 is connected to the 3.3V power supply VCC_3V3.

[0099] The fourth voltage regulator unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R41, the first terminal of the capacitor C51, the first terminal of the capacitor C52, the power input terminal VIN1 of the voltage regulator U5, and the power input terminal VIN2 of the voltage regulator U5.

[0100] The second terminal of capacitor C51 is grounded, and the second terminal of capacitor C52 is grounded.

[0101] The second terminal of resistor R41 is connected to the first terminal of capacitor C53 and the enable terminal EN of voltage regulator U5;

[0102] The second terminal of capacitor C53 is grounded;

[0103] The power status indicator terminal PG of voltage regulator U5 is connected to the first terminal of resistor R57, and the second terminal of resistor R57 is connected to the second terminal of resistor R54.

[0104] The power output terminal VOUT1 of voltage regulator U5 is connected to the power output terminal VOUT2 of voltage regulator U5, the first terminal of capacitor C54, the first terminal of capacitor C55, and the first terminal of capacitor C56, and outputs DDR power VCC_DDR.

[0105] The second terminal of capacitor C54 is grounded, the second terminal of capacitor C55 is grounded, and the second terminal of capacitor C56 is grounded.

[0106] The output voltage fine-tuning terminal VOS of voltage regulator U5 is connected to the first terminal of resistor R42;

[0107] The second end of resistor R42 is connected to the feedback terminals FB1 and FB2 of voltage regulator U5 and the first end of resistor R43;

[0108] The second end of resistor R43 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U5 and then grounded.

[0109] The fifth voltage regulator unit includes: a 3.3V power supply VCC_3V3 connected to the first terminal of capacitor C63 and the power input terminal VIN of voltage regulator U7, and the second terminal of capacitor C63 grounded;

[0110] The voltage regulator U7's voltage adjustment terminal GND / ADJ is connected to the first terminal of resistor R49 and the first terminal of resistor R47;

[0111] The second terminal of resistor R49 is grounded, and the second terminal of resistor R47 is connected to the first terminal of capacitor C64, the power output terminal VOUT_2 of voltage regulator U7, and the power output terminal VOUT_1 of voltage regulator U7, and outputs a 1.8V power supply VCC_1V8.

[0112] The second terminal of capacitor C64 is grounded;

[0113] The sixth power conversion unit includes: the power input terminal VIN of the DC-DC converter chip U61 is connected to the first end of resistor R16, the first end of capacitor C69, and a 25V power supply;

[0114] The control terminal CTRL of the DC-DC converter chip U61 is connected to the second terminal of resistor R16.

[0115] The ground terminal GND of DC-DC converter chip U61 is connected to the second terminal of capacitor C69 and grounded.

[0116] The positive voltage output terminal VO+ of the DC-DC converter chip U61 is connected to the first terminal of capacitor C21 and the first terminal of capacitor C72, and outputs a 12V power supply VCC12V.

[0117] The first terminal of the TRIM trimmer of the DC-DC converter chip U61 is connected to the first terminal of the resistor R18.

[0118] The negative voltage output terminal VO of DC-DC converter chip U61 is connected to the second terminal of resistor R18, the second terminal of capacitor C21 and the second terminal of capacitor C72, and then grounded.

[0119] The 7th voltage regulator unit includes: the voltage regulator chip U13, the power input terminal VIN is connected to the first terminal of resistor R17, the first terminal of capacitor C83, the first terminal of capacitor C5, the first terminal of capacitor C4, and the 12V power supply VCC12V.

[0120] The enable pin EN of the voltage regulator chip U13 is connected to the second terminal of resistor R17;

[0121] The voltage output terminal VOUT of the voltage regulator chip U13 is connected to the first terminal of capacitor C6, the first terminal of capacitor C7, and the first terminal of capacitor C86, and outputs a 3.3V power supply P3V3.

[0122] The voltage adjustment terminal VOS of the voltage regulator chip U13 is connected to the first terminal of resistor R19;

[0123] The feedback terminal of the voltage regulator chip U13 is connected to the second terminal of resistor R19 and the first terminal of resistor R3;

[0124] The ground terminal GND of the voltage regulator chip U13 is connected to the second terminals of capacitors C83, C5, C4, R3, C6, C7, and C86, and then grounded.

[0125] The 8th power conversion unit includes: the voltage input terminal of the adjustable voltage regulator D2 is connected to the first terminal of capacitor C73 and the power supply VCC_15V_IN;

[0126] The second terminal of capacitor C73 is grounded;

[0127] The voltage output terminal VOUT of the adjustable voltage regulator D2 is connected to the first terminal of resistor R171 and the voltage output terminal TAB / VOUT of the adjustable voltage regulator D2.

[0128] The adjustable voltage regulator D2 adjustment terminal ADJ is connected to the first terminal of resistor R172 and the first terminal of resistor R173;

[0129] The second terminal of resistor R171 is connected to the second terminal of resistor R172 and the first terminal of capacitor C74, and outputs a 14V power supply VCC_14V_DIS.

[0130] The second terminal of resistor R173 is grounded, and the second terminal of capacitor C74 is grounded.

[0131] In a preferred embodiment of this utility model, a cloud control platform is also included, which is connected to the coprocessor via an Ethernet interface (BT16A07).

[0132] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are: it supports remote control of the power supply status, can receive remote control commands through the network interface, realize remote operation of the power supply and real-time monitoring of the working status of the power supply hardware, and when abnormal conditions such as overvoltage, overcurrent, and overheating are detected, the control platform remotely issues an alarm.

[0133] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0134] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0135] Figure 1 This is a design block diagram of the multi-path controllable DC power supply display system of this utility model.

[0136] Figure 2 This is a schematic diagram of the circuit connection of the main control processor unit of this utility model.

[0137] Figure 3 This is a schematic diagram of the circuit connection of the reset control unit of this utility model.

[0138] Figure 4 This is a schematic diagram of the circuit connection of the software storage unit of this utility model.

[0139] Figure 5 This is a schematic diagram of the circuit connection of the recording and storage unit of this utility model.

[0140] Figure 6 This is a schematic diagram of the circuit connection of the coprocessor unit of this utility model.

[0141] Figure 7 This is a schematic diagram of the communication unit circuit connection of the control platform of this utility model.

[0142] Figure 8 This is a schematic diagram of the 5V power conversion circuit of this utility model.

[0143] Figure 9 This is a schematic diagram of the 0.9V power conversion circuit of this utility model.

[0144] Figure 10 This is a schematic diagram of the 3.3V power conversion circuit of this utility model.

[0145] Figure 11 This is a schematic diagram of the CPU power conversion circuit connection of this utility model.

[0146] Figure 12 This is a schematic diagram of the DDR power conversion circuit connection of this utility model.

[0147] Figure 13 This is a schematic diagram of the 1.8V power conversion circuit of this utility model.

[0148] Figure 14 This is a schematic diagram of the 12V power conversion circuit of this utility model.

[0149] Figure 15 This is a schematic diagram of the P3V3 power conversion circuit of this utility model.

[0150] Figure 16 This is a schematic diagram of the 14V power conversion circuit of this utility model. Detailed Implementation

[0151] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0152] like Figure 1 As shown, this utility model discloses a multi-path controlled DC power supply display system, wherein the design block diagram of the multi-path controlled DC power supply display system is as follows:

[0153] Includes: a control and storage module, a power supply module, a communication control module, and a display module;

[0154] The control storage module includes: a main control processor unit, a coprocessor unit, a software storage unit, and a record storage unit;

[0155] The communication control module includes: a control platform, a control platform communication unit, and a reset control unit;

[0156] The communication terminal of the main control processor unit is connected to the communication terminal of the coprocessor unit;

[0157] The reset terminal of the main control processor unit is connected to the reset terminal of the coprocessor unit;

[0158] The data terminal of the coprocessor unit is connected to the data terminal of the software storage unit and the data terminal of the record storage unit;

[0159] The control platform and the main control processor are connected through the control platform communication unit;

[0160] The voltage output terminal of the power module is connected to the voltage input terminal of the main control processor unit, coprocessor unit, software storage unit, record storage unit and control platform communication unit;

[0161] The display module is connected to the display signal terminal of the main control processor to display the current operation interface.

[0162] The SPI terminal of the main control processor unit is connected to a display screen. When the main control processor detects that the output voltage of the power module exceeds the rated voltage or the load current exceeds the rated current, it will give an alarm prompt through the display screen and indicator lights, requiring re-entry.

[0163] The main control processor unit and the coprocessor unit also have a debug serial port, for example, the debug serial port can be a reserved Micro-DB9 interface;

[0164] The system connects to an external keyboard via the I2C1 serial port and to the control platform via the CAN serial port. Target values ​​for voltage and current can be set. The main control processor detects whether the input voltage and current range exceeds the rated parameters of the power supply hardware. If the input voltage or current value exceeds the range, a prompt will be displayed on the screen requiring re-entry.

[0165] The coprocessor unit provides one debugging serial port for system debugging and one communication serial port for data exchange between the main control processor unit and the coprocessor unit. It also provides two 100M Ethernet interfaces to connect to the cloud control platform for software system debugging and remote control of the power module. To ensure system stability, a 1+1 backup design is adopted. Power acquisition data and operation commands are periodically stored on the eMMC connected to the recording processor. The coprocessor unit's SPI serial port is connected to an external SPI Flash chip to store the boot and application software. During program execution, a large amount of intermediate data and temporary variables are generated. DDR provides high-speed cache space for this data, facilitating fast CPU access and processing, reducing CPU waiting time for data, and improving data processing efficiency.

[0166] like Figure 2 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the main control processor unit circuit connection diagram shows the specific connection method:

[0167] The main control processor MCU serial port 1 transmitter UART1_TX is connected to the first end of resistor R110, and the second end of resistor R110 is connected to the coprocessor U1A digital signal input terminal GPIO0_C0_d;

[0168] The main control processor MCU serial port 1 receiver UART1_RX is connected to the first end of resistor R111, and the second end of resistor R111 is connected to the digital signal output terminal GPIO0_C1_d of coprocessor U1A;

[0169] The main control processor MCU serial port 2 transmitter UART2_TX is connected to the first end of resistor R141, and the second end of resistor R141 is connected to the coprocessor U1A digital signal input terminal GPIO0_A0_u;

[0170] The main control processor MCU serial port 2 receiver UART2_RX is connected to the first end of resistor R142, and the second end of resistor R142 is connected to the digital signal output terminal GPIO0_A2_u of coprocessor U1A.

[0171] The main control processor MCU serial port 3 transmitter UART3_TX is connected to the first end of resistor R143, and the second end of resistor R143 is connected to the coprocessor U1A digital signal input terminal GPIO0_B7_d;

[0172] The main control processor MCU serial port 3 receiver terminal UART3_RX is connected to the first end of resistor R144, and the second end of resistor R144 is connected to the digital signal output terminal GPIO0_B6_d of the communication coprocessor U1A.

[0173] The UART1 receive / transmit (RX / TX) terminal is connected to the coprocessor communication signal terminal through resistors R110 / R111 to realize communication between the main control processor and the coprocessor;

[0174] The CAN0_TX / RX (Controller Area Network) terminal connects to the control platform through the control platform communication unit, ensuring reliable communication between the devices (control platform and main control processor) connected at both ends of the communication circuit.

[0175] An external keyboard can be connected to the I2C1_SCL / SDA terminal, and an external display screen can be connected to the SPI3_NSS / SCK terminal. Input can be made via the buttons, and the display screen will show the corresponding operation interface.

[0176] like Figure 3 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the specific connection method of the reset control unit circuit is as follows:

[0177] Reset chip U2 manual reset terminal Connect the first terminal of capacitor C17 to the first terminal of resistor R3, and connect the second terminal of resistor R3 to the power supply VCC3V3_PMUIO.

[0178] The ground terminal GND of the reset chip U2 is connected to the second terminal of capacitor C17 and the first terminal of capacitor C18 and grounded.

[0179] Reset chip U2 reset output terminal Connect the first end of resistor R4, the first end of resistor R5, and the reset terminal NPOR of coprocessor U1A. Connect the second end of resistor R4 to the power supply VCC3V3_PMUIO.

[0180] The second end of resistor R5 is connected to the digital signal terminal GPIO0_C5_Z of coprocessor U1A;

[0181] The power supply terminal VCC of the reset chip U2 is connected to the second terminal of capacitor C18 and the power supply VCC3V3_PMUIO.

[0182] The reset button is connected to the manual reset terminal of the reset chip U2 (MAX811S). The other end of the reset button is grounded. When the reset button is pressed, a low-level signal is sent to the reset chip U2, and the reset chip U2 resets its output. Send a reset signal to the coprocessor U1A.

[0183] like Figure 4 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the specific connection method of the software storage unit circuit is as follows:

[0184] The coprocessor U1C's digital signal terminal GPIO2_A0_u is connected to the SPI Flash chip U3 chip select signal.

[0185] The digital signal terminal GPIO2_A1_d of the coprocessor U1C is connected to the first end of resistor R12, and the second end of resistor R12 is connected to the clock signal terminal C of the SPI Flash chip U3.

[0186] The coprocessor U1C's digital signal terminal GPIO2_A2_u is connected to the SPI Flash chip U3's data output / input terminal DQ0;

[0187] The coprocessor U1C's digital signal terminal GPIO2_A3_u is connected to the SPI Flash chip U3's data output / input terminal DQ1;

[0188] The coprocessor U1C's digital signal terminal GPIO2_A4_u connects to the SPI Flash chip U3's data communication terminal. and the first terminal of resistor R14;

[0189] The coprocessor U1C's digital signal terminal GPIO2_A5_u connects to the SPI Flash chip U3's data communication terminal. and the first terminal of resistor R15;

[0190] The power supply terminal VCCIO2_VCC of the coprocessor U1C is connected to the first terminal of capacitor C23, the first terminal of resistor R13, and the power supply VCCIO_FLASH.

[0191] The second terminal of resistor R13 is connected to power supply VCC_3V3, and the second terminal of capacitor C23 is grounded.

[0192] The second end of resistor R14 is connected to the positive terminal VCC of the SPI Flash chip U3 power supply, the first end of capacitor C24, the first end of capacitor C25, the 3.3V power supply, and the second end of resistor R15.

[0193] The second terminal of capacitor C24 is connected to the second terminal of capacitor C25 and grounded;

[0194] The power ground terminal VSS of the SPI Flash chip U3 is grounded.

[0195] The capacitance of capacitor C24 is 10uF, the capacitance of capacitor C25 is 100nF, the capacitance of resistors R14 and R15 is 10K, and the SPI Flash chip U3 (N25Q128A13ESE40) is used to store the boot and application software.

[0196] like Figure 5 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the specific connection method of the recording and storage unit circuit connection diagram is as follows:

[0197] The reset pin RST_N of the eMMC chip U9A is connected to the first end of resistor R65, and the second end of resistor R65 is connected to the power supply VCC_1V8.

[0198] The data terminal GPIO3_A0_d of the coprocessor U1E is connected to the first end of resistor R28, and the second end of resistor R28 is connected to the clock output terminal CLK of the eMMC chip U9A and the first end of capacitor C75.

[0199] The second terminal of capacitor C75 is grounded;

[0200] The data terminal GPIO3_A1_d of the coprocessor U1E is connected to the first end of resistor R59 and the instruction terminal CMD of the eMMC chip U9A;

[0201] The data terminal GPIO3_A2_d of the coprocessor U1E is connected to the first end of resistor R63 and the data transmission terminal DAT0 of the eMMC chip U9A.

[0202] The data terminal GPIO3_A3_d of the coprocessor U1E is connected to the first end of resistor R62 and the data transmission terminal DAT1 of the eMMC chip U9A;

[0203] The data terminal GPIO3_A4_d of the coprocessor U1E is connected to the first end of resistor R61 and the data transmission terminal DAT2 of the eMMC chip U9A.

[0204] The data terminal GPIO3_A5_d of the coprocessor U1E is connected to the first end of resistor R60 and the data transmission terminal DAT3 of the eMMC chip U9A.

[0205] The second terminal of resistor R59 is connected to the second terminals of resistors R63, R62, R61, and R60, and the power supply VCC_1V8.

[0206] The eMMC chip U9A's data strobe terminal DS is connected to the first terminal of resistor R64, and the second terminal of resistor R64 is grounded.

[0207] Connect the power ground terminal VSS of the eMMC chip U9A to the interface ground terminal VSSQ of the eMMC chip U9A and ground it;

[0208] The power supply terminal VSSIM of the eMMC chip U9A circuit is connected to the first terminal of resistor C79, and the second terminal of resistor C79 is grounded.

[0209] The power supply terminal VCCQ of the eMMC chip U9A interface is connected to the first terminals of resistors R72, R73, and R74, and the power supply VCC_1V8.

[0210] The second terminal of resistor R72 is grounded, the second terminal of resistor R73 is grounded, and the second terminal of resistor R74 is grounded.

[0211] The power supply terminal VCC of the eMMC chip U9A is connected to the first terminals of resistors R76, R77, and R78, and the power supply VCC_3V3.

[0212] The second terminal of resistor R76 is grounded, the second terminal of resistor R77 is grounded, and the second terminal of resistor R78 is grounded.

[0213] The second and fifth voltage regulator units output 3.3V (VCC_3V3) and 1.8V (VCC_1V8) respectively to provide the eMMC chip with both 3.3V and 1.8V voltages, meeting the voltage requirements of the eMMC chip (FEMDRW064G-88A19). Capacitors C72, C73, and C76 have a capacitance of 100nF, capacitors C78 and C74 have a capacitance of 4.7uF, and resistors R59, R62, and R64 have a resistance of 10KΩ. The coprocessor U1E periodically stores the power acquisition data and operation commands on the eMMC chip connected to the MMC serial port of the coprocessor U1E.

[0214] like Figure 6As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the specific connection method of the coprocessor unit circuit connection diagram is as follows:

[0215] The oscillator output terminal OSC_XOUT of the coprocessor U1A is connected to the first terminal of resistor R1 and the first terminal of resistor R2;

[0216] The oscillator input terminal OSC_XIN of the coprocessor U1A is connected to the second terminal of resistor R2, the first terminal of capacitor C15, and the crystal output terminal X1 of crystal oscillator Y1;

[0217] The second terminal of capacitor C15 is grounded, and the second terminal of resistor R1 is connected to the first terminal of capacitor C16 and the crystal input terminal X2 of crystal oscillator Y1.

[0218] The second terminal of capacitor C16 is grounded, and the ground terminal of crystal oscillator Y1 is grounded;

[0219] The power supply terminal ASYS_PLL_AVDD1V8 of the coprocessor U1A is connected to the power supply VCC_1V8 and the first terminal of capacitor C19, and the second terminal of capacitor C19 is grounded.

[0220] The reset signal terminal NPOR of the coprocessor U1A is connected to the first terminal of capacitor C20, and the second terminal of capacitor C20 is grounded.

[0221] The coprocessor U1A is mainly divided into two parts: the OSC / PLL area and the PMUIO Domain. The OSC / PLL area is mainly responsible for clock signal generation and output, providing the basic clock source for the system. The PMUIO Domain area is mainly responsible for integrating power management and general I / O functions, supporting UART, I2C2, PWM and Ethernet clock output. The coprocessor U1A can realize clock generation, power management, multi-channel serial communication (UART / I2C), PWM control and Ethernet clock synchronization. It communicates with the main control processor MCU through UART, and other general input and output terminals can be used for custom function expansion.

[0222] like Figure 7 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection method of the control platform communication unit is as follows:

[0223] The signal output terminal RXD of the isolated transceiver chip U11 is connected to the first end of the data interface;

[0224] The signal input terminal TXD of the isolated transceiver chip U11 is connected to the second end of the data interface;

[0225] The power supply terminal VCC of the isolated transceiver chip U11 is connected to the first terminal of capacitor C102 and the 3.3V power supply VCC3V3_ISO, and the second terminal of capacitor C102 is grounded.

[0226] The grounding terminal GND of the isolated transceiver chip U11 is grounded;

[0227] The high-level signal terminal CANH of the isolation transceiver chip U11 is connected to the first terminal of resistor R61 and the signal B input terminal B1 of the signal surge suppression chip U12.

[0228] The low-level signal terminal CANL of the isolation transceiver chip U11 is connected to the second terminal of resistor R61 and the signal A input terminal A1 of the signal surge suppression chip U12;

[0229] The isolated transceiver chip U11's isolated output ground terminal CANG is connected to the ground terminal GND1 and GND2 of the signal surge suppression chip U12, the first terminal of resistor R183, and the first terminal of capacitor C90.

[0230] The signal surge suppression chip U12's signal B output terminal B2 is connected to the first terminal of resistor R184 and the first terminal of the CAN bus interface;

[0231] The ground terminal PE1 of the signal surge suppression chip U12 is connected to the ground terminal PE2 of the signal surge suppression chip U12, the second terminal of resistor R183, the second terminal of capacitor C90, and grounded.

[0232] The signal surge suppression chip U12 connects the second terminal of the signal A output terminal A2 to the second terminal of the resistor R184 and the second terminal of the CAN bus interface.

[0233] The first and second ends of the CAN bus interface of the control platform are connected to the signal surge suppression chip U12's signal B output terminal B2 and signal A output terminal A2, respectively, to achieve safe and stable signal transmission. The isolated transceiver chip U11 (CTM1051AMG) ensures electrical isolation between external devices and the main control processor. The isolated signal communicates with the main control processor through an internal path (CAN_TXD / CAN_RXD). The 3.3V power supply VCC3V3_ISO output from the power module powers the communication module.

[0234] like Figure 8 As shown in the diagram, this utility model discloses a multi-channel controlled DC power supply display system, wherein the 5V power conversion circuit connection diagram shows the specific connection method:

[0235] The diagram shows the specific circuit connection method for converting a 5V power supply VCC_5V_IN to a 5V power supply VCC5V0_SYS through a filter protection module:

[0236] Filtering and protection module: The 5V power supply VCC_5V_IN is connected to the first terminal of fuse F1. The second terminal of fuse F1 is connected to the negative terminal of diode D1, the first terminal of capacitor C42, the first terminal of capacitor C43 and the first terminal of capacitor C44, and outputs the 5V power supply VCC5V0_SYS.

[0237] The positive terminal of diode D1 is grounded, the second terminal of capacitor C42 is grounded, the second terminal of capacitor C43 is grounded, and the second terminal of capacitor C44 is grounded.

[0238] The input 5V power supply VCC_5V_IN is converted into a stable 5V power supply VCC5V0_SYS output through a filter protection module. Fuse F1 provides overcurrent protection, diode D1 (SMAJ6.0) provides surge overvoltage protection, and three capacitors connected in parallel with different voltages provide filter protection.

[0239] like Figure 9 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection diagram of the 0.9V power conversion circuit is as follows:

[0240] The 5V power supply VCC5V0_SYS is connected to the first terminal of resistor R38, the first terminal of capacitor C45, the first terminal of capacitor C46, ​​the power input terminal VIN1 of voltage regulator U4, and the power input terminal VIN2 of voltage regulator U4.

[0241] The second terminal of capacitor C45 is grounded, and the second terminal of capacitor C46 is grounded.

[0242] The second terminal of resistor R38 is connected to the first terminal of capacitor C47 and the enable terminal EN of voltage regulator U4;

[0243] The power status indicator terminal PG of voltage regulator U4 is connected to the first terminal of resistor R53, and the second terminal of resistor R53 is connected to the second terminal of resistor R41.

[0244] The second terminal of capacitor C47 is grounded;

[0245] The power output terminal VOUT1 of voltage regulator U4 is connected to the power output terminal VOUT2 of voltage regulator U4, the first terminal of capacitor C48, the first terminal of capacitor C49 and the first terminal of capacitor C50, and outputs a 0.9V power supply VDD_0V9.

[0246] The second terminal of capacitor C48 is grounded, the second terminal of capacitor C49 is grounded, and the second terminal of capacitor C50 is grounded.

[0247] The output voltage fine-tuning terminal VOS of voltage regulator U4 is connected to the first terminal of resistor R39;

[0248] The second end of resistor R39 is connected to the feedback terminals FB1 and FB2 of voltage regulator U4 and the first end of resistor R40;

[0249] The second end of resistor R40 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U4 and then grounded.

[0250] The 5V power supply VCC5V0_SYS input voltage is stably converted to a 0.9V power supply VDD_0V9 output; the 0.9V power supply voltage is output through the regulator U4 (NAE03S03-B), setting resistor R39 (20K), and resistor R40 (160K).

[0251] like Figure 10 As shown, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection diagram of the 3.3V power conversion circuit is as follows:

[0252] The 5V power supply VCC5V0_SYS is connected to the first terminal of resistor R54, the first terminal of capacitor C66, the first terminal of capacitor C67, the power input terminals VIN1 and VIN2 of voltage regulator U8;

[0253] The second terminal of capacitor C66 is grounded, and the second terminal of capacitor C67 is grounded.

[0254] The second terminal of resistor R54 is connected to the first terminal of capacitor C68 and the enable terminal EN of voltage regulator U8.

[0255] The second terminal of capacitor C68 is grounded;

[0256] The power output terminal VOUT1 of the voltage regulator U8 is connected to the power output terminal VOUT2 of the voltage regulator U8, the first terminal of capacitor C69, the first terminal of capacitor C70, and the first terminal of capacitor C71, and outputs a 3.3V power supply VCC_3V3 (also called power supply VCC3V3_PMUIO).

[0257] The second terminal of capacitor C69 is grounded, the second terminal of capacitor C70 is grounded, and the second terminal of capacitor C71 is grounded.

[0258] The output voltage fine-tuning terminal VOS of voltage regulator U8 is connected to the first terminal of resistor R55.

[0259] The second end of resistor R55 is connected to the feedback terminals FB1 and FB2 of voltage regulator U8 and the first end of resistor R58.

[0260] The second end of resistor R58 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U8 and then grounded.

[0261] The 5V power supply VCC5V0_SYS input voltage is stably converted to a 3.3V power supply VCC_3V3 output; the 3.3V power supply voltage is output through the regulator U8 (NAE03S03-B), setting resistor R55 (20K), and resistor R58 (6.34K).

[0262] like Figure 11 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the CPU power conversion circuit connection diagram shows the specific connection method:

[0263] The 5V power supply VCC5V0_SYS is connected to the first terminal of resistor R44, the first terminal of capacitor C57, the first terminal of capacitor C58, the power input terminals VIN1 and VIN2 of voltage regulator U6;

[0264] The second terminal of capacitor C57 is grounded, and the second terminal of capacitor C58 is grounded.

[0265] The second terminal of resistor R44 is connected to the first terminal of capacitor C59 and the enable terminal EN of voltage regulator U6, and the second terminal of capacitor C59 is grounded.

[0266] The power status indicator terminal PG of voltage regulator U6 is connected to the first terminal of resistor R56, and the second terminal of resistor R56 is connected to the second terminal of resistor R41.

[0267] The power output terminal VOUT1 of voltage regulator U6 is connected to the power output terminal VOUT2 of voltage regulator U6, the first terminal of capacitor C60, the first terminal of capacitor C61, and the first terminal of capacitor C62, and outputs the CPU power supply VDD_CPU.

[0268] The second terminal of capacitor C60 is grounded, the second terminal of capacitor C61 is grounded, and the second terminal of capacitor C62 is grounded.

[0269] The voltage regulator U6 output voltage fine-tuning terminal VOS is connected to the first terminal of resistor R45. The second terminal of resistor R45 is connected to the first terminal of resistor R46, the feedback terminal FB1 of voltage regulator U6, the feedback terminal FB2 of voltage regulator U6, and the first terminal of resistor R51.

[0270] The second end of resistor R46 is connected to the grounding terminals GND2 and GND1 of voltage regulator U6 and then grounded.

[0271] The second terminal of resistor R51 is connected to the first terminal of capacitor C65, the first terminal of resistor R52, and the first terminal of resistor R50.

[0272] The second terminal of capacitor C65 is grounded, and the second terminal of resistor R52 is grounded.

[0273] The second end of resistor R50 is connected to the first end of resistor R48 and the PWM signal output terminal of coprocessor U1A. The second end of resistor R48 is connected to the 3.3V power supply VCC_3V3.

[0274] The feedback network R45 (20K) and R46 (160K) and the PWM signal output of the coprocessor U1A achieve dynamic voltage regulation. The PWM signal output by the coprocessor U1A adjusts the duty cycle to adjust the effective resistance value of the feedback network, thereby changing the output voltage. It provides a dynamically adjustable low-voltage high-current power supply to the CPU. The voltage is stabilized by the voltage regulator U6 (NAE03S03-B), the feedback network R45 (20K) and R46 (160K), and the filter capacitor.

[0275] like Figure 12 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the DDR power conversion circuit connection diagram shows the specific connection method:

[0276] The 5V power supply VCC5V0_SYS is connected to the first terminal of resistor R41, the first terminal of capacitor C51, the first terminal of capacitor C52, the power input terminal VIN1 of voltage regulator U5, and the power input terminal VIN2 of voltage regulator U5.

[0277] The second terminal of capacitor C51 is grounded, and the second terminal of capacitor C52 is grounded.

[0278] The second terminal of resistor R41 is connected to the first terminal of capacitor C53 and the enable terminal EN of voltage regulator U5;

[0279] The second terminal of capacitor C53 is grounded;

[0280] The power status indicator terminal PG of voltage regulator U5 is connected to the first terminal of resistor R57, and the second terminal of resistor R57 is connected to the second terminal of resistor R54.

[0281] The power output terminal VOUT1 of voltage regulator U5 is connected to the power output terminal VOUT2 of voltage regulator U5, the first terminal of capacitor C54, the first terminal of capacitor C55, and the first terminal of capacitor C56, and outputs DDR power VCC_DDR.

[0282] The second terminal of capacitor C54 is grounded, the second terminal of capacitor C55 is grounded, and the second terminal of capacitor C56 is grounded.

[0283] The output voltage fine-tuning terminal VOS of voltage regulator U5 is connected to the first terminal of resistor R42;

[0284] The second end of resistor R42 is connected to the feedback terminals FB1 and FB2 of voltage regulator U5 and the first end of resistor R43;

[0285] The second end of resistor R43 is connected to the grounding terminal GND2 and GND1 of voltage regulator U5 and then grounded.

[0286] The 5V power supply VCC5V0_SYS input voltage is stably converted to the DDR power supply VCC_DDR output to provide a stable voltage value for the DDR memory. The output voltage is 0.9V through the voltage regulator U5 (NAE03S03-B), setting resistor R42 (20K), and R43 (28.7K).

[0287] like Figure 13 As shown, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection diagram of the 1.8V power conversion circuit is as follows:

[0288] The 3.3V power supply VCC_3V3 is connected to the first terminal of capacitor C63 and the power input terminal VIN of voltage regulator U7, and the second terminal of capacitor C63 is grounded.

[0289] The voltage regulator U7's voltage adjustment terminal GND / ADJ is connected to the first terminal of resistor R49 and the first terminal of resistor R47;

[0290] The second terminal of resistor R49 is grounded, and the second terminal of resistor R47 is connected to the first terminal of capacitor C64, the power output terminal VOUT_2 of voltage regulator U7, and the power output terminal VOUT_1 of voltage regulator U7, and outputs a 1.8V power supply VCC_1V8.

[0291] The second terminal of capacitor C64 is grounded;

[0292] The 3.3V power supply VCC_3V3 input is converted into a stable 1.8V power supply VCC_1V8 output to power the chip that requires 1.8V; the 1.8V power supply voltage is output through the regulator U7 (ZTP1117SA), setting resistor R47 (270Ω), and R49 (120Ω).

[0293] The power module is a multi-voltage output system. Its core function is to convert voltages (such as VCC5V0_SYS, VCC_3V3, etc.) into the operating voltages required by the internal functional units (CPU, DDR, communication interface, etc.) to ensure stable system operation. Its design takes into account efficiency and noise control.

[0294] Its main control processor and co-controller's VDD / VSS terminals are directly powered by the 0.9V power supply of the power module, emphasizing low-noise design to avoid degradation of ADC / DAC accuracy;

[0295] The power supply VCCQ (1.8V) is directly connected to the 1.8V power supply VCC_1V8. It is necessary to isolate the power supply plane noise through a ferrite bead (such as FB101).

[0296] like Figure 14 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the 12V power conversion circuit connection diagram shows the specific connection method:

[0297] The control terminal CTRL of the DC-DC converter chip U61 is connected to the second terminal of resistor R16.

[0298] The ground terminal GND of DC-DC converter chip U61 is connected to the second terminal of capacitor C69 and grounded.

[0299] The positive voltage output terminal VO+ of the DC-DC converter chip U61 is connected to the first terminal of capacitor C21 and the first terminal of capacitor C72, and outputs a 12V power supply VCC12V.

[0300] The first terminal of the TRIM trimmer of the DC-DC converter chip U61 is connected to the first terminal of the resistor R18.

[0301] The negative voltage output terminal VO of DC-DC converter chip U61 is connected to the second terminal of resistor R18, the second terminal of capacitor C21 and the second terminal of capacitor C72, and then grounded.

[0302] The circuit is built around the DC-DC converter chip U61 (URB2405YMD-15WR3); it converts the input 25V voltage into a stable 12V output voltage.

[0303] This circuit achieves electrical isolation between input and output through an internal transformer, blocks common-mode interference, and improves the system's anti-interference capability. It can also achieve fine-tuning of output voltage and control of operating mode through the TRIM and CTRL terminals.

[0304] like Figure 15 As shown in the diagram, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection method of the P3V3 power conversion circuit is as follows:

[0305] The power input terminal VIN of the voltage regulator chip U13 is connected to the first terminal of resistor R17, the first terminal of capacitor C83, the first terminal of capacitor C5, the first terminal of capacitor C4, and the power supply VCC12V.

[0306] The enable pin EN of the voltage regulator chip U13 is connected to the second terminal of resistor R17;

[0307] The voltage output terminal VOUT of the voltage regulator chip U13 is connected to the first terminal of capacitor C6, the first terminal of capacitor C7, and the first terminal of capacitor C86, and outputs a 3.3V power supply P3V3.

[0308] The voltage adjustment terminal VOS of the voltage regulator chip U13 is connected to the first terminal of resistor R19;

[0309] The feedback terminal of the voltage regulator chip U13 is connected to the second terminal of resistor R19 and the first terminal of resistor R3;

[0310] The ground terminal GND of the voltage regulator chip U13 is connected to the second terminals of capacitors C83, C5, C4, R3, C6, C7, and C86, and then grounded.

[0311] The circuit is built around the voltage regulator chip U13 (nae03s03-b). Through resistors R17 (10K), R19 (20K), and R3 (6.49K), the input 12V voltage is stably regulated to the operating 3.3V voltage required by other chips, ensuring stable operation of the load.

[0312] like Figure 16 As shown, this utility model discloses a multi-path controlled DC power supply display system, wherein the connection diagram of the 14V power conversion circuit is as follows:

[0313] The voltage input terminal of the adjustable voltage regulator D2 is connected to the first terminal of capacitor C73 and the power supply VCC_15V_IN;

[0314] The second terminal of capacitor C73 is grounded;

[0315] The voltage output terminal VOUT of the adjustable voltage regulator D2 is connected to the first terminal of resistor R171 and the voltage output terminal TAB / VOUT of the adjustable voltage regulator D2.

[0316] The adjustable voltage regulator D2 adjustment terminal ADJ is connected to the first terminal of resistor R172 and the first terminal of resistor R173;

[0317] The second terminal of resistor R171 is connected to the second terminal of resistor R172 and the first terminal of capacitor C74, and outputs a 14V power supply VCC_14V_DIS.

[0318] The second terminal of resistor R173 is grounded, and the second terminal of capacitor C74 is grounded.

[0319] By adjusting the resistors R127 (240R) and R173 (2.49K) on the adjustment terminal ADJ of the adjustable voltage regulator D2 (LM317EMP), a stable output voltage of 14V, 14V power supply VCC_14V_DIS, is generated to power the display module.

[0320] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A multi-path controlled DC power supply display system, characterized in that, include: Control storage module, power supply module, communication control module, and display module; The control storage module includes: a main control processor unit, a coprocessor unit, a software storage unit, and a record storage unit; The communication control module includes: a control platform, a control platform communication unit, and a reset control unit; The communication terminal of the main control processor unit is connected to the communication terminal of the coprocessor unit; The reset terminal of the main control processor unit is connected to the reset terminal of the coprocessor unit; The data terminal of the coprocessor unit is connected to the data terminal of the software storage unit and the data terminal of the record storage unit; The control platform and the main control processor are connected through the control platform communication unit; The voltage output terminal of the power module is connected to the voltage input terminal of the main control processor unit, coprocessor unit, software storage unit, record storage unit and control platform communication unit; The display module is connected to the display signal terminal of the main control processor to display the current operation interface.

2. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The main control processor unit includes: The main control processor MCU serial port 1 data transmitter UART1_TX is connected to the first end of resistor R110, and the second end of resistor R110 is connected to the coprocessor U1A data receiver GPIO0_C0_d; The main control processor MCU serial port 1 data receiver UART1_RX is connected to the first end of resistor R111, and the second end of resistor R111 is connected to the coprocessor U1A data transmitter GPIO0_C1_d; The main control processor MCU serial port 2 data transmitter UART2_TX is connected to the first end of resistor R141, and the second end of resistor R141 is connected to the coprocessor U1A data receiver GPIO0_A0_u; The main control processor MCU serial port 2 data receiving terminal UART2_RX is connected to the first end of resistor R142, and the second end of resistor R142 is connected to the coprocessor U1A data transmitting terminal GPIO0_A2_u; The main control processor MCU serial port 3 data transmitter UART3_TX is connected to the first end of resistor R143, and the second end of resistor R143 is connected to the coprocessor U1A data receiver GPIO0_B7_d. The main control processor MCU serial port 3 data receiving terminal UART3_RX is connected to the first end of resistor R144, and the second end of resistor R144 is connected to the communication processor U1A data transmitting terminal GPIO0_B6_d.

3. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The reset control unit includes: Reset chip U2 manual reset terminal Connect the first terminal of capacitor C17 to the first terminal of resistor R3, and connect the second terminal of resistor R3 to the power supply VCC3V3_PMUIO. The ground terminal GND of the reset chip U2 is connected to the second terminal of capacitor C17 and the first terminal of capacitor C18 and grounded. Reset chip U2 reset output terminal Connect the first end of resistor R4, the first end of resistor R5, and the reset terminal NPOR of coprocessor U1A. Connect the second end of resistor R4 to the power supply VCC3V3_PMUIO. The second end of resistor R5 is connected to the digital signal terminal GPIO0_C5_Z of coprocessor U1A; The power supply terminal VCC of the reset chip U2 is connected to the second terminal of capacitor C18 and the power supply VCC3V3_PMUIO.

4. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The coprocessor unit includes: The oscillator output terminal OSC_XOUT of the coprocessor U1A is connected to the first terminal of resistor R1 and the first terminal of resistor R2; The oscillator input terminal OSC_XIN of the coprocessor U1A is connected to the second terminal of resistor R2, the first terminal of capacitor C15, and the crystal output terminal X1 of crystal oscillator Y1; The second terminal of capacitor C15 is grounded, and the second terminal of resistor R1 is connected to the first terminal of capacitor C16 and the crystal input terminal X2 of crystal oscillator Y1. The second terminal of capacitor C16 is grounded, and the ground terminal GND of crystal oscillator Y1 is grounded. The power supply terminal ASYS_PLL_AVDD1V8 of the coprocessor U1A is connected to the power supply VCC_1V8 and the first terminal of capacitor C19, and the second terminal of capacitor C19 is grounded. The reset signal terminal NPOR of the coprocessor U1A is connected to the first terminal of capacitor C10, and the second terminal of capacitor C10 is grounded.

5. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The software storage unit includes: The coprocessor U1C's digital signal terminal GPIO2_A0_u is connected to the SPI Flash chip U3 chip select signal. The digital signal terminal GPIO2_A1_d of the coprocessor U1C is connected to the first end of resistor R12, and the second end of resistor R12 is connected to the clock signal terminal C of the SPIFlash chip U3. The coprocessor U1C's digital signal terminal GPIO2_A2_u is connected to the SPI Flash chip U3's data communication terminal DQ0; The coprocessor U1C's digital signal terminal GPIO2_A3_u is connected to the SPI Flash chip U3's data communication terminal DQ1; The coprocessor U1C's digital signal terminal GPIO2_A4_u connects to the SPI Flash chip U3's data communication terminal. / VPP / DQ2 and the first terminal of resistor R14; The coprocessor U1C's digital signal terminal GPIO2_A5_u connects to the SPI Flash chip U3's data communication terminal. / DQ3 and the first terminal of resistor R15; The power supply terminal VCCIO2_VCC of the coprocessor U1C is connected to the first terminal of capacitor C23, the first terminal of resistor R13, and the power supply VCCIO_FLASH. The second terminal of resistor R13 is connected to power supply VCC_3V3, and the second terminal of capacitor C23 is grounded. The second end of resistor R14 is connected to the positive terminal of the power supply VCC of SPI Flash chip U3, the first end of capacitor C24, the first end of capacitor C25, power supply VCC_3V3, and the second end of resistor R15. The second terminal of capacitor C24 is connected to the second terminal of capacitor C25 and grounded; The power ground terminal VSS of the SPI Flash chip U3 is grounded.

6. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The recording storage unit includes: The reset pin RST_N of the eMMC chip U9A is connected to the first end of resistor R65, and the second end of resistor R65 is connected to the power supply VCC_1V8. The data terminal GPIO3_A0_d of the coprocessor U1E is connected to the first end of resistor R28, and the second end of resistor R28 is connected to the clock output terminal CLK of the eMMC chip U9A and the first end of capacitor C75. The second terminal of capacitor C75 is grounded; The data terminal GPIO3_A1_d of the coprocessor U1E is connected to the first terminal of resistor R59 and the instruction terminal CMD of the eMMC chip U9A; The data terminal GPIO3_A2_d of the coprocessor U1E is connected to the first end of resistor R63 and the data transmission terminal DAT0 of the eMMC chip U9A. The data terminal GPIO3_A3_d of the coprocessor U1E is connected to the first end of resistor R62 and the data transmission terminal DAT1 of the eMMC chip U9A; The data terminal GPIO3_A4_d of the coprocessor U1E is connected to the first end of resistor R61 and the data transmission terminal DAT2 of the eMMC chip U9A; The data terminal GPIO3_A5_d of the coprocessor U1E is connected to the first end of resistor R60 and the data transmission terminal DAT3 of the eMMC chip U9A. The second terminal of resistor R59 is connected to the second terminals of resistors R63, R62, R61, and R60, and the power supply VCC_1V8. The eMMC chip U9A's data strobe terminal DS is connected to the first terminal of resistor R64, and the second terminal of resistor R64 is grounded. Connect the power ground terminal VSS of the eMMC chip U9A to the interface ground terminal VSSQ of the eMMC chip U9A and ground it; The power supply terminal VSSIM of the eMMC chip U9A circuit is connected to the first terminal of resistor C79, and the second terminal of resistor C79 is grounded. The power supply terminal VCCQ of the eMMC chip U9A interface is connected to the first terminals of resistors R72, R73, and R74, and the power supply VCC_1V8. The second terminal of resistor R72 is grounded, the second terminal of resistor R73 is grounded, and the second terminal of resistor R74 is grounded. The power supply terminal VCC of the eMMC chip U9A is connected to the first terminals of resistors R76, R77, and R78, and the power supply VCC_3V3. The second terminal of resistor R76 is grounded, the second terminal of resistor R77 is grounded, and the second terminal of resistor R78 is grounded.

7. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The control platform communication unit includes: The signal output terminal RXD of the isolated transceiver chip U11 is connected to the first end of the data interface; The signal input terminal TXD of the isolated transceiver chip U11 is connected to the second end of the data interface; The power supply terminal VCC of the isolated transceiver chip U11 is connected to the first terminal of capacitor C102 and the 3.3V power supply VCC3V3_ISO, and the second terminal of capacitor C102 is grounded. The grounding terminal GND of the isolated transceiver chip U11 is grounded; The high-level signal terminal CANH of the isolation transceiver chip U11 is connected to the first terminal of resistor R61 and the signal B input terminal B1 of the signal surge suppression chip U12. The low-level signal terminal CANL of the isolation transceiver chip U11 is connected to the second terminal of resistor R61 and the signal A input terminal A1 of the signal surge suppression chip U12; The isolated transceiver chip U11's isolated output ground terminal CANG is connected to the ground terminal GND1 and GND2 of the signal surge suppression chip U12, the first terminal of resistor R183, and the first terminal of capacitor C90. The signal surge suppression chip U12's signal B output terminal B2 is connected to the first terminal of resistor R184 and the first terminal of the CAN bus interface; The ground terminal PE1 of the signal surge suppression chip U12 is connected to the ground terminal PE2 of the signal surge suppression chip U12, the second terminal of resistor R183, the second terminal of capacitor C90, and grounded. The signal surge suppression chip U12 connects the second terminal of the signal A output terminal A2 to the second terminal of the resistor R184 and the second terminal of the CAN bus interface.

8. The multi-path controlled DC power supply display system according to claim 1, characterized in that, The power module includes one of the 1 to 8 or any combination of voltage regulator units; The first regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R38, the first terminal of the capacitor C45, the first terminal of the capacitor C46, ​​the power input terminal VIN1 of the regulator U4, and the power input terminal VIN2 of the regulator U4. The second terminal of capacitor C45 is grounded, and the second terminal of capacitor C46 is grounded. The second terminal of resistor R38 is connected to the first terminal of capacitor C47 and the enable terminal EN of voltage regulator U4; The power status indicator terminal PG of voltage regulator U4 is connected to the first terminal of resistor R53, and the second terminal of resistor R53 is connected to the second terminal of resistor R41. The second terminal of capacitor C47 is grounded; The power output terminal VOUT1 of voltage regulator U4 is connected to the power output terminal VOUT2 of voltage regulator U4, the first terminal of capacitor C48, the first terminal of capacitor C49 and the first terminal of capacitor C50, and outputs a 0.9V power supply VDD_0V9. The second terminal of capacitor C48 is grounded, the second terminal of capacitor C49 is grounded, and the second terminal of capacitor C50 is grounded. The output voltage fine-tuning terminal VOS of voltage regulator U4 is connected to the first terminal of resistor R39; The second end of resistor R39 is connected to the feedback terminals FB1 and FB2 of voltage regulator U4 and the first end of resistor R40; The second end of resistor R40 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U4 and then grounded. The second regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R54, the first terminal of the capacitor C66, the first terminal of the capacitor C67, the power input terminal VIN1 of the regulator U8, and the power input terminal VIN2 of the regulator U8. The second terminal of capacitor C66 is grounded, and the second terminal of capacitor C67 is grounded. The second terminal of resistor R54 is connected to the first terminal of capacitor C68 and the enable terminal EN of voltage regulator U8. The second terminal of capacitor C68 is grounded; The power output terminal VOUT1 of voltage regulator U8 is connected to the power output terminal VOUT2 of voltage regulator U8, the first terminal of capacitor C69, the first terminal of capacitor C70, and the first terminal of capacitor C71, and outputs a 3.3V power supply VCC_3V3. The second terminal of capacitor C69 is grounded, the second terminal of capacitor C70 is grounded, and the second terminal of capacitor C71 is grounded. The output voltage fine-tuning terminal VOS of voltage regulator U8 is connected to the first terminal of resistor R55. The second end of resistor R55 is connected to the feedback terminals FB1 and FB2 of voltage regulator U8 and the first end of resistor R58. The second end of resistor R58 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U8 and then grounded. The third regulated power supply unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R44, the first terminal of the capacitor C57, the first terminal of the capacitor C58, the power input terminal VIN1 of the regulator U6, and the power input terminal VIN2 of the regulator U6. The second terminal of capacitor C57 is grounded, and the second terminal of capacitor C58 is grounded. The second terminal of resistor R44 is connected to the first terminal of capacitor C59 and the enable terminal EN of voltage regulator U6, and the second terminal of capacitor C59 is grounded. The power status indicator terminal PG of voltage regulator U6 is connected to the first terminal of resistor R56, and the second terminal of resistor R56 is connected to the second terminal of resistor R41. The power output terminal VOUT1 of voltage regulator U6 is connected to the power output terminal VOUT2 of voltage regulator U6, the first terminal of capacitor C60, the first terminal of capacitor C61, the first terminal of capacitor C62, and outputs the CPU power supply VDD_CPU. The second terminal of capacitor C60 is grounded, the second terminal of capacitor C61 is grounded, and the second terminal of capacitor C62 is grounded. The voltage regulator U6 output voltage fine-tuning terminal VOS is connected to the first terminal of resistor R45. The second terminal of resistor R45 is connected to the first terminal of resistor R46, the feedback terminal FB1 of voltage regulator U6, the feedback terminal FB2 of voltage regulator U6, and the first terminal of resistor R51. The second end of resistor R46 is connected to the grounding terminals GND2 and GND1 of voltage regulator U6 and then grounded. The second terminal of resistor R51 is connected to the first terminal of capacitor C65, the first terminal of resistor R52, and the first terminal of resistor R50. The second terminal of capacitor C65 is grounded, and the second terminal of resistor R52 is grounded. The second end of resistor R50 is connected to the first end of resistor R48 and the PWM signal output terminal of coprocessor U1A. The second end of resistor R48 is connected to the 3.3V power supply VCC_3V3. The fourth voltage regulator unit includes: the first terminal of the 5V power supply VCC5V0_SYS connected to the first terminal of the resistor R41, the first terminal of the capacitor C51, the first terminal of the capacitor C52, the power input terminal VIN1 of the voltage regulator U5, and the power input terminal VIN2 of the voltage regulator U5. The second terminal of capacitor C51 is grounded, and the second terminal of capacitor C52 is grounded. The second terminal of resistor R41 is connected to the first terminal of capacitor C53 and the enable terminal EN of voltage regulator U5; The second terminal of capacitor C53 is grounded; The power status indicator terminal PG of voltage regulator U5 is connected to the first terminal of resistor R57, and the second terminal of resistor R57 is connected to the second terminal of resistor R54. The power output terminal VOUT1 of voltage regulator U5 is connected to the power output terminal VOUT2 of voltage regulator U5, the first terminal of capacitor C54, the first terminal of capacitor C55, and the first terminal of capacitor C56, and outputs DDR power VCC_DDR. The second terminal of capacitor C54 is grounded, the second terminal of capacitor C55 is grounded, and the second terminal of capacitor C56 is grounded. The output voltage fine-tuning terminal VOS of voltage regulator U5 is connected to the first terminal of resistor R42; The second end of resistor R42 is connected to the feedback terminals FB1 and FB2 of voltage regulator U5 and the first end of resistor R43; The second end of resistor R43 is connected to the grounding terminal GND2 and grounding terminal GND1 of voltage regulator U5 and then grounded. The fifth voltage regulator unit includes: a 3.3V power supply VCC_3V3 connected to the first terminal of capacitor C63 and the power input terminal VIN of voltage regulator U7, and the second terminal of capacitor C63 grounded; The voltage regulator U7's voltage adjustment terminal GND / ADJ is connected to the first terminal of resistor R49 and the first terminal of resistor R47; The second terminal of resistor R49 is grounded, and the second terminal of resistor R47 is connected to the first terminal of capacitor C64, the power output terminal VOUT_2 of voltage regulator U7, and the power output terminal VOUT_1 of voltage regulator U7, and outputs a 1.8V power supply VCC_1V8. The second terminal of capacitor C64 is grounded; The sixth power conversion unit includes: the power input terminal VIN of the DC-DC converter chip U61 is connected to the first end of resistor R16, the first end of capacitor C69, and a 25V power supply; The control terminal CTRL of the DC-DC converter chip U61 is connected to the second terminal of resistor R16. The ground terminal GND of DC-DC converter chip U61 is connected to the second terminal of capacitor C69 and grounded. The positive voltage output terminal VO+ of the DC-DC converter chip U61 is connected to the first terminal of capacitor C21 and the first terminal of capacitor C72, and outputs a 12V power supply VCC12V. The first terminal of the TRIM trimmer of the DC-DC converter chip U61 is connected to the first terminal of the resistor R18. The negative voltage output terminal VO of DC-DC converter chip U61 is connected to the second terminal of resistor R18, the second terminal of capacitor C21 and the second terminal of capacitor C72, and then grounded. The 7th voltage regulator unit includes: the voltage regulator chip U13, the power input terminal VIN is connected to the first terminal of resistor R17, the first terminal of capacitor C83, the first terminal of capacitor C5, the first terminal of capacitor C4, and the 12V power supply VCC12V. The enable pin EN of the voltage regulator chip U13 is connected to the second terminal of resistor R17; The voltage output terminal VOUT of the voltage regulator chip U13 is connected to the first terminal of capacitor C6, the first terminal of capacitor C7, and the first terminal of capacitor C86, and outputs a 3.3V power supply P3V3. The voltage adjustment terminal VOS of the voltage regulator chip U13 is connected to the first terminal of resistor R19; The feedback terminal of the voltage regulator chip U13 is connected to the second terminal of resistor R19 and the first terminal of resistor R3; The ground terminal GND of the voltage regulator chip U13 is connected to the second terminals of capacitors C83, C5, C4, R3, C6, C7, and C86, and then grounded. The 8th power conversion unit includes: the voltage input terminal of the adjustable voltage regulator D2 is connected to the first terminal of capacitor C73 and the power supply VCC_15V_IN; The second terminal of capacitor C73 is grounded; The voltage output terminal VOUT of the adjustable voltage regulator D2 is connected to the first terminal of resistor R171 and the voltage output terminal TAB / VOUT of the adjustable voltage regulator D2. The adjustable voltage regulator D2 adjustment terminal ADJ is connected to the first terminal of resistor R172 and the first terminal of resistor R173; The second terminal of resistor R171 is connected to the second terminal of resistor R172 and the first terminal of capacitor C74, and outputs a 14V power supply VCC_14V_DIS. The second terminal of resistor R173 is grounded, and the second terminal of capacitor C74 is grounded.

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