A high-precision digital pulse signal delay system based on FPGA carry chain

Abstract

The utility model discloses a kind of high-precision digital pulse signal delay system based on FPGA carry chain, system is set in single-chip FPGA, including coarse delay counting module, TDC time measurement module and digital pulse output channel module;A calibration module is set between digital pulse output channel module and TDC time measurement module to carry out signal transmission, TDC time measurement module is externally connected with a multi-channel signal selector, further including the clock module of providing working clock and calibration clock;The scheme uses single-chip FPGA chip, circuit is simple, degree of integration is high, cost and power consumption are low, convenient for expansion;Performance index is greatly improved: 20ps jitter is realized, 4ps resolution digital pulse signal output.

Description

Technical Field

[0001] This utility model relates to the field of digital pulse signal delay generator technology, and in particular to a high-precision digital pulse signal delay system based on FPGA carry chain. Background Technology

[0002] In existing technical solutions, FPGA-based digital delay synchronizers require external high-precision delay control circuits. These circuits have low integration, complex delay circuitry, and high cost and power consumption. Furthermore, their external trigger jitter and delay accuracy are both relatively large (100ps). Moreover, current products are inherently complex in their circuit design, with many solutions requiring external high-precision delay chips and control circuits, resulting in significant external trigger jitter and delay adjustment accuracy. Therefore, the main drawbacks of current digital delay technology lie in the following aspects: 1. The circuit is complex and generally requires an external high-precision delay circuit, resulting in low integration, high cost, and high power consumption; 2. The digital pulse signal output exhibits significant jitter; 3. The accuracy of digital pulse delay adjustment is low. Utility Model Content

[0003] To address the aforementioned technical problems, this utility model provides a high-precision digital pulse signal delay system based on FPGA carry chain, which simplifies the digital delay circuit while ensuring the normal operation of time measurement and delay control functions.

[0004] This utility model is achieved using the following technical solution: A high-precision digital pulse signal delay system based on FPGA carry chain is installed within a single FPGA chip, including a coarse delay counting module, a TDC time measurement module, and a digital pulse output channel module; a calibration module is set between the digital pulse output channel module and the TDC time measurement module for signal transmission, and a multiplexer is externally connected to the TDC time measurement module.

[0005] Specifically, it also includes a clock module that provides a working clock and a calibration clock, the clock module being connected to the coarse delay counting module, the TDC time measurement module and the calibration module, respectively.

[0006] Specifically, the digital pulse output channel module is provided with multiple digital pulse output channels, and the input end of the digital pulse output channel is connected to the coarse delay counting module.

[0007] Specifically, the digital pulse output channel has built-in delay chains that process the leading edge and trailing edge of the pulse signal respectively, and the delay chains are constructed by interpolation of the carry chain within the FPGA.

[0008] Specifically, the carry chain within the FPGA includes one or more carry chains.

[0009] Specifically, the multiplexer includes an interface for inputting an external trigger pulse and multiple input signal interfaces.

[0010] The beneficial effects of this utility model are as follows: This utility model uses only one FPGA, without the need for an external high-precision delay circuit, resulting in a simple circuit, high integration, low cost and low power consumption; by using the FPGA's internal carry chain and constructing a TDC and a high-precision, high-resolution delay chain through multi-chain interpolation, the measurement, delay compensation, and adjustment accuracy are greatly improved, thereby achieving a digital pulse signal output with 20ps jitter and 4ps resolution; it simplifies circuit design, improves integration, facilitates expansion, and reduces cost and power consumption; at the same time, it improves jitter performance and delay compensation adjustment accuracy. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0012] Figure 1 This is a diagram of the high-precision digital pulse signal delay system architecture based on FPGA carry chain in this embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the calculation of system pulse parameters in an embodiment of this utility model. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0014] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0015] The following is in conjunction with the appendix Figure 1-2 The following describes some embodiments of the present invention in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0016] This invention proposes a high-precision digital pulse signal delay system based on FPGA carry chain, such as... Figure 1 As shown, the system, housed within a single FPGA, includes a coarse delay counting module, a TDC time measurement module, and a digital pulse output channel module. A calibration module is connected between the digital pulse output channel module and the TDC time measurement module for signal transmission. The TDC time measurement module is externally connected to a multiplexer. The system also includes a clock module providing the operating clock and calibration clock, which are connected to the coarse delay counting module, the TDC time measurement module, and the calibration module, respectively. The digital pulse output channel module contains multiple digital pulse output channels, with their inputs connected to the coarse delay counting module. Each digital pulse output channel has a built-in delay chain that processes the leading and trailing edges of the pulse signal, constructed by interpolating the carry chains within the FPGA. The FPGA carries chains may consist of one or more chains. The multiplexer includes an interface for inputting an external trigger pulse and multiple input signal interfaces.

[0017] The following detailed description, with reference to specific embodiments, illustrates the entire operation process of the digital pulse signal in the high-precision digital pulse signal delay system based on FPGA carry chain proposed in this invention: I. Calibration In this embodiment, the calibration of the high-precision digital pulse signal delay system based on the FPGA carry chain includes two parts.

[0018] First, the first part is the calibration of the TDC time measurement module. The calibration method can be the code density method commonly used by those skilled in the art.

[0019] Secondly, the second part involves calibrating the delay chain constructed by the carry chain within the FPGA in the digital pulse output channel, based on the calibration performed by the TDC time measurement module. In this embodiment, because the delay of the carry chain within the FPGA is not constant, and the delay of each stage of the carry chain is not the same, to solve this problem, the system uses a calibration module to generate a calibration signal and sends it into the constructed delay chain, and sends the signal output by the delay chain into the TDC time measurement module; this allows the delay of each output tap of the delay chain to be measured. To obtain the delay of each tap more accurately, multiple measurements can be taken and the average taken; finally, the delays of each output tap are arranged from smallest to largest to obtain a high-precision delay chain.

[0020] In this embodiment, if a more precise delay chain is required, multiple carry delay chains can be constructed and interpolated to obtain a single delay chain. (When constructing the delay chain, it must be ensured that the total delay of the constructed delay chain is at least greater than one clock cycle of the FPGA operating clock).

[0021] Thus, a high-precision controlled delay chain is obtained, which provides high precision and high resolution for the subsequent output digital pulse signal.

[0022] II. Calculation of Pulse Parameters The user inputs the desired digital pulse signal's delay (Td) and pulse width (Tw). Tc represents the FPGA's operating clock cycle, T0 is the moment the TDC time measurement module detects the "input external trigger pulse signal," and Te is the phase difference (time difference) between the "input external trigger pulse signal" and the "FPGA operating clock" measured by the TDC time measurement module. Figure 2 As shown.

[0023] Based on the parameters above, the required coarse delay count (Nr) and delay chain delay time (Tcr) for the leading edge of the output pulse and the coarse delay count (Nf) and delay chain delay time (Tcf) for the trailing edge can be calculated within the FPGA, and the coarse delay counting module and delay chain can be configured. Nr = (Td + Te - Tc) / Tc rounded down; Tcr = Td – (Nr+1) * Tc + Te; Nf = (Td + Tw + Te - Tc) / Tc rounded down; Tcf = Td + Tw – (Nf + 1) * Tc + Te.

[0024] Nr and Nf are the FPGA operating clock counts in the coarse delay counting module, while Tcr and Tcf are the delay times that need to be delayed by the constructed delay chain (this delay time is less than Tc and has a very small resolution; based on the current AMD K7 Ultrascale Plus series FPGA's carry8 using multi-chain interpolation (average), a single tap delay can be around 4ps).

[0025] III. Output Pulse The digital pulse signal output after being delayed by the delay chain in the previous step is then processed by the internal logic operation of the FPGA (AND operation), and finally outputs a low-jitter, high-resolution digital pulse signal.

[0026] The high-precision digital pulse signal delay system based on FPGA carry chain proposed in this invention achieves the following improvements and effects: (1) Using only one FPGA: Time measurement and output phase delay compensation are achieved in one FPGA. The circuit is simple, highly integrated, and has low cost and power consumption. (2) Jitter less than 20ps: By using the carry chain inside the FPGA, a TDC and a high-precision, high-resolution delay chain are constructed through multi-chain interpolation, which greatly improves the accuracy of measurement, delay compensation, and adjustment; the delay chain built inside the FPGA is calibrated, so that it is controlled, avoiding the drift caused by the environment due to the use of external high-precision delay chip circuits, which leads to inaccurate delay compensation and increased jitter. (3) High adjustment accuracy: By using the carry chain inside the FPGA, a TDC and a high-precision, high-resolution delay chain are constructed through multi-chain interpolation and calibrated, so that the adjustment accuracy reaches 4ps.

[0027] For the foregoing embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0028] The above embodiments describe the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this utility model. Modifications and variations made by those skilled in the art without departing from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A high-precision digital pulse signal delay system based on FPGA carry chain, configured within a single FPGA, characterized in that, It includes a coarse delay counting module, a TDC time measurement module, and a digital pulse output channel module; a calibration module is set between the digital pulse output channel module and the TDC time measurement module for signal transmission, and the TDC time measurement module is externally connected to a multiplexer.

2. The high-precision digital pulse signal delay system based on FPGA carry chain as described in claim 1, characterized in that, It also includes a clock module that provides a working clock and a calibration clock, the clock module being connected to the coarse delay counting module, the TDC time measurement module and the calibration module, respectively.

3. The high-precision digital pulse signal delay system based on FPGA carry chain as described in claim 1, characterized in that, The digital pulse output channel module is equipped with multiple digital pulse output channels, and the input terminals of the digital pulse output channels are connected to the coarse delay counting module.

4. The high-precision digital pulse signal delay system based on FPGA carry chain as described in claim 3, characterized in that, The digital pulse output channel has built-in delay chains that process the leading edge and trailing edge of the pulse signal respectively. The delay chains are constructed by interpolation of the carry chain within the FPGA.

5. A high-precision digital pulse signal delay system based on FPGA carry chain as described in claim 4, characterized in that, The carry chain within the FPGA may include one or more.

6. A high-precision digital pulse signal delay system based on FPGA carry chain as described in claim 1, characterized in that, The multiplexer includes an interface for inputting an external trigger pulse and multiple input signal interfaces.

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