Gate driving chip and driving mode control circuit thereof

Abstract

Embodiments of the present disclosure provide a gate drive chip and a drive mode control circuit thereof, which comprises a voltage stabilizer, a clamping circuit and a dead time configuration circuit, the input end of the clamping circuit is connected with the dead time configuration port, the output end of the clamping circuit is connected with the input end of the dead time configuration circuit, the voltage stabilizer generates an analog voltage based on a power supply voltage and limits the analog voltage to not exceed a safe voltage to supply power to the dead time configuration circuit, the clamping circuit limits a target voltage to not exceed a safe voltage in a double-channel mode, the dead time configuration circuit determines a drive mode according to the target voltage and generates different double-drive output signals in different drive modes, and the dead time is flexibly set based on an external resistance in a programmable dead time mode, thus, different drive modes can be flexibly configured through only one port, the dead time can be flexibly configured in the programmable dead time mode to adapt to different application scenarios, and the high-voltage input can also be compatible.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more particularly to a gate driver chip and its driving mode control circuit. Background Technology

[0002] Gate drivers are typically classified into three types: single-channel, dual-channel, and half-bridge. Dual-channel drivers allow both outputs to be active simultaneously, while half-bridge drivers have overlap protection and cannot have both outputs active simultaneously. Dual-channel and half-bridge drivers are usually different types of chips; therefore, different gate driver chips need to be selected for different application scenarios. In half-bridge mode applications, dead-time protection is usually involved to prevent the upper and lower bridge arm power devices from conducting simultaneously. If the dead time is too small, there is still a risk of large current due to inter-chip differences; if the dead time is too large, it will affect the operating efficiency of the power devices. Therefore, different half-bridge drivers need to be designed for different types of power devices and their driving capabilities.

[0003] Therefore, existing gate drivers have poor flexibility and are difficult to adapt to different application scenarios. In addition, the dead-time configuration circuit in the gate driver is internally a low-voltage power supply domain, making it difficult to be compatible with high-voltage inputs. Utility Model Content

[0004] This disclosure provides a gate driver chip and its drive mode control circuit, which can flexibly configure the drive mode and dead time through a single port to adapt to different application scenarios and is compatible with high voltage input.

[0005] In a first aspect, this disclosure provides a drive mode control circuit for a gate driver chip. The gate driver chip includes a dead time configuration port. The drive mode control includes a voltage regulator, a clamping circuit, and a dead time configuration circuit. The power supply voltage is connected to the power supply terminal of the dead time configuration circuit through the voltage regulator. The input terminal of the clamping circuit is connected to the dead time configuration port. The output terminal of the clamping circuit is connected to the input terminal of the dead time configuration circuit. The control terminal of the clamping circuit is connected to the detection output terminal of the dead time configuration circuit.

[0006] The voltage regulator is configured to generate an analog voltage based on the power supply voltage, limit the analog voltage to a safe voltage, and output it.

[0007] The dead-time configuration circuit is configured to determine a drive mode based on a target voltage. The drive modes include a dual-channel mode, a half-bridge fixed dead-time mode, and a programmable dead-time mode. In the dual-channel mode, dual drive output signals that can be active simultaneously are generated. In the half-bridge fixed dead-time mode / programmable dead-time mode, dual drive output signals that cannot be active simultaneously are generated.

[0008] The clamping circuit is configured to limit the target voltage from exceeding the safe voltage in the dual-channel mode.

[0009] In the half-bridge fixed dead time mode, the dual-drive output signal has a fixed dead time, and in the programmable dead time mode, the dual-drive output signal has an adjustable dead time, wherein the adjustable dead time depends on the external resistor of the dead time configuration port.

[0010] In a second aspect, this disclosure provides a gate driver chip, including any of the drive mode control circuits provided in the first aspect.

[0011] In the technical solution of this embodiment, the drive mode control circuit includes a voltage regulator, a clamping circuit, and a dead time configuration circuit. The input terminal of the clamping circuit is connected to the dead time configuration port, and the output terminal of the clamping circuit is connected to the input terminal of the dead time configuration circuit. The voltage regulator generates an analog voltage based on the power supply voltage and limits the analog voltage to a safe voltage to supply power to the dead time configuration circuit. The clamping circuit can limit the target voltage to a safe voltage in dual-channel mode. The dead time configuration circuit determines the drive mode according to the target voltage and generates dual drive output signals that can be effective simultaneously in dual-channel mode. In half-bridge fixed dead time mode / programmable dead time mode, it generates dual drive output signals that cannot be effective simultaneously. In this way, different drive modes can be flexibly configured through only one port, and the dead time can be flexibly configured in programmable dead time mode to adapt to different application scenarios and is also compatible with high voltage input. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a drive mode control circuit provided in a disclosed embodiment.

[0014] Figure 2This is a circuit diagram of a clamping circuit provided in an embodiment of the present disclosure.

[0015] Figure 3 This is a schematic diagram of a dead-time configuration circuit provided in an embodiment of the present disclosure.

[0016] Figure 4 This is a circuit diagram of a pattern detection circuit provided in an embodiment of the present disclosure.

[0017] Figure 5 This is a circuit diagram of a control logic circuit provided in an embodiment of the present disclosure.

[0018] Figure 6 This is a circuit diagram of a first fixed dead time circuit provided in an embodiment of the present disclosure.

[0019] Figure 7 This is a schematic diagram of the signal in the half-bridge fixed dead time mode provided in an embodiment of this disclosure.

[0020] Figure 8 This is a circuit diagram of a second fixed dead time circuit provided in an embodiment of the present disclosure.

[0021] Figure 9 This is a circuit diagram of an adjustable dead-time circuit provided in an embodiment of the present disclosure.

[0022] Figure 10 This is a schematic diagram of a signal in a programmable dead-time mode provided in an embodiment of this disclosure.

[0023] Figure 11 This is a circuit diagram of an output logic circuit provided in an embodiment of the present disclosure.

[0024] Figure 12 This is a schematic diagram of the signal in dual-channel mode provided in an embodiment of this disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0027] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0028] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0029] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0030] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0032] The gate driver chip disclosed herein includes a package, a dead-time configuration pin, and a gate driver die. The dead-time configuration pin is fixed outside the package, and the gate driver die is fixed inside the package. The dead-time configuration pin can be connected to external devices externally and to the gate driver die internally. The gate driver die includes a dead-time configuration port and integrates a drive mode control circuit. The dead-time configuration pin is connected to the drive mode control circuit through the dead-time configuration port.

[0033] The dead-time configuration pin has three connection relationships with external devices: connected to power, floating, and connected to a resistor to ground. Therefore, the connection state of the dead-time configuration port can be any one of these three: connected to power, floating, or connected to a resistor. The gate driver chip's driving modes include dual-channel mode, half-bridge fixed dead-time mode, and programmable dead-time mode. The connection state of the dead-time configuration port corresponds one-to-one with the gate driver chip's driving mode.

[0034] Specifically, when the connection status is connected to power, the drive mode is dual-channel mode; when the connection status is floating, the drive mode is half-bridge fixed dead time mode; and when the connection status is connected to ground via a resistor, the drive mode is programmable dead time mode.

[0035] In the half-bridge fixed dead time mode, the dual drive output signals generated by the drive mode control circuit cannot be effective at the same time and have a fixed dead time. That is, when the first drive output signal is high, the second drive output signal is low, and when the second drive output signal is high, the first drive output signal is low. The first drive output signal and the second drive output signal have a fixed dead time.

[0036] In programmable dead-time mode, the dual drive output signals generated by the drive mode control circuit cannot be valid simultaneously and have an adjustable dead time. This adjustable dead time depends on the external resistor connected to the dead-time configuration port. Specifically, when the first drive output signal is high, the second drive output signal is low, and when the second drive output signal is high, the first drive output signal is low. Both the first and second drive output signals have adjustable dead times. The adjustable dead time depends on the external resistor connected to the dead-time configuration port.

[0037] In dual-channel mode, the dual drive output signals generated by the drive mode control circuit can be effective simultaneously. That is, when the first drive output signal is high, the second drive output signal can be either high or low, and when the second drive output signal is high, the first drive output signal can be either high or low.

[0038] Thus, the drive mode control circuit provided in this disclosure can generate different dual drive output signals in different drive modes through a single port to flexibly configure the drive mode. It can also flexibly configure the dead time based on an external resistor in the programmable dead time mode to adapt to different application scenarios.

[0039] Because the internal power supply domain of the drive mode control circuit is low-voltage in dual-channel mode, the power supply voltage connected to the dead time configuration port cannot be higher than the internal power supply voltage of the drive mode control circuit, making it difficult for the drive mode control circuit to be compatible with high-voltage input.

[0040] To address the aforementioned issues, the drive mode control circuit provided in this disclosure includes a voltage regulator and a clamping circuit. The voltage regulator generates an analog voltage based on the power supply voltage and limits the analog voltage to a safe voltage to power the dead time configuration circuit. The clamping circuit can limit the target voltage to a safe voltage in dual-channel mode, thereby enabling the drive mode control circuit to be compatible with high-voltage input.

[0041] The drive mode control circuit provided in this disclosure will be described in detail below with reference to several specific embodiments.

[0042] Figure 1 This is a schematic diagram of the structure of a drive mode control circuit provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the drive mode control circuit 100 includes a voltage regulator 110, a clamping circuit 120, and a dead time configuration circuit 130.

[0043] The power supply voltage VDD is connected to the power supply terminal of the dead time configuration circuit 130 through the voltage regulator 110. The input terminal of the clamping circuit 120 is connected to the dead time configuration port DT. The output terminal of the clamping circuit 120 is connected to the input terminal of the dead time configuration circuit 130. The control terminal of the clamping circuit 120 is connected to the detection output terminal of the dead time configuration circuit 130.

[0044] The regulator 110 is configured to generate an analog voltage AVDD based on the power supply voltage VDD, limit the analog voltage AVDD to not exceed the safe voltage Vsafe, and then output it.

[0045] The dead-time configuration circuit 130 is configured to determine the drive mode based on the target voltage V1, and in dual-channel mode, generate dual drive output signals (OUTA and OUTB) that can be effective simultaneously, and in half-bridge fixed dead-time mode / programmable dead-time mode, generate dual drive output signals (OUTA and OUTB) that cannot be effective simultaneously.

[0046] The clamping circuit 120 is configured to limit the target voltage V1 to no more than the safe voltage Vsafe in dual-channel mode.

[0047] For example, the safety voltage Vsafe is the upper limit of the supply voltage for which the dead-time configuration circuit 130 can operate normally; for example, the safety voltage Vsafe could be 5V. The supply voltage VDD is a wide-range supply voltage; for example, the supply voltage VDD could be any voltage between 3V and 20V. The regulator 110 could be a regulator with high-voltage buck functionality, such as a low-dropout regulator (LDO).

[0048] When the power supply voltage VDD is greater than the safe voltage Vsafe, the regulator 110 can step down the power supply voltage VDD to the safe voltage Vsafe, then the analog voltage AVDD = Vsafe, and provide the analog voltage AVDD to the dead time configuration circuit 130 to power the dead time configuration circuit 130.

[0049] When the power supply voltage VDD is less than or equal to the safe voltage Vsafe, the analog voltage AVDD follows the power supply voltage VDD, that is, AVDD = VDD. The regulator 110 provides the analog voltage AVDD to the dead time configuration circuit 130, thus powering the dead time configuration circuit 130.

[0050] Figure 2 This is a circuit diagram of a clamping circuit provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the clamping circuit 110 includes a clamping transistor Dz and a current limiting circuit 111. The input of the current limiting circuit 111 is connected to the dead time configuration port DT, the output of the current limiting circuit 111 is connected to the first terminal of the clamping transistor Dz and the input of the dead time configuration circuit 130, the second terminal of the clamping transistor Dz is grounded, and the control terminal of the current limiting circuit 111 is connected to the detection output of the dead time configuration circuit 130.

[0051] For example, the current limiting circuit 111 includes a current limiting resistor R_limit and a current limiting control switch M_limit. The current limiting resistor R_limit and the current limiting control switch M_limit are connected in parallel between the first end of the clamping transistor Dz and the dead time configuration port DT. The control terminal of the current limiting control switch M_limit is connected to the detection output terminal of the dead time configuration circuit 130.

[0052] In dual-channel mode, when the power supply voltage VDD is high, the target voltage V1 is greater than the safety voltage Vsafe. Therefore, the clamping transistor Dz is turned on, clamping the target voltage V1 to the safety voltage Vsafe before outputting it to the dead-time configuration circuit 130. When the power supply voltage VDD is low, the target voltage V1 is less than or equal to the safety voltage Vsafe. Therefore, the clamping transistor Dz is turned off, and the target voltage V1 is directly output to the dead-time configuration circuit 130.

[0053] In dual-channel mode, the current limiting control switch M_limit is off, and the current limiting resistor R_limit can limit the current flowing through the clamping transistor Dz when it is on. In programmable dead-time mode, the clamping transistor Dz is off, the current limiting control switch M_limit is on, the current limiting resistor R_limit is short-circuited, and the dead-time configuration port DT has only the path of the external resistor to ground.

[0054] Thus, in dual-channel mode, the current limiting circuit 111 can limit the current flowing through the clamping transistor Dz. In programmable dead-time mode, the current limiting circuit 111 can limit the dead-time configuration port DT to ground only through an external resistor. The clamping transistor Dz can output the safe voltage Vsafe when the target voltage V1 is greater than the safe voltage Vsafe, and output the target voltage V1 when the target voltage V1 is less than or equal to the safe voltage Vsafe.

[0055] For example, Figure 3 This is a schematic diagram of a dead-time configuration circuit provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the dead time configuration circuit 130 includes a mode detection circuit 131, a first fixed dead time circuit 132, a second fixed dead time circuit 133, an adjustable dead time circuit 134, a control logic circuit 135, and an output logic circuit 136.

[0056] The first input terminal of the pattern detection circuit 131 and the input terminal of the adjustable dead time circuit 134 are connected to the reference voltage VREF. The second input terminal of the pattern detection circuit 131 is connected to the output terminal of the clamping circuit to receive the target voltage V1. The first output terminal of the pattern detection circuit 131 is connected to the first input terminal of the control logic circuit 135 to output the first pattern detection signal ADJ1. The second output terminal of the pattern detection circuit 131 is connected to the second input terminal of the control logic circuit 135 and the first input terminal of the output logic circuit 136 to output the second pattern detection signal ADJ2. The third output terminal of the pattern detection circuit 131 is connected to the first control terminal of the adjustable dead time circuit 134 to output the voltage V3.

[0057] The first output terminal of the control logic circuit 135 is connected to the input terminal of the first fixed dead time circuit 132 and the second input terminal of the output logic circuit 136 to output the first dead time input signal INA_SDT. The second output terminal of the control logic circuit 135 is connected to the input terminal of the second fixed dead time circuit 133 and the third input terminal of the output logic circuit 136 to output the second dead time input signal INB_SDT. The third output terminal of the control logic circuit 135 is connected to the second control terminal of the adjustable dead time circuit 134 to output the first control signal CTR1. The fourth output terminal of the control logic circuit 135 is connected to the third control terminal of the adjustable dead time circuit 134 to output the second control signal CTR2.

[0058] The first output terminal of the adjustable dead time circuit 134 is connected to the fourth input terminal of the output logic circuit 136 to output a first adjustable dead time signal RDTA. The second output terminal of the adjustable dead time circuit 134 is connected to the fifth input terminal of the output logic circuit 136 to output a second adjustable dead time signal RDTB. The output terminal of the first fixed dead time circuit 132 is connected to the sixth input terminal of the output logic circuit 136 to output a first fixed dead time signal OUTA_SDT. The output terminal of the second fixed dead time circuit 133 is connected to the seventh input terminal of the output logic circuit 136 to output a second fixed dead time signal OUTB_SDT.

[0059] For example, Figure 4 A circuit diagram of a pattern detection circuit provided in an embodiment of this disclosure is shown below. Figure 4 As shown, the pattern detection circuit 131 includes an operational amplifier OPA, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a first comparator CMP1, a pull-down resistor R_down, a first hysteresis inverter INV_S1, a second hysteresis inverter INV_S2, a third hysteresis inverter INV_S3, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first NOR gate NOR1.

[0060] The first transistor M1 is connected between the output of the voltage regulator and the non-inverting input of the operational amplifier OPA. The second transistor M2 and the pull-down resistor R_down are connected in series between the output of the voltage regulator and ground. The first branch, formed by the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 connected in series, is connected between the output of the voltage regulator and ground. The second branch, formed by the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 connected in series, is connected between the output of the voltage regulator and ground. The eleventh transistor M11 is connected between the output of the voltage regulator and the output of the first comparator CMP1.

[0061] The non-inverting input of the operational amplifier OPA is connected to the connection point of the fourth transistor M4 and the fifth transistor M5, the output of the clamping circuit, and the inverting input of the first comparator CMP1. The inverting input of the operational amplifier OPA is connected to the reference voltage VREF. The output of the operational amplifier OPA is connected to the control terminals of the first transistor M1, the second transistor M2, and the first control terminal of the adjustable dead-time circuit. The connection point of the second transistor M2 and the pull-down resistor R_down is connected to the input terminals of the first hysteresis inverter INV_S1 and the second hysteresis inverter INV_S2. The output terminal of the first hysteresis inverter INV_S1 is connected to the first input terminal of the control logic circuit and the control terminal of the clamping circuit 120 through the first inverter INV1. The output terminal of the second hysteresis inverter INV_S2 is connected to the first input terminal of the first NOR gate NOR1 through the second inverter INV2.

[0062] The non-inverting input of the first comparator CMP1 is connected to the connection point of the eighth transistor M8 and the ninth transistor M9. The output of the first comparator CMP1 is connected to the input of the third hysteresis inverter INV_S3. The output of the third hysteresis inverter INV_S3 is connected to the second input of the first NOR gate NOR1 through the third inverter INV3. The output of the first NOR gate NOR1 is connected to the second input of the control logic circuit and the first input of the output logic circuit.

[0063] The fourth transistor M4 and the eighth transistor M8 are diodes. The third transistor M3, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 are controlled by the first mode detection signal ADJ1. The eleventh transistor M11 is controlled by the inverted signal of the first mode detection signal.

[0064] In dual-channel mode, when the power supply voltage VDD is high, the non-inverting input voltage of the operational amplifier OPA is the target voltage V1 = Vsafe, and the inverting input voltage of the operational amplifier OPA is the reference voltage VREF. The reference voltage VREF is generally 1.2V. Therefore, the non-inverting input voltage of the operational amplifier OPA is greater than the inverting input voltage, so the output voltage V3 of the operational amplifier OPA is high.

[0065] When the power supply voltage VDD is low, the non-inverting input voltage of the operational amplifier OPA is the target voltage V1 = VDD - I. M6 *R', where I M6 R' is the current flowing through the sixth transistor M6, and R' is the resistance value of the current-limiting resistor R_limit. The sixth transistor M6 and the tenth transistor M10 are controlled by the bias voltage VBN. The current I can be controlled by adjusting the bias voltage VBN. M6If the target voltage V1 is set to a small value, making it close to the power supply voltage VDD, then the non-inverting input voltage of the operational amplifier OPA will still be greater than the inverting input voltage, and the output voltage V3 of the operational amplifier OPA will still be high.

[0066] Under the action of voltage V3, the first transistor M1 and the second transistor M2 are turned off. The voltage OUT1 at the connection point of the second transistor M2 and the pull-down resistor R_down is pulled low, so the first mode detection signal ADJ1 is at the first level, i.e., low level. The third transistor M3, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 are turned on under the action of the first mode detection signal ADJ1, i.e., the first branch and the second branch are turned on. The eleventh transistor M11 is the inverted signal of the first mode detection signal. It is shut off under the action of [something].

[0067] At this time, the target voltage V1 = VDD - I M6 *R', the voltage V2 at the connection point between the eighth transistor M8 and the ninth transistor M9 is VDD - VDS_M7 - VGS_M8, where VDS_M7 is the drain-source voltage of the seventh transistor, and VGS_M8 is the gate-source voltage of the eighth transistor M8. Because I M6 Since the voltage is smaller and AVDD≤VDD, V1>V2. Therefore, the non-inverting input voltage of the first comparator CMP1 is less than the inverting input voltage, and the output voltage OUT2 of the first comparator CMP1 is low. Thus, the second mode detection signal ADJ2 is at the second level, i.e., high level.

[0068] In the half-bridge fixed dead-time mode, since the dead-time configuration port DT is floating, the target voltage V1 is pulled up to be greater than the reference voltage VREF. The output voltage V3 of the operational amplifier OPA is high, the first transistor M1 and the second transistor M2 are turned off, and the voltage OUT1 is pulled low. Therefore, the first mode detection signal ADJ1 is at the first level, i.e., low level, the first branch and the second branch are turned on, and the eleventh transistor M11 is turned off. At this time, the target voltage V1 = AVDD - VDS_M3 - VGS_M4, where VDS_M3 is the drain-source voltage of the third transistor M3, VGS_M4 is the gate-source voltage of the fourth transistor M4, and the voltage V2 = AVDD - VDS_M7 - VGS_M8.

[0069] By setting the sizes of the fourth transistor M4 and the eighth transistor M8 to be different and / or setting the number of sixth transistors M6 to be greater than the number of tenth transistors M10, the current flowing through the first branch is made greater than the current flowing through the second branch, wherein the current flowing through the first branch is I. M6 The current flowing through the second branch is the same as the current I flowing through the tenth transistor M10. M10, thereby making V1 < V2. Therefore, the non-inverting input voltage of the first comparator CMP1 is greater than the inverting input voltage, and the output voltage OUT2 of the first comparator CMP1 is high, so the second mode detection signal ADJ2 is at the first level, that is, low level.

[0070] In the programmable dead time mode, V1 = VREF, the output voltage V3 of the operational amplifier OPA is low, the first transistor M2 and the second transistor M2 are turned on, and the voltage OUT1 is pulled up, so the first mode detection signal ADJ1 is at the second level, that is, high level. At this time, the third transistor M3, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 are turned off, that is, the first branch and the second branch are turned off, the eleventh transistor M11 is turned on, and the output voltage OUT2 is pulled up, so the second mode detection signal ADJ2 is at the first level, that is, low level.

[0071] It should be noted that the first hysteresis inverter INV_S1, the second hysteresis inverter INV_S2, the third hysteresis inverter INV_S3, the first inverter INV1, the second inverter INV2, the third inverter INV3, and the first NOR gate NOR1 constitute the detection logic circuit in the mode detection circuit 131, and Figure 4 only the structure of the detection logic circuit is shown exemplarily.

[0072] In practical applications, it can be replaced Figure 4 at least some of the logic gates in the shown detection logic circuit or add logic gates to the detection logic circuit, so that the detection logic circuit can still pull down the first mode detection signal ADJ1 and pull up the second mode detection signal ADJ2 when the voltage OUT1 and the voltage OUT2 are low, pull down the first mode detection signal ADJ1 and the second mode detection signal ADJ2 when the voltage OUT1 is low and the voltage OUT2 is high, and pull up the first mode detection signal ADJ1 and pull down the second mode detection signal ADJ2 when the voltage OUT1 and the voltage OUT2 are high.

[0073] For example, the second hysteresis inverter INV_S2 and the second inverter INV2 in the detection logic circuit can be replaced with a Schmitt trigger, and the third hysteresis inverter INV_S3 and the third inverter INV3 can be replaced with another Schmitt trigger.

[0074] Thus, when the dead-time configuration port DT is connected to power, the mode detection circuit 131 determines that the first mode detection signal ADJ1 is at the first level and the second mode detection signal ADJ2 is at the second level, thereby determining that the driving mode is dual-channel mode. When the dead-time configuration port DT is floating, it determines that the first mode detection signal ADJ1 and the second mode detection signal ADJ2 are at the first level, thereby determining that the driving mode is half-bridge fixed dead-time mode. When the dead-time configuration port DT is connected to ground via a resistor, it determines that the first mode detection signal ADJ1 is at the second level and the second mode detection signal ADJ2 is at the first level, thereby determining that the driving mode is programmable dead-time mode.

[0075] For example, Figure 5 A circuit diagram of a control logic circuit provided in an embodiment of this disclosure is shown below. Figure 5 As shown, the control logic circuit 135 includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third NOR gate NOR3.

[0076] The first drive input signal INA is connected to the first input terminal of the first NAND gate NAND1, and the second drive input signal INB is connected to the first input terminal of the second NAND gate NAND2. The second output terminal of the mode detection circuit, i.e., the second mode detection signal ADJ2, is connected to the second input terminal of the first NAND gate NAND1 and the second input terminal of the second NAND gate NAND2 through the fourth inverter INV4. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the sixth inverter INV6, the input terminal of the first fixed dead time circuit, the first input terminal of the third NOR gate NOR3, and the second input terminal of the output logic circuit through the fifth inverter INV5. The output terminal of the second NAND gate NAND2 is connected to the input terminal of the eighth inverter INV8, the input terminal of the second fixed dead time circuit, the first input terminal of the second NOR gate NOR2, and the third input terminal of the output logic circuit through the seventh inverter INV7.

[0077] The output of the sixth inverter INV6 is connected to the second input of the second NOR gate NOR2. The output of the eighth inverter INV8 is connected to the second input of the third NOR gate NOR3. The output of the second NOR gate NOR2 is connected to the first input of the third NAND gate NAND3. The output of the third NOR gate NOR3 is connected to the first input of the fourth NAND gate NAND4. The second inputs of the third NAND gate NAND3 and the fourth NAND gate NAND4 are connected to the first output of the mode detection circuit to receive the first mode detection signal ADJ1. The output of the third NAND gate NAND3 is connected to the second control terminal of the adjustable dead time circuit to output the first control signal CTR1. The output of the fourth NAND gate NAND4 is connected to the third control terminal of the adjustable dead time circuit to output the second control signal CTR2.

[0078] In dual-channel mode, the second mode detection signal ADJ2 is high, while the first dead-time input signal INA_SDT output from the fifth inverter INV5 and the second dead-time input signal INB_SDT output from the sixth inverter INV6 are always low. At this time, the first mode detection signal ADJ1 is low, while the first control signal CTR1 output from the third NAND gate NAND3 and the second control signal CTR2 output from the fourth NAND gate NAND4 are always high.

[0079] In the half-bridge fixed dead-time mode, the second mode detection signal ADJ2 is low, the first dead-time input signal INA_SDT is in phase with the first drive input signal INA, and the second dead-time input signal INB_SDT is in phase with the second drive input signal INB. At this time, the first mode detection signal ADJ1 is low, and the first control signal CTR1 and the second control signal CTR2 are always high.

[0080] In programmable dead-time mode, the second mode detection signal ADJ2 is low, the first dead-time input signal INA_SDT is in phase with the first drive input signal INA, and the second dead-time input signal INB_SDT is in phase with the second drive input signal INB. At this time, the first mode detection signal ADJ1 is high, the first control signal CTR1 is out of phase with the first drive input signal INA, and the second control signal CTR2 is out of phase with the second drive input signal INB.

[0081] It should be noted that, Figure 5The structure of the control logic circuit 135 is shown only as an example. In practical applications, at least some of the logic gates in the control logic circuit 135 can be replaced or logic gates can be added to the control logic circuit 135 so that the control logic circuit 135 can still output dual dead-time input signals (INA_SDT and INB_SDT) that are always low and dual control signals (CTR1 and CTR2) that are always high in dual-channel mode.

[0082] In half-bridge fixed dead-time mode, the output consists of dual dead-time input signals (INA_SDT and INB_SDT) in phase with the dual drive input signals (INA and INB), and dual control signals (CTR1 and CTR2) that are always high. In programmable dead-time mode, the output consists of dual dead-time input signals (INA_SDT and INB_SDT) in phase with the dual drive input signals (INA and INB), and dual control signals (CTR1 and CTR2) that are out of phase with the dual drive input signals (INA and INB).

[0083] For example, the first NAND gate NAND1 and the fifth inverter INV5 in the control logic circuit 135 can be replaced with an AND gate, and the second NAND gate NAND2 and the seventh inverter INV7 can be replaced with another AND gate.

[0084] Thus, in the half-bridge fixed dead-time mode, the control logic circuit 135 can generate dual dead-time input signals (INA_SDT and INB_SDT) based on the dual drive input signals (INA and INB). In the programmable dead-time mode, the control logic circuit 135 can generate dual dead-time input signals (INA_SDT and INB_SDT) based on the dual drive input signals (INA and INB), and generate dual control signals (CTR1 and CTR2) based on the dual dead-time input signals (INA_SDT and INB_SDT).

[0085] For example, Figure 6 A circuit diagram of a first fixed dead-time circuit provided in an embodiment of this disclosure is shown below. Figure 6 As shown, the first fixed dead time circuit 132 includes a first pull-up transistor MH1, a first pull-down transistor ML1, a first grounding resistor R_gnd1, and a first capacitor C1.

[0086] The first pull-up transistor MH1, the first pull-down transistor ML1, and the first grounding resistor R_gnd1 are connected in series between the output terminal of the voltage regulator and ground. The control terminals of the first pull-up transistor MH1 and the first pull-down transistor ML1 are connected to the first output terminal of the control logic circuit to receive the first dead-time input signal INA_SDT. The first capacitor C1 is connected between the output terminal of the voltage regulator and the connection point of the first pull-up transistor MH1 and the first pull-down transistor ML1. The connection point of the first pull-up transistor MH1 and the first pull-down transistor ML1 is connected to the sixth input terminal of the output logic circuit to output the first fixed dead-time signal OUTA_SDT.

[0087] In dual-pass mode, the first dead time input signal INA_SDT is low, the first pull-up transistor MH1 is turned on, the first pull-down transistor ML1 is turned off, and the first fixed dead time signal OUTA_SDT is always high.

[0088] In half-bridge fixed dead-time mode / programmable dead-time mode, the first dead-time input signal INA_SDT is in phase with the first drive input signal INA. An RC circuit, consisting of the first grounding resistor R_gnd1 and the first capacitor C1, with a delay of, for example, 8ns, generates a non-overlapping fixed dead-time Tmin after the falling edge of the first dead-time input signal INA_SDT, thus obtaining the first fixed dead-time signal OUTA_SDT. Figure 7 As shown, Figure 7 This is a schematic diagram of a signal under a half-bridge fixed dead time mode provided in an embodiment of this disclosure.

[0089] The aforementioned first fixed dead time signal OUTA_SDT can be understood as the falling edge delayed and inverted signal of the first dead time input signal INA_SDT, that is, the falling edge delayed and inverted signal of the first drive input signal INA.

[0090] In practical applications, to improve driving capability, 2n inverters can be connected in series between the control terminal of the first pull-up transistor MH1 and the first output terminal of the control logic circuit, where n is an integer greater than or equal to 1, such as... Figure 6 As shown. Furthermore, 2m inverters can be connected in series between the connection point of the first pull-up transistor MH1 and the first pull-down transistor ML1 and the sixth input terminal of the output logic circuit, where m is an integer greater than or equal to 1, such as... Figure 6 As shown.

[0091] Thus, the first fixed dead time circuit 132 can generate the falling edge delayed inverted signal of the first drive input signal INA, i.e. the first fixed dead time signal OUTA_SDT, based on the received first dead time input signal INA_SDT.

[0092] For example, Figure 8 A circuit diagram of a second fixed dead-time circuit provided in an embodiment of this disclosure is shown below. Figure 8 As shown, the second fixed dead time circuit 133 includes a second pull-up transistor MH2, a second pull-down transistor ML2, a second grounding resistor R_gnd2, and a second capacitor C2.

[0093] The second pull-up transistor MH2, the second pull-down transistor ML2, and the second grounding resistor R_gnd2 are connected in series between the output terminal of the voltage regulator and ground. The control terminals of the second pull-up transistor MH2 and the second pull-down transistor ML2 are connected to the second output terminal of the control logic circuit to receive the second dead-time input signal INB_SDT. The second capacitor C2 is connected between the output terminal of the voltage regulator and the connection point of the second pull-up transistor MH2 and the second pull-down transistor ML2. The connection point of the second pull-up transistor MH2 and the second pull-down transistor ML2 is connected to the seventh input terminal of the output logic circuit to output the second fixed dead-time signal OUTB_SDT.

[0094] In dual-pass mode, the second dead time input signal INB_SDT is low, the second pull-up transistor MH2 is turned on, the second pull-down transistor ML2 is turned off, and the second fixed dead time signal OUTB_SDT is always high.

[0095] In half-bridge fixed dead-time mode / programmable dead-time mode, the second dead-time input signal INB_SDT is in phase with the second drive input signal INB. An RC circuit, consisting of the second grounding resistor R_gnd2 and the second capacitor C2, with a delay of, for example, 8ns, generates a non-overlapping fixed dead-time Tmin on the falling edge of the second dead-time input signal INB_SDT to obtain the second fixed dead-time signal OUTB_SDT. Figure 7 As shown. The second fixed dead time signal OUTB_SDT can be understood as the falling edge delayed and inverted signal of the second dead time input signal INB_SDT, i.e., the falling edge delayed and inverted signal of the second drive input signal INB.

[0096] In practical applications, to improve driving capability, 2i inverters can be connected in series between the control terminal of the second pull-up transistor MH2 and the second output terminal of the control logic circuit, where i is an integer greater than or equal to 1, such as... Figure 8 As shown. Furthermore, 2j inverters can be connected in series between the connection point of the second pull-up transistor MH2 and the second pull-down transistor ML2 and the seventh input terminal of the output logic circuit, where j is an integer greater than or equal to 1, such as... Figure 8 As shown.

[0097] Thus, the second fixed dead time circuit 133 can generate the falling edge delayed inverted signal of the second drive input signal INB, i.e. the second fixed dead time signal OUTB_SDT, based on the received second dead time input signal INB_SDT.

[0098] For example, Figure 9 A circuit diagram of an adjustable dead-time circuit provided in an embodiment of this disclosure is shown below. Figure 9 As shown, the adjustable dead-time circuit 134 includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, a third capacitor C3, a fourth capacitor C4, a second comparator CMP2, and a third comparator CMP3.

[0099] The inverting input of the second comparator CMP2 is connected to the first terminal of the twelfth transistor M12, the first terminal of the thirteenth transistor M13, and the first plate of the third capacitor C3. The non-inverting input of the second comparator CMP2 is connected to the reference voltage VREF. The output of the second comparator CMP2 is grounded through the fourteenth transistor M14. The output of the second comparator CMP2 is connected to the fourth input of the output logic circuit to output the first adjustable dead time signal RDTA. The enable terminal of the second comparator CMP2, the control terminal of the thirteenth transistor M13, and the control terminal of the fourteenth transistor M14 are connected to the third output of the control logic circuit to receive the first control signal CTR1.

[0100] The inverting input of the third comparator CMP3 is connected to the first terminal of the fifteenth transistor M15, the first terminal of the sixteenth transistor M16, and the first plate of the fourth capacitor. The non-inverting input of the third comparator CMP3 is connected to the reference voltage VREF. The output of the third comparator CMP3 is grounded through the seventeenth transistor M17. The output of the third comparator CMP3 is connected to the fifth input of the output logic circuit to output the second adjustable dead time signal RDTB. The enable terminal of the third comparator CMP3, the control terminal of the sixteenth transistor M16, and the control terminal of the seventeenth transistor M17 are connected to the fourth output of the control logic circuit to receive the second control signal CTR2.

[0101] The second terminal of the twelfth transistor M12 and the second terminal of the fifteenth transistor M15 are connected to the output terminal of the voltage regulator. The second terminal of the thirteenth transistor M13, the second terminal of the sixteenth transistor M16, the second plate of the third capacitor C3, and the second plate of the fourth capacitor C4 are grounded. The control terminal of the twelfth transistor M12 and the control terminal of the fifteenth transistor M15 are connected to the third output terminal of the mode detection circuit to receive the output voltage V3.

[0102] In dual-pass mode / half-bridge fixed dead time mode, the output voltage V3 is high, the twelfth transistor M12 and the fifteenth transistor M15 are turned off, the first control signal CTR1 and the second control signal CTR2 are always high, the second comparator CMP2 and the third comparator CMP3 are disabled, and the first adjustable dead time signal RDTA output by the second comparator CMP2 and the second adjustable dead time signal RDTB output by the third comparator CMP3 are always low.

[0103] In programmable dead-time mode, the output voltage V3 is low, the twelfth transistor M12 and the fifteenth transistor M15 are turned on, the first control signal CTR1 is inverted with the first drive input signal INA, and the second control signal CTR2 is inverted with the second drive input signal INB. At this time, the first mode detection signal ADJ1 is high, the current limiting control switch M_limit is turned on, the current limiting resistor R_limit is short-circuited, and the current I flowing through the first transistor M1... M1 =VREF / R DT , where R DT This is the resistance value of the external resistor.

[0104] When the first drive input signal INA toggles from low to high, the first control signal CTR1 toggles from high to low, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, and the first adjustable dead-time signal RDTA toggles from low to high. Figure 10 As shown, Figure 10 This is a schematic diagram of a signal in a programmable dead-time mode provided in an embodiment of this disclosure.

[0105] At this time, the third capacitor C3 starts charging from 0V. When the voltage on the third capacitor C3, i.e., the inverting input voltage V4 of the second comparator CMP2, rises above the reference voltage VREF, the first adjustable dead time signal RDTA flips to a low level. Therefore, the first adjustable dead time signal RDTA is a pulse square wave, and the pulse width of the first adjustable dead time signal RDTA is the first adjustable dead time T1. Figure 10 As shown.

[0106] The current flowing through the twelfth transistor M12 is VREF / R DT Then the charging current of the third capacitor C3, IREF = VREF / R DT The first adjustable dead time T1 = C3 * VREF / IREF = C3 * R DT Where C3 is the capacitance of the third capacitor C3. Therefore, the resistance R through the external resistor... DT The first adjustable dead time T1 can be linearly adjusted; for example, C3 = 10 pF, T1 = 10 * R. DT The resistance value R of the external resistor is...DT If the value is on the order of kΩ, then the first adjustable dead time T1 is on the order of ns.

[0107] When the second drive input signal INB flips from low to high, the second control signal CTR2 flips from high to low, the sixteenth transistor M16 and the seventeenth transistor M17 are turned off, the second adjustable dead-time signal RDTB flips from low to high, and the fourth capacitor C4 starts charging from 0V. When the voltage on the fourth capacitor C4, i.e., the inverting input voltage V5 of the third comparator CMP3, rises above the reference voltage VREF, the second adjustable dead-time signal RDTB flips to low. Then, the second adjustable dead-time signal RDTB is a square pulse wave, and the pulse width of the second adjustable dead-time signal RDTB is the second adjustable dead-time T2. Figure 10 As shown.

[0108] The current flowing through the fifteenth transistor M15 is VREF / R DT Then the charging current of the fourth capacitor C4, IREF = VREF / R DT The second adjustable dead time T2 = C4 * VREF / IREF = C4 * R DT Where C4 is the capacitance of the fourth capacitor C4, therefore, the resistance R through the external resistor... DT The second adjustable dead time T2 can be linearly adjusted.

[0109] Thus, the adjustable dead-time circuit 134 can adjust the resistance value R of the external resistor according to the dual control signals (CTR1 and CTR2). DT Converted into a dual adjustable dead-time signal (RDTA and RDTB).

[0110] For example, Figure 11 A circuit diagram of an output logic circuit provided in an embodiment of this disclosure is shown below. Figure 11 As shown, the output logic circuit 136 includes a fourth NOR gate (NOR4), a fifth NOR gate (NOR5), a sixth NOR gate (NOR6), a seventh NOR gate (NOR7), an eighth NOR gate (NOR8), a ninth NOR gate (NOR9), a ninth inverter (INV9), a tenth inverter (INV10), an eleventh inverter (INV11), a twelfth inverter (INV12), a thirteenth inverter (INV13), a fourteenth inverter (INV14), a fifteenth inverter (INV15), a fifth NAND gate (NAND5), a sixth NAND gate (NAND6), a seventh NAND gate (NAND7), an eighth NAND gate (NAND8), a ninth NAND gate (NAND9), and a tenth NAND gate (NAND10).

[0111] The first input of the fourth NOR gate NOR4 is connected to the second output of the control logic circuit to receive the second dead time input signal INB_SDT. The second input of the fourth NOR gate NOR4 is connected to the first output of the adjustable dead time circuit to receive the first adjustable dead time signal RDTA. The output of the fourth NOR gate NOR4 is connected to the first input of the fifth NOR gate NOR5.

[0112] The second input of the fifth NOR gate NOR5 is connected to the second output of the mode detection circuit to receive the second mode detection signal ADJ2, and the output of the fifth NOR gate NOR5 is connected to the first input of the sixth NOR gate NOR6.

[0113] The second input of the sixth NOR gate NOR6 is connected to the output of the first fixed dead time circuit to receive the first fixed dead time signal OUTA_SDT. The output of the sixth NOR gate NOR6 is connected to the first input of the fifth NOR gate NOR5 through the ninth inverter INV9.

[0114] The first input of the seventh NOR gate NOR7 is connected to the first output of the control logic circuit to receive the first dead time input signal INA_SDT. The second input of the seventh NOR gate NOR7 is connected to the second output of the adjustable dead time circuit to receive the second adjustable dead time signal RDTB. The output of the seventh NOR gate NOR7 is connected to the first input of the eighth NOR gate NOR8.

[0115] The second input of the eighth NOR gate NOR8 is connected to the second output of the mode detection circuit to receive the second mode detection signal ADJ2, and the output of the eighth NOR gate NOR8 is connected to the first input of the ninth NOR gate NOR9.

[0116] The second input of the ninth NOR gate NOR9 is connected to the output of the second fixed dead time circuit to receive the second fixed dead time signal OUTB_SDT. The output of the ninth NOR gate NOR9 is connected to the first input of the eighth NAND gate NAND8 through the tenth inverter INV10.

[0117] The second mode detection signal ADJ2 is connected to the second input terminal of the fifth NAND gate NAND5 and the second input terminal of the eighth NAND gate NAND8 through the eleventh inverter INV11. The second mode detection signal ADJ2 is connected to the first input terminal of the sixth NAND gate NAND6. The first drive input signal INA is connected to the second input terminal of the sixth NAND gate NAND6 through the twelfth inverter INV12.

[0118] The output of the fifth NAND gate NAND5 is connected to the first input of the seventh NAND gate NAND7, the output of the sixth NAND gate NAND6 is connected to the second input of the seventh NAND gate NAND7, and the output of the seventh NAND gate NAND7 outputs the first drive output signal OUTA through the thirteenth inverter INV13.

[0119] The second mode detection signal ADJ2 is connected to the first input terminal of the ninth NAND gate NAND9. The second drive input signal INB is connected to the second input terminal of the ninth NAND gate NAND9 through the fourteenth inverter INV14. The output terminal of the eighth NAND gate NAND8 is connected to the first input terminal of the tenth NAND gate NAND10. The output terminal of the ninth NAND gate NAND9 is connected to the second input terminal of the tenth NAND gate NAND10. The output terminal of the tenth NAND gate NAND10 outputs the second drive output signal OUTB through the fifteenth inverter INV15.

[0120] In dual-channel mode, the second mode detection signal ADJ2 is high, the sixth NAND gate NAND6 outputs the in-phase signal of the first drive input signal INA, the ninth NAND gate NAND9 outputs the in-phase signal of the second drive input signal INB, and the fifth NAND gate NAND5 and the eighth NAND gate NAND8 output high levels. Therefore, the first drive output signal OUTA is in phase with the first drive input signal INA, and the second drive output signal OUTB is in phase with the second drive input signal INB. Figure 12 As shown, Figure 12 This is a schematic diagram of the signal in dual-channel mode provided in an embodiment of this disclosure.

[0121] In the half-bridge fixed dead-time mode, the second mode detection signal ADJ2 is low, and the first adjustable dead-time signal RDTA and the second adjustable dead-time signal RDTB are always low. The fourth NOR gate NOR4 outputs the inverted signal of the second dead-time input signal INB_SDT, which is also the inverted signal of the second drive input signal INB. Therefore, the fifth NOR gate NOR5 outputs the in-phase signal of the second drive input signal INB. Simultaneously, the seventh NOR gate NOR7 outputs the inverted signal of the first dead-time input signal INA_SDT, which is also the inverted signal of the first drive input signal INA. Therefore, the eighth NOR gate NOR8 outputs the in-phase signal of the first drive input signal INA.

[0122] When the first drive input signal INA is high, the first fixed dead time signal OUTA_SDT is low, and the falling edge has a fixed dead time delay. When the second drive input signal INB flips to low, the sixth NOR gate NOR6 outputs an in-phase signal of the first drive input signal INA with a fixed dead time delay after the second drive input signal INB falls.

[0123] At this time, the output signal of the fifth NAND gate (NAND5) is in phase with the output signal of the sixth NOR gate (NOR6), and the first drive output signal OUTA is in phase with the output signal of the fifth NAND gate (NAND5). Therefore, the first drive output signal OUTA is an in-phase signal of the first drive input signal INA, which has a fixed dead-time delay after the second drive input signal INB falls. Figure 7 As shown.

[0124] Similarly, when the second drive input signal INB is high, the second fixed dead time signal OUTB_SDT is low, and the falling edge has a fixed dead time delay. When the first drive input signal INA flips to low, the ninth NOR gate NOR9 outputs a second drive input signal INB with a fixed dead time delay after the first drive input signal INA falls.

[0125] At this time, the output signal of the eighth NAND gate NAND8 is in phase with the output signal of the ninth NOR gate NOR9, and the second drive output signal OUTB is in phase with the output signal of the eighth NAND gate NAND8. Therefore, the second drive output signal OUTB is an in-phase signal of the second drive input signal INB with a fixed dead time delay after the first drive input signal INA falls.

[0126] In programmable dead-time mode, the second mode detection signal ADJ2 is low. When the second drive input signal INB flips from high to low, the output signal of the fourth NOR gate NOR4 continues to be low for the first adjustable dead time T1 and then flips to high. That is, the fourth NOR gate NOR4 outputs the in-phase signal of the first drive input signal INA with the first adjustable dead time T1 controlled by an external resistor. Then the fifth NOR gate NOR5 outputs the in-phase signal of the first drive input signal INA with the first adjustable dead time T1.

[0127] Therefore, both input signals of the sixth NOR gate NOR6 are inverted signals of the first drive input signal INA and have a falling edge delay. When both input signals are low at the same time, the sixth NOR gate NOR6 outputs a high level, and the first adjustable dead time T1 is greater than the fixed dead time. That is, the sixth NOR gate NOR6 outputs an in-phase signal of the first drive input signal INA with the first adjustable dead time T1.

[0128] At this time, the output signal of the fifth NAND gate NAND5 is in phase with the output signal of the sixth NOR gate NOR6, and the first drive output signal OUTA is in phase with the output signal of the fifth NAND gate NAND5. Therefore, the first drive output signal OUTA is an in-phase signal of the first drive input signal INA with a first adjustable dead time T1. Figure 10 As shown.

[0129] Similarly, when the first drive input signal INA flips from high level to low level, the output signal of the seventh NOR gate NOR7 flips to high level after remaining at a low level for the second adjustable dead time T2. That is, the seventh NOR gate NOR7 outputs a non-inverting signal of the second drive input signal INB with the second adjustable dead time T2 controlled by an external resistor, and the eighth NOR gate NOR8 outputs an inverting signal of the second drive input signal INB with the second adjustable dead time T2.

[0130] Therefore, both input signals of the ninth NOR gate NOR9 are inverted signals of the second drive input signal INB and have a falling edge delay. When both input signals are low at the same time, the ninth NOR gate NOR9 outputs a high level, and the second adjustable dead time T2 is greater than the fixed dead time. That is, the ninth NOR gate NOR9 outputs an in-phase signal of the second drive input signal INB with the second adjustable dead time T2.

[0131] At this time, the output signal of the eighth NAND gate NAND8 is in phase with the output signal of the ninth NOR gate NOR9, and the second drive output signal OUTB is in phase with the output signal of the eighth NAND gate NAND8. Therefore, the second drive output signal OUTB is an in-phase signal of the second drive input signal INB with the second adjustable dead time T2.

[0132] Thus, in dual-channel mode, the output logic circuit 136 can generate dual-drive output signals (OUTA and OUTB) based on the dual-drive input signals (INA and INB).

[0133] In the half-bridge fixed dead time mode, the output logic circuit 136 can generate dual drive output signals (OUTA and OUTB) based on the dual dead time input signals (INA_SDT and INB_SDT) and the dual fixed dead time signals (OUTA_SDT and OUTB_SDT).

[0134] In programmable dead-time mode, the output logic circuit 136 can drive the output signals (OUTA and OUTB) according to the dual dead-time input signals (INA_SDT and INB_SDT), dual fixed dead-time signals (OUTA_SDT and OUTB_SDT), and dual adjustable dead-time signals (RDTA and RDTB).

[0135] In summary, in this embodiment, the drive mode control circuit includes a voltage regulator, a clamping circuit, and a dead-time configuration circuit. The input of the clamping circuit is connected to the dead-time configuration port, and the output of the clamping circuit is connected to the input of the dead-time configuration circuit. The voltage regulator generates an analog voltage based on the power supply voltage and limits the analog voltage to a safe voltage to supply power to the dead-time configuration circuit. In dual-channel mode, the clamping circuit can limit the target voltage to a safe voltage. The dead-time configuration circuit determines the drive mode based on the target voltage and generates dual drive output signals that can be effective simultaneously in dual-channel mode. In half-bridge fixed dead-time mode / programmable dead-time mode, it generates dual drive output signals that cannot be effective simultaneously. Thus, different drive modes can be flexibly configured through only one port, and the dead time can be flexibly configured in programmable dead-time mode to adapt to different application scenarios and is also compatible with high-voltage input.

[0136] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0137] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0138] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A driving mode control circuit for a gate driver chip, characterized in that, The gate driver chip includes a dead time configuration port, and the drive mode control circuit includes a voltage regulator, a clamping circuit, and a dead time configuration circuit. The power supply voltage is connected to the power supply terminal of the dead time configuration circuit through the voltage regulator. The input terminal of the clamping circuit is connected to the dead time configuration port. The output terminal of the clamping circuit is connected to the input terminal of the dead time configuration circuit. The control terminal of the clamping circuit is connected to the detection output terminal of the dead time configuration circuit. The voltage regulator is configured to generate an analog voltage based on the power supply voltage, limit the analog voltage to a safe voltage, and output it. The dead-time configuration circuit is configured to determine the driving mode based on the target voltage. The driving mode includes a dual-channel mode, a half-bridge fixed dead-time mode, and a programmable dead-time mode. In the dual-channel mode, dual driving output signals that can be effective simultaneously are generated. In the half-bridge fixed dead-time mode / programmable dead-time mode, dual driving output signals that cannot be effective simultaneously are generated. The clamping circuit is configured to limit the target voltage from exceeding the safe voltage in the dual-channel mode. In the half-bridge fixed dead time mode, the dual-drive output signal has a fixed dead time, and in the programmable dead time mode, the dual-drive output signal has an adjustable dead time, wherein the adjustable dead time depends on the external resistor of the dead time configuration port.

2. The drive mode control circuit according to claim 1, characterized in that, The clamping circuit includes a clamping transistor and a current limiting circuit; The input terminal of the current limiting circuit is connected to the dead time configuration port, the output terminal of the current limiting circuit is connected to the first terminal of the clamping transistor and the input terminal of the dead time configuration circuit, the second terminal of the clamping transistor is grounded, and the control terminal of the current limiting circuit is connected to the detection output terminal of the dead time configuration circuit. The current limiting circuit is configured to, in the dual-channel mode, limit the current flowing through the clamping transistor; and in the programmable dead-time mode, limit the dead-time configuration port to ground only through the external resistor. The clamping transistor is configured to output the safety voltage when the target voltage is greater than the safety voltage, and to output the target voltage when the target voltage is less than or equal to the safety voltage.

3. The drive mode control circuit according to claim 2, characterized in that, The current limiting circuit includes a current limiting resistor and a current limiting control switch. The current limiting resistor and the current limiting control switch are connected in parallel between the first end of the clamping transistor and the dead time configuration port. The control terminal of the current limiting control switch is connected to the detection output terminal of the dead time configuration circuit.

4. The drive mode control circuit according to claim 2, characterized in that, The dead time configuration circuit includes a mode detection circuit, a first fixed dead time circuit, a second fixed dead time circuit, an adjustable dead time circuit, a control logic circuit, and an output logic circuit. The first input terminal of the pattern detection circuit and the input terminal of the adjustable dead time circuit are connected to a reference voltage. The second input terminal of the pattern detection circuit is connected to the output terminal of the clamping circuit. The first output terminal of the pattern detection circuit is connected to the first input terminal of the control logic circuit. The second output terminal of the pattern detection circuit is connected to the second input terminal of the control logic circuit and the first input terminal of the output logic circuit. The third output terminal of the pattern detection circuit is connected to the first control terminal of the adjustable dead time circuit. The first output terminal of the control logic circuit is connected to the input terminal of the first fixed dead time circuit and the second input terminal of the output logic circuit. The second output terminal of the control logic circuit is connected to the input terminal of the second fixed dead time circuit and the third input terminal of the output logic circuit. The third output terminal of the control logic circuit is connected to the second control terminal of the adjustable dead time circuit. The fourth output terminal of the control logic circuit is connected to the third control terminal of the adjustable dead time circuit. The first output terminal of the adjustable dead time circuit is connected to the fourth input terminal of the output logic circuit, the second output terminal of the adjustable dead time circuit is connected to the fifth input terminal of the output logic circuit, the output terminal of the first fixed dead time circuit is connected to the sixth input terminal of the output logic circuit, and the output terminal of the second fixed dead time circuit is connected to the seventh input terminal of the output logic circuit. The mode detection circuit is configured to determine that when the dead time configuration port is connected to power, the first mode detection signal is at a first level and the second mode detection signal is at a second level, so as to determine that the driving mode is the dual-channel mode. When the dead time configuration port is floating, the first mode detection signal and the second mode detection signal are determined to be at the first level, so that the driving mode is the half-bridge fixed dead time mode. When the dead time configuration port is connected to ground by a resistor, the first mode detection signal is determined to be the second level, and the second mode detection signal is determined to be the first level, so that the driving mode is the programmable dead time mode. The control logic circuit is configured to generate a dual dead-time input signal based on the dual drive input signal in the half-bridge fixed dead-time mode / programmable dead-time mode; and to generate dual control signals based on the dual dead-time input signal in the programmable dead-time mode. The fixed dead time circuit is configured to generate a fixed dead time signal based on the received dead time input signal, wherein the fixed dead time signal is a falling edge delayed inverted signal of the corresponding drive input signal; The adjustable dead-time circuit is configured to convert the resistance value of the external resistor into a dual adjustable dead-time signal according to the dual control signal. The output logic circuit is configured to generate the dual-drive output signal based on the dual-drive input signal in the dual-channel mode; generate the dual-drive output signal based on the dual-dead-time input signal and the dual-fixed-dead-time signal in the half-bridge fixed-dead-time mode; and generate the dual-drive output signal based on the dual-dead-time input signal, the dual-fixed-dead-time signal, and the dual-adjustable-dead-time signal in the programmable-dead-time mode.

5. The drive mode control circuit according to claim 4, characterized in that, The pattern detection circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first comparator, a pull-down resistor, a first hysteresis inverter, a second hysteresis inverter, a third hysteresis inverter, a first inverter, a second inverter, a third inverter, and a first NOR gate. The first transistor is connected between the output terminal of the voltage regulator and the non-inverting input terminal of the operational amplifier; the second transistor and the pull-down resistor are connected in series between the output terminal of the voltage regulator and ground; the first branch formed by the third, fourth, fifth, and sixth transistors connected in series is connected between the output terminal of the voltage regulator and ground; the second branch formed by the seventh, eighth, ninth, and tenth transistors connected in series is connected between the output terminal of the voltage regulator and ground; and the eleventh transistor is connected between the output terminal of the voltage regulator and the output terminal of the first comparator. The non-inverting input of the operational amplifier is connected to the connection point of the fourth and fifth transistors, the output of the clamping circuit, and the inverting input of the first comparator. The inverting input of the operational amplifier is connected to the reference voltage. The output of the operational amplifier is connected to the control terminal of the first transistor, the control terminal of the second transistor, and the first control terminal of the adjustable dead-time circuit. The connection point of the second transistor and the pull-down resistor is connected to the input terminals of the first and second hysteresis inverters. The output of the first hysteresis inverter is connected to the first input terminal of the control logic circuit and the control terminal of the clamping circuit through the first inverter. The output of the second hysteresis inverter is connected to the first input terminal of the first NOR gate through the second inverter. The non-inverting input of the first comparator is connected to the connection point of the eighth transistor and the ninth transistor. The output of the first comparator is connected to the input of the third hysteresis inverter. The output of the third hysteresis inverter is connected to the second input of the first NOR gate through the third inverter. The output of the first NOR gate is connected to the second input of the control logic circuit and the first input of the output logic circuit. The fourth and eighth transistors are diodes. When the first mode detection signal is at the first level, the current flowing through the first branch is greater than the current flowing through the second branch. The third, fifth, seventh, and ninth transistors are controlled by the first mode detection signal, and the eleventh transistor is controlled by the inverted signal of the first mode detection signal.

6. The drive mode control circuit according to claim 4, characterized in that, The control logic circuit includes a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a second NOR gate, and a third NOR gate; The first driving input signal is connected to the first input terminal of the first NAND gate, the second driving input signal is connected to the first input terminal of the second NAND gate, the second output terminal of the pattern detection circuit is connected to the second input terminal of the first NAND gate and the second input terminal of the second NAND gate through the fourth inverter, the output terminal of the first NAND gate is connected to the input terminal of the sixth inverter, the input terminal of the first fixed dead time circuit, the first input terminal of the third NOR gate and the second input terminal of the output logic circuit through the fifth inverter, and the output terminal of the second NAND gate is connected to the input terminal of the eighth inverter, the input terminal of the second fixed dead time circuit, the first input terminal of the second NOR gate and the third input terminal of the output logic circuit through the seventh inverter; The output of the sixth inverter is connected to the second input of the second NOR gate, the output of the eighth inverter is connected to the second input of the third NOR gate, the output of the second NOR gate is connected to the first input of the third NAND gate, the output of the third NOR gate is connected to the first input of the fourth NAND gate, the second inputs of the third NAND gate and the fourth NAND gate are connected to the first output of the pattern detection circuit, the output of the third NAND gate is connected to the second control terminal of the adjustable dead time circuit, and the output of the fourth NAND gate is connected to the third control terminal of the adjustable dead time circuit.

7. The drive mode control circuit according to claim 4, characterized in that, The first fixed dead time circuit includes a first pull-up transistor, a first pull-down transistor, a first grounding resistor, and a first capacitor; the second fixed dead time circuit includes a second pull-up transistor, a second pull-down transistor, a second grounding resistor, and a second capacitor. The first pull-up transistor, the first pull-down transistor, and the first grounding resistor are connected in series between the output terminal of the voltage regulator and ground. The control terminals of the first pull-up transistor and the first pull-down transistor are connected to the first output terminal of the control logic circuit. The first capacitor is connected between the output terminal of the voltage regulator and the connection point of the first pull-up transistor and the first pull-down transistor. The connection point of the first pull-up transistor and the first pull-down transistor is connected to the sixth input terminal of the output logic circuit. The second pull-up transistor, the second pull-down transistor, and the second grounding resistor are connected in series between the output terminal of the voltage regulator and ground. The control terminals of the second pull-up transistor and the second pull-down transistor are connected to the second output terminal of the control logic circuit. The second capacitor is connected between the output terminal of the voltage regulator and the connection point of the second pull-up transistor and the second pull-down transistor. The connection point of the second pull-up transistor and the second pull-down transistor is connected to the seventh input terminal of the output logic circuit.

8. The drive mode control circuit according to claim 4, characterized in that, The adjustable dead-time circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a third capacitor, a fourth capacitor, a second comparator, and a third comparator; The inverting input of the second comparator is connected to the first terminal of the twelfth transistor, the first terminal of the thirteenth transistor, and the first plate of the third capacitor. The non-inverting input of the second comparator is connected to the reference voltage. The output of the second comparator is grounded through the fourteenth transistor. The output of the second comparator is connected to the fourth input of the output logic circuit. The enable terminal of the second comparator, the control terminal of the thirteenth transistor, and the control terminal of the fourteenth transistor are connected to the third output of the control logic circuit. The inverting input of the third comparator is connected to the first terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, and the first plate of the fourth capacitor. The non-inverting input of the third comparator is connected to the reference voltage. The output of the third comparator is grounded through the seventeenth transistor. The output of the third comparator is connected to the fifth input of the output logic circuit. The enable terminal of the third comparator, the control terminal of the sixteenth transistor, and the control terminal of the seventeenth transistor are connected to the fourth output of the control logic circuit. The second terminals of the twelfth transistor and the fifteenth transistor are connected to the output terminal of the voltage regulator. The second terminals of the thirteenth transistor, the sixteenth transistor, the second plate of the third capacitor, and the second plate of the fourth capacitor are grounded. The control terminals of the twelfth transistor and the fifteenth transistor are connected to the third output terminal of the mode detection circuit.

9. The drive mode control circuit according to claim 4, characterized in that, The output logic circuit includes a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, an eighth NOR gate, a ninth NOR gate, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a fifteenth inverter, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, and a tenth NAND gate; The first input terminal of the fourth NOR gate is connected to the second output terminal of the control logic circuit, the second input terminal of the fourth NOR gate is connected to the first output terminal of the adjustable dead time circuit, the output terminal of the fourth NOR gate is connected to the first input terminal of the fifth NOR gate, the second input terminal of the fifth NOR gate is connected to the second output terminal of the pattern detection circuit, the output terminal of the fifth NOR gate is connected to the first input terminal of the sixth NOR gate, the second input terminal of the sixth NOR gate is connected to the output terminal of the first fixed dead time circuit, and the output terminal of the sixth NOR gate is connected to the first input terminal of the fifth NAND gate through the ninth inverter. The first input terminal of the seventh NOR gate is connected to the first output terminal of the control logic circuit; the second input terminal of the seventh NOR gate is connected to the second output terminal of the adjustable dead time circuit; the output terminal of the seventh NOR gate is connected to the first input terminal of the eighth NOR gate; the second input terminal of the eighth NOR gate is connected to the second output terminal of the pattern detection circuit; the output terminal of the eighth NOR gate is connected to the first input terminal of the ninth NOR gate; the second input terminal of the ninth NOR gate is connected to the output terminal of the second fixed dead time circuit; and the output terminal of the ninth NOR gate is connected to the first input terminal of the eighth NAND gate through the tenth inverter. The second output of the pattern detection circuit is connected to the second input of the fifth NAND gate and the second input of the eighth NAND gate through the eleventh inverter. The second output of the pattern detection circuit is connected to the first input of the sixth NAND gate. The first drive input signal is connected to the second input of the sixth NAND gate through the twelfth inverter. The output of the fifth NAND gate is connected to the first input of the seventh NAND gate. The output of the sixth NAND gate is connected to the second input of the seventh NAND gate. The output of the seventh NAND gate outputs the first drive output signal through the thirteenth inverter. The second output terminal of the pattern detection circuit is connected to the first input terminal of the ninth NAND gate. The second drive input signal is connected to the second input terminal of the ninth NAND gate through the fourteenth inverter. The output terminal of the eighth NAND gate is connected to the first input terminal of the tenth NAND gate. The output terminal of the ninth NAND gate is connected to the second input terminal of the tenth NAND gate. The output terminal of the tenth NAND gate outputs the second drive output signal through the fifteenth inverter.

10. A gate driver chip, characterized in that, Includes the drive mode control circuit as described in any one of claims 1-9.

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