An electronic ballast circuit for a UV lamp

Abstract

The utility model discloses a kind of UV lamp electronic ballast circuit, including DC inverter module, isolation transformer T1, sampling feedback control module, interface CN1 and interface CN2;DC inverter module includes PWM control unit and full-bridge inverter chip U4, full-bridge inverter chip U4 has IN1 end, IN2 end, nSLP end, Vref end, OUT1 end, OUT2 end and IPROPI end;PWM control unit has first end, second end and third end, the first end of PWM control unit connects the IN1 end of full-bridge inverter chip U4, the second end of PWM control unit is connected input voltage and the IN2 end of full-bridge inverter chip U4 respectively, the third end of PWM control unit is grounded;The primary of isolation transformer T1 is connected the OUT1 end and OUT2 end of full-bridge inverter chip U4 respectively;The secondary of isolation transformer T1 is connected interface CN1 and interface CN2 in turn;The input end of sampling feedback control module is connected the secondary of isolation transformer T1 and interface CN2 respectively, the output end of sampling feedback control module connects the IN1 end of full-bridge inverter chip U4.

Description

Technical Field

[0001] This utility model relates to the field of electronic ballast circuit technology for UV lamps, specifically, to an electronic ballast circuit for UV lamps. Background Technology

[0002] The electronic ballast circuit is a crucial component of the UV lamp driver circuit. Its primary function is to convert industrial frequency AC power to high-level AC power, providing a stable driving voltage for the UV lamp. Existing UV lamps typically employ traditional inductive electronic ballasts or open-loop electronic ballasts. Both types lack effective overcurrent protection, making them prone to circuit burnout. Furthermore, open-loop electronic ballasts, lacking feedback circuitry, cannot guarantee a stable sinusoidal output current waveform, leading to unstable output current. Utility Model Content

[0003] To address the shortcomings of existing technologies, an electronic ballast circuit for UV lamps is provided.

[0004] To achieve the above objectives, this utility model provides an electronic ballast circuit for a UV lamp, including a DC inverter module, an isolation transformer T1, a sampling feedback control module, an interface CN1, and an interface CN2. The DC inverter module includes a PWM control unit and a full-bridge inverter chip U4. The full-bridge inverter chip U4 has an IN1 terminal, an IN2 terminal, an nSLP terminal, a Vref terminal, an OUT1 terminal, an OUT2 terminal, and an IPROP1 terminal. The PWM control unit has a first terminal, a second terminal, and a third terminal. The first terminal of the PWM control unit is connected to the IN1 terminal of the full-bridge inverter chip U4, the second terminal of the PWM control unit is connected to the input voltage and the IN2 terminal of the full-bridge inverter chip U4, and the third terminal of the PWM control unit is grounded. The primary winding of the isolation transformer T1 is connected to the OUT1 and OUT2 terminals of the full-bridge inverter chip U4. The secondary winding of the isolation transformer T1 is connected in series with the interface CN1 and the interface CN2. The input terminal of the sampling feedback control module is connected to the secondary winding of the isolation transformer T1 and the interface CN2, and the output terminal of the sampling feedback control module is connected to the IN1 terminal of the full-bridge inverter chip U4.

[0005] According to one embodiment of the present invention, the PWM control unit includes a MOSFET Q1. The gate of the MOSFET Q1 is connected to the IN1 terminal of the full-bridge inverter chip U4 and the output terminal of the sampling feedback control module. The drain of the MOSFET Q1 is connected to the IN2 terminal of the full-bridge inverter chip U4, and the source of the MOSFET Q1 is grounded.

[0006] According to one embodiment of the present invention, the sampling feedback control module includes a sampling unit and a comparator U5. One end of the sampling unit is connected to interface CN2, and the other end of the sampling unit is grounded together with the secondary winding of the isolation transformer T1. The comparator U5 has an IV+ terminal, a V- terminal, an IN- terminal, a V+ terminal, an SD terminal, and an OUT terminal. The IV+ terminal of the comparator U5 is connected to the sampling unit, and the V- terminal of the comparator U5 is grounded together with the sampling unit. The IN- terminal of the comparator U5 is grounded, and the V+ and SD terminals of the comparator U5 are connected to the input voltage. The OUT terminal of the comparator U5 is connected to the IN1 terminal of the full-bridge inverter U4.

[0007] According to one embodiment of the present invention, the DC inverter module further includes a first voltage divider unit, which includes resistor R7 and resistor R8. One end of resistor R7 is connected to the Vref terminal of the full-bridge inverter chip U4, and the other end is connected to the power supply voltage. One end of resistor R8 is connected to resistor R7 and the Vref terminal of the full-bridge inverter chip U4, and the other end is grounded.

[0008] According to one embodiment of the present invention, the PWM control unit further includes a second voltage divider unit, which includes resistors R4 and R6. One end of resistor R4 is connected to the IN1 terminal of the full-bridge inverter chip U4, and the other end is connected to resistor R6 and the gate of MOSFET Q1. The other end of resistor R6 is grounded together with the source of MOSFET Q1.

[0009] According to one embodiment of the present invention, the DC inverter module further includes a current limiting unit, which is connected to the nSLP terminal of the full-bridge inverter chip U4.

[0010] According to one embodiment of the present invention, the DC inverter module further includes a filter module, which includes capacitor EC1 and capacitor C2. One end of capacitor EC1 is connected to the VM terminal and the operating voltage of the full-bridge inverter chip U4, and the other end is grounded. Capacitor C2 is connected in parallel with capacitor EC1.

[0011] According to one embodiment of the present invention, it further includes capacitors CCB1 and CCB2. One end of capacitor CCB1 is connected to isolation transformer T1, and the other end is connected to interface CN1; one end of capacitor CCB2 is connected to interface CN1, and the other end is connected to interface CN2.

[0012] According to one embodiment of the present invention, the sampling unit includes an isolation transformer T2 and a sampling resistor RS1. One end of the isolation transformer T2 is connected to an interface CN2, and the other end is connected to the sampling resistor RS1 and the IV+ terminal of the comparator U5. The other end of the sampling resistor RS1 is grounded together with the secondary winding of the isolation transformer T1 and the V- terminal of the comparator U5.

[0013] According to one embodiment of the present invention, a feedback module is also included. The feedback module includes a voltage divider component and a filter capacitor C1. The voltage divider component includes a resistor R5 and a resistor R10. One end of the resistor R5 is connected to the IPO terminal of the full-bridge inverter chip U4 and the resistor R10 respectively, and the other end of the resistor R5 is grounded. The other end of the resistor R10 is connected to the filter capacitor C1, and the other end of the filter capacitor C1 and the resistor R5 are grounded together.

[0014] The beneficial effect of this utility model is that, by setting up a sampling feedback control module and a PWM control unit, the sampling feedback control module samples the electrical signal output by the isolation transformer T1, generates a PWM signal, and feeds the PWM signal back to the PWM control unit 11. The PWM control unit switches the switching state according to the PWM signal to adjust the output of the full-bridge inverter chip U4, thereby adjusting the output of the full-bridge inverter chip U4 to maintain a stable output of the UV lamp electronic ballast signal. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram of the electronic ballast for the UV lamp in the embodiment.

[0016] Explanation of reference numerals in the attached figures 1. DC inverter module; 11. PWM control unit; 111. Second voltage divider unit; 12. First voltage divider unit; 13. Current limiting unit; 14. Filtering module; 2. Sampling feedback control module; 21. Sampling unit; 3. Feedback module; 31. Voltage divider assembly. Detailed Implementation

[0017] The following drawings will disclose several embodiments of this utility model. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this utility model. That is, in some embodiments of this utility model, these practical details are not essential. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0018] Furthermore, in this utility model, the use of terms such as "first" and "second" is for descriptive purposes only and does not specifically refer to any order or sequence, nor is it intended to limit the utility model. They are merely used to distinguish components or operations described with the same technical terms and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If a combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0019] Please refer to Figure 1 , Figure 1 This is a circuit diagram of an electronic ballast circuit for a UV lamp. This embodiment provides an electronic ballast circuit for a UV lamp, which includes a DC inverter module 1, an isolation transformer T2, a sampling feedback control module 2, interface CN1, and interface CN2. The DC inverter module 1 includes a PWM control unit 11 and a full-bridge inverter chip U4. Specifically, the full-bridge inverter chip U4 has IN1, IN2, nSLP, Vref, OUT1, OUT2, IPROPI, VM, and GND terminals. IN1 is used to receive PWM signals, IN2 is used to receive voltage signals, nSLP is the enable terminal, Vref is the reference voltage terminal providing a jump voltage to the full-bridge inverter chip U4, OUT1 and OUT2 are output terminals, IPROPI is the signal feedback terminal, VM is the power supply terminal, and GND is the ground terminal.

[0020] The PWM control unit 11 has a first terminal, a second terminal and a third terminal. The first terminal of the PWM control unit 11 is connected to the IN1 terminal of the full-bridge inverter chip U4. The second terminal of the PWM control unit 11 is connected to the power supply voltage and the IN2 terminal of the full-bridge inverter chip. The third terminal of the PWM control unit 11 is grounded.

[0021] The primary winding of isolation transformer T1 is connected to the OUT1 and OUT2 terminals of the full-bridge inverter chip U4, respectively. The secondary winding of isolation transformer T1 is connected in series with interface CN1 and interface CN2.

[0022] The input terminals of sampling feedback control module 2 are connected to the secondary winding of isolation transformer T1 and interface CN2, respectively. The output terminal of sampling feedback module 3 is connected to the IN1 terminal of full-bridge inverter chip U4.

[0023] The full-bridge inverter chip U4 converts DC to AC, the isolation transformer T1 converts the AC to high-frequency AC output, and interfaces CN1 and CN2 connect to the UV lamp so that the UV lamp's electronic ballast circuit can output a stable high-frequency signal to power the UV lamp. The sampling feedback control module 2 collects the AC output from the isolation transformer T1 and generates a PWM signal output based on the collected AC. The PWM control unit 11 switches the switching state according to the input power supply signal and the PWM signal to control the input of the full-bridge inverter chip U4. In this example, the full-bridge inverter chip U4 is a TMI8123 full-bridge driver chip.

[0024] In practical use, the VM terminal of the full-bridge inverter chip U4 is connected to a +12V power supply. The nSLP and IPROPI terminals of the full-bridge inverter chip U4 are connected to an external host computer. When the UV lamp electronic ballast circuit starts, the host computer sends an enable signal to the nSLP terminal of the full-bridge inverter chip U4, causing the full-bridge inverter chip U4 to start. After the full-bridge inverter chip U4 starts, a +5V input voltage is input to the IN2 terminal of the full-bridge inverter chip U4 and the second terminal of the PWM control unit 11. After the +5V power supply voltage is input to the full-bridge inverter chip U4, the full-bridge inverter chip U4 converts the input voltage into AC power and outputs the AC power to the isolation transformer T1. The isolation transformer T1 converts the AC power output by the full-bridge inverter chip U4 into high-frequency AC power and outputs it to interfaces CN1 and CN2 to power the UV lamps connected to interfaces CN1 and CN2. At the same time, the sampling feedback module 3 collects the electrical signal output by the isolation transformer T1 and generates and outputs a PWM signal based on the collected electrical signal. The PWM signal output by the sampling feedback control module 2 is input to the IN terminal of the full-bridge inverter chip U4 and the first terminal of the PWM control unit 11. The PWM control unit 11 switches its on / off state according to the PWM signal to change the input voltage IN2 of the full-bridge inverter chip U4, thereby changing the output of the full-bridge inverter chip U4. In this way, the full-bridge inverter chip U4 can adjust its output according to the voltage feedback from the isolation transformer T1, ensuring that the UV lamp electronic ballast circuit maintains a stable sinusoidal current output. Furthermore, during use, the input voltage is input to the Vref terminal of the full-bridge inverter chip U4. The full-bridge inverter chip U4 compares the input voltage with a preset reference voltage. If the input voltage is greater than the preset reference voltage, the full-bridge inverter chip U4 shuts down, thereby preventing overvoltage input from damaging the components of the UV lamp electronic ballast circuit and providing overcurrent protection.

[0025] In this example, the DC inverter module 1 also includes resistor 1 and resistor R2. One end of resistor R1 is connected to the IN2 terminal of the full-bridge inverter chip U4, and the other end is connected to the +5V input voltage. Resistor R1 is used for current limiting. One end of resistor R2 is connected to the IN1 terminal of the full-bridge inverter chip U4, and the other end is connected to the output terminal of the sampling feedback control module 2. Resistor R2 is used for current limiting.

[0026] The DC inverter module 1 also includes a first voltage divider unit 12, which includes resistors R7 and R8. One end of resistor R7 is connected to the Vref terminal of the full-bridge inverter chip U4, and the other end is connected to the supply voltage. One end of resistor R8 is connected to both resistor R7 and the Vref terminal of the full-bridge inverter chip U4, and the other end is grounded. Resistors R7 and R8 are used to divide the electrical signal input to the Vref terminal of the full-bridge inverter chip U4.

[0027] The DC inverter module 1 also includes a filter module 14, which includes capacitor EC1 and capacitor C2. One end of capacitor EC1 is connected to the VM terminal of the full-bridge inverter chip U4 and the operating voltage, and the other end is grounded. Capacitor C2 is connected in parallel with capacitor EC1.

[0028] Capacitor EC1 is used to filter out low-frequency noise and ripple in the +12V operating voltage, stabilize the power supply voltage, and reduce the interference of power supply fluctuations on the circuit. Capacitor C2 is used to filter out high-frequency interference in the +12V operating voltage. Together with capacitor EC1, they form a "high-low frequency complementary" power supply filtering network, further improving power supply purity and ensuring the stable operation of the full-bridge inverter chip U4.

[0029] The DC inverter module 1 also includes a current limiting unit 13, which is connected to the nSLP terminal of the full-bridge inverter chip U4. In this example, the current limiting unit 13 includes a resistor R3, one end of which is connected to the nSLP terminal of the full-bridge inverter chip U4, and the other end is connected to an external host computer.

[0030] Furthermore, the UV lamp electronic ballast circuit also includes a feedback module 3, which includes a voltage divider component 31 and a filter capacitor C1. The voltage divider component 31 includes resistors R5 and R10. One end of resistor R5 is connected to the IPPROPO terminal of the full-bridge inverter chip U4 and resistor R10, respectively, and the other end is grounded. The other end of resistor R10 is connected to the filter capacitor C1, and the other end of the filter capacitor C1 is grounded together with resistor R5.

[0031] Resistors R5 and R10 are used for voltage division to prevent the electrical signal output by the full-bridge inverter chip U4 from being too large and damaging the external host computer. Filter capacitor C1 is used to filter out high-frequency signals, so that the signal output by the full-bridge inverter chip U4 remains stable.

[0032] Furthermore, the UV lamp electronic ballast circuit also includes capacitors CCB1 and CCB2. One end of capacitor CCB1 is connected to isolation transformer T1, and the other end is connected to interface CN1; one end of capacitor CCB2 is connected to interface CN1, and the other end is connected to interface CN2.

[0033] In this example, capacitors CCB1 and CCB2 are used to isolate DC power, ensuring a stable sinusoidal AC output to interfaces CN1 and CN2. During connection, interfaces CN1 and CN2 have terminals 1, 2, and 3, respectively. One end of capacitor CCB1 is connected to one end of the secondary winding of isolation transformer T1, and the other end of capacitor CCB1 is connected to terminal 1 of interface CN1. Terminal 3 of interface CN1 is connected to one end of capacitor CCB2, and the other end of capacitor CCB2 is connected to terminal 1 of interface CN2. Terminal 3 of interface CN2 is connected to sampling feedback control module 2.

[0034] Furthermore, the PWM control unit 11 includes a MOSFET Q1. The gate of the MOSFET Q1 serves as the first terminal of the PWM control module and is connected to the IN1 terminal of the full-bridge inverter chip U4 and the output terminal of the sampling feedback control module 2. The drain of the MOSFET Q1 serves as the second terminal of the PWM control module and is connected to the IN2 terminal of the full-bridge inverter chip U4. The source of the MOSFET Q1 serves as the third terminal of the PWM control module and is grounded.

[0035] In operation, MOSFET Q1 switches its on / off state according to the PWM signal. When the PWM signal is high, MOSFET Q1 is on, allowing the input voltage to be input to the full-bridge inverter chip U1; when the PWM signal is low, MOSFET Q1 is off, preventing the input voltage from being input to the full-bridge inverter chip U1. Thus, by switching the on / off state of MOSFET Q1, the input voltage of the full-bridge inverter chip U1 changes, thereby causing the full-bridge inverter chip U1 to adjust its output electrical signal.

[0036] Furthermore, the PWM control unit 11 also includes a second voltage divider unit 111. The second voltage divider unit 111 includes resistors R4 and R6. One end of resistor R4 is connected to the IN1 terminal of the full-bridge inverter chip U4, and the other end is connected to resistor R6 and the gate of MOSFET Q1. The other end of resistor R6 is grounded together with the source of MOSFET Q1. Resistors R4 and R6 are used to divide the signal input to MOSFET Q1.

[0037] The sampling feedback control module 2 includes a sampling unit 21 and a comparator U5. One end of the sampling unit 21 is connected to interface CN2, and the other end of the sampling unit 21 is grounded together with the secondary side of the isolation transformer T1. The comparator U5 has IV+, V-, IN-, V+, SD and OUT terminals. The IV+ terminal of the comparator U5 is connected to the sampling unit 21, and the V- terminal of the comparator U5 is grounded together with the sampling unit 21. The IN- terminal of the comparator U5 is grounded, and the V+ and SD terminals of the comparator U5 are connected to the +5V input voltage. The OUT terminal of the comparator U5 is connected to the IN1 terminal of the full-bridge inverter U4.

[0038] Sampling unit 21 is used to acquire the voltage output from isolation transformer T1 to interface CN2. Comparator U5 is used to receive the voltage acquired by sampling unit 21 and compare the voltage acquired by sampling unit 21 with a preset value. When the voltage acquired by sampling unit 21 reaches the preset value, comparator U5 triggers a level flip, thereby generating a PWM signal, thus realizing the function of PWM signal flipping. In this example, the comparator U5 is an LMV331.

[0039] Furthermore, the sampling feedback control module 2 also includes a resistor R9 and a capacitor C9. One end of the resistor R9 is connected to the OUT terminal of the comparator U5, and the other end is connected to the V+ terminal of the comparator U5. The other end of the capacitor C9 is grounded. In this example, the resistor R9 is used for current limiting, and the capacitor C9 is used for filtering.

[0040] The sampling unit 21 includes an isolation transformer T2 and a sampling resistor RS1. One end of the isolation transformer T2 is connected to terminal 3 of interface CN2, and the other end is connected to the sampling resistor RS1 and the IV+ terminal of comparator U5. The other end of the sampling resistor RS1 is grounded together with the secondary winding of the isolation transformer T1 and the V- terminal of comparator U5.

[0041] Isolation transformer T2 receives the voltage output from isolation transformer T1 to interface CN2 and provides electrical isolation to suppress common-mode noise. The voltage output from isolation transformer T2 is converted into a current signal by sampling resistor RS1 and input to the V+ terminal of comparator U5.

[0042] In summary, by setting up a sampling feedback control module 2 and a PWM control unit 11, the sampling feedback control module 2 samples the electrical signal output by the isolation transformer T1, generates a PWM signal, and feeds the PWM signal back to the PWM control unit 11. The PWM control unit 11 switches the switching state according to the PWM signal to adjust the output of the full-bridge inverter chip U4, thereby adjusting the output of the full-bridge inverter chip U4 to maintain a stable output of the UV lamp electronic ballast signal.

[0043] The above description is merely an embodiment of this utility model and is not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this utility model should be included within the scope of the claims of this utility model.

Claims

1. An electronic ballast circuit for a UV lamp, characterized in that, include: The DC inverter module (1), isolation transformer T1, sampling feedback control module (2), interface CN1 and interface CN2; the DC inverter module (1) includes a PWM control unit (11) and a full-bridge inverter chip U4, the full-bridge inverter chip U4 having IN1 terminal, IN2 terminal, nSLP terminal, Vref terminal, OUT1 terminal, OUT2 terminal and IPROP1 terminal; the PWM control unit (11) has a first terminal, a second terminal and a third terminal, the first terminal of the PWM control unit (11) is connected to the IN1 terminal of the full-bridge inverter chip U4, the PWM control unit... The second terminal of the element (11) is connected to the input voltage and the IN2 terminal of the full-bridge inverter chip U4, respectively, and the third terminal of the PWM control unit (11) is grounded; the primary winding of the isolation transformer T1 is connected to the OUT1 and OUT2 terminals of the full-bridge inverter chip U4, respectively; the secondary winding of the isolation transformer T1 is connected in series with the interface CN1 and the interface CN2; the input terminal of the sampling feedback control module (2) is connected to the secondary winding of the isolation transformer T1 and the interface CN2, respectively, and the output terminal of the sampling feedback control module (2) is connected to the IN1 terminal of the full-bridge inverter chip U4.

2. The UV lamp electronic ballast circuit according to claim 1, characterized in that, The PWM control unit (11) includes a MOS transistor Q1. The gate of the MOS transistor Q1 is connected to the IN1 terminal of the full-bridge inverter chip U4 and the output terminal of the sampling feedback control module (2). The drain of the MOS transistor Q1 is connected to the IN2 terminal of the full-bridge inverter chip U4, and the source of the MOS transistor Q1 is grounded.

3. The UV lamp electronic ballast circuit according to claim 1, characterized in that, The sampling feedback control module (2) includes a sampling unit (21) and a comparator U5. One end of the sampling unit (21) is connected to the interface CN2, and the other end of the sampling unit (21) is grounded together with the secondary side of the isolation transformer T1. The comparator U5 has an IV+ terminal, a V- terminal, an IN- terminal, a V+ terminal, an SD terminal, and an OUT terminal. The IV+ terminal of the comparator U5 is connected to the sampling unit (21), and the V- terminal of the comparator U5 is grounded together with the sampling unit (21). The IN- terminal of the comparator U5 is grounded, and the V+ terminal and SD terminal of the comparator U5 are connected to the input voltage. The OUT terminal of the comparator U5 is connected to the IN1 terminal of the full-bridge inverter U4.

4. The UV lamp electronic ballast circuit according to claim 1, characterized in that, The DC inverter module (1) further includes a first voltage divider unit (12), which includes resistor R7 and resistor R8. One end of resistor R7 is connected to the Vref terminal of the full-bridge inverter chip U4, and the other end is connected to the power supply voltage. One end of resistor R8 is connected to resistor R7 and the Vref terminal of the full-bridge inverter chip U4, and the other end is grounded.

5. The UV lamp electronic ballast circuit according to claim 2, characterized in that, The PWM control unit (11) further includes a second voltage divider unit (111), which includes resistors R4 and R6. One end of resistor R4 is connected to the IN1 terminal of the full-bridge inverter chip U4, and the other end is connected to resistor R6 and the gate of the MOS transistor Q1. The other end of resistor R6 is grounded together with the source of the MOS transistor Q1.

6. The UV lamp electronic ballast circuit according to claim 1, characterized in that, The DC inverter module (1) also includes a current limiting unit (13), which is connected to the nSLP terminal of the full-bridge inverter chip U4.

7. The UV lamp electronic ballast circuit according to claim 1, characterized in that, The DC inverter module (1) also includes a filter module (14), which includes capacitor EC1 and capacitor C2. One end of capacitor EC1 is connected to the VM terminal and the operating voltage of the full-bridge inverter chip U4, and the other end is grounded. Capacitor C2 is connected in parallel with capacitor EC1.

8. The UV lamp electronic ballast circuit according to claim 1, characterized in that, It also includes capacitors CCB1 and CCB2. One end of capacitor CCB1 is connected to the isolation transformer T1, and the other end is connected to the interface CN1. One end of capacitor CCB2 is connected to the interface CN1, and the other end is connected to the interface CN2.

9. The UV lamp electronic ballast circuit according to claim 3, characterized in that, The sampling unit (21) includes an isolation transformer T2 and a sampling resistor RS1. One end of the isolation transformer T2 is connected to the interface CN2, and the other end is connected to the sampling resistor RS1 and the IV+ terminal of the comparator U5. The other end of the sampling resistor RS1 is grounded together with the secondary winding of the isolation transformer T1 and the V- terminal of the comparator U5.

10. The UV lamp electronic ballast circuit according to claim 1, characterized in that, It also includes a feedback module (3), which includes a voltage divider component (31) and a filter capacitor C1. The voltage divider component (31) includes a resistor R5 and a resistor R10. One end of the resistor R5 is connected to the IPO terminal of the full-bridge inverter chip U4 and the resistor R10, respectively, and the other end is grounded. The other end of the resistor R10 is connected to the filter capacitor C1, and the other end of the filter capacitor C1 is grounded together with the resistor R5.

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