A trench power mos device with enhanced voltage withstand characteristics

Abstract

A trench power MOS device with enhanced voltage resistance characteristics. It relates to the technical field of semiconductor. The polycrystalline silicon is arranged in the K dielectric layer, a stable gate conductive channel is formed, the interface contact performance with the K dielectric layer is excellent, the rising of conduction loss caused by the increase of gate resistance can be avoided (compared with the traditional external polycrystalline silicon structure, the conduction loss can be reduced by 10%-15%), meanwhile, the arc-shaped bottom design of the K dielectric layer does not increase the lateral size of the device additionally, and does not introduce a complex laminated structure, the increase of gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) can be effectively controlled, the switch speed is prevented from falling, the core characteristics of low conduction loss and fast switch speed of the device are ensured, and the operation demand of 'high frequency and high efficiency' of the electric drive system of the electric vehicle is met.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a trench power MOS device with enhanced withstand voltage characteristics. Background Technology

[0002] In the field of power semiconductor devices, trench MOSFETs are power devices that optimize current paths through a vertical trench structure. Their core feature is the formation of three-dimensional conductive channels within the silicon wafer using a deep trench etching process. Compared to traditional planar MOSFETs, trench structures offer lower conduction losses, better switching performance, and avoid the parasitic JFET effect.

[0003] Currently, the curvature effect at the bottom of the trench in trench MOSFETs causes severe electric field concentration in the silicon dioxide dielectric layer in this region. This not only significantly reduces the gate oxide quality, but may also cause gate oxide breakdown in severe cases. As the performance requirements of power devices in electric vehicle drive systems continue to increase, maintaining device characteristics and improving voltage withstand characteristics have become key research directions in the current development of power semiconductor technology. Utility Model Content

[0004] To address the above problems, this invention provides a trench power MOS device with enhanced withstand voltage characteristics that maintains the device's on-resistance, threshold voltage, and improves its withstand voltage characteristics.

[0005] The technical solution of this utility model is:

[0006] A trench power MOS device with enhanced breakdown voltage characteristics includes a substrate, an epitaxial layer, a WELL region and a source region connected sequentially from bottom to top;

[0007] The source region is equipped with:

[0008] A metal layer extends downward from the top of the source region to the third WELL region;

[0009] A K dielectric layer extends downward from the top of the source region, and the bottom of the K dielectric layer has an arc-shaped structure, located below the WELL region;

[0010] Polycrystalline silicon is disposed within the K dielectric layer.

[0011] Specifically, the thickness of the epitaxial layer ranges from 4 to 20 μm.

[0012] Specifically, the depth of the K dielectric layer ranges from 0.5 to 3 μm.

[0013] Specifically, the thickness of the K dielectric layer in step three ranges from 200 to 1000 Å.

[0014] Specifically, the material of the K dielectric layer is one or a combination of HfO2, Al2O3, and ZrO2.

[0015] This invention features polysilicon disposed within a K dielectric layer, forming a stable gate conductive channel. Its interface with the K dielectric layer exhibits excellent contact performance, preventing increased conduction losses due to increased gate resistance (conduction losses can be reduced by 10%-15% compared to traditional external polysilicon structures). Simultaneously, the arc-shaped bottom design of the K dielectric layer does not increase the device's lateral dimensions or introduce complex stacked structures, effectively controlling the increase in gate-source capacitance (Cgs) and gate-drain capacitance (Cgd), preventing a decrease in switching speed, and ensuring that the device maintains its core characteristics of low conduction loss and fast switching speed, meeting the "high-frequency, high-efficiency" operation requirements of electric vehicle drive systems. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the substrate and epitaxial structure.

[0017] Figure 2 This is a schematic diagram of the etched trench structure;

[0018] Figure 3 This is a schematic diagram of the gate dielectric layer structure;

[0019] Figure 4 This is a schematic diagram of a deposited polycrystalline silicon (Poly) structure;

[0020] Figure 5 This is a schematic diagram of the WELL region structure formed by stepwise injection;

[0021] Figure 6 This is a schematic diagram of the active region structure formed by injection;

[0022] Figure 7 This is a schematic diagram of etching through holes and filling a metal structure;

[0023] In the figure, 1 is the substrate, 2 is the epitaxial layer, 3 is the high-k dielectric layer, 4 is polysilicon, 5 is the first Well region, 6 is the second Well region, 7 is the third Well region, 8 is the source region, and 9 is the metal layer. Detailed Implementation

[0024] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0025] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0026] A method for fabricating a trench power MOS device with enhanced breakdown voltage characteristics includes the following steps:

[0027] Step 1, as follows Figure 1 As shown, a silicon substrate 1 is provided, and an epitaxial layer 2 of the same conductivity type is grown on the substrate 1, wherein the thickness of the epitaxial layer 2 ranges from 4 to 20 μm.

[0028] Step two, as Figure 2 As shown, a layer of silicon oxide and silicon nitride is deposited on the surface of epitaxial layer 2 to protect the non-trench areas. Using photolithography, silicon nitride, silicon oxide, and epitaxial layer 2 are sequentially etched away in the areas exposed by the photomask to form trenches of a specific depth. Next, the bottom of the trenches is processed to make the corners rounded. After obtaining the trenches, the surface silicon oxide and silicon nitride are removed. The depth of the formed trenches ranges from 0.5 to 3 μm and cannot exceed the thickness of epitaxial layer 2.

[0029] Step 3, as Figure 3 As shown, a K dielectric layer 3 is deposited on the surface of the trench;

[0030] The thickness of the K dielectric layer 3 ranges from 200 to 1000 Å. The thickness of the dielectric layer 3 at the bottom of the trench is greater than that of the dielectric layer 3 on the sidewall. The material of the high K dielectric layer can be one or a combination of HfO2, Al2O3, and ZrO2.

[0031] Step four, as Figure 4 As shown, polysilicon 4 is filled into the trench and then etched back to the horizontal.

[0032] Step 5, as Figure 5 As shown, ion implantation is performed on epitaxial layer 2 to form a well region;

[0033] Further optimization involves multiple ion implantations to sequentially form the first Well region 5, the second Well region 6, and the third Well region 7. The total depth of the Well regions cannot exceed the trench depth. The doping concentrations of the third Well region 7, the second Well region 6, and the first Well region 5 decrease sequentially from the silicon wafer surface, forming a stepped concentration distribution. The first Well region 5 and the second Well region 6 have lower doping concentrations, acting as buffer layers between Well region 7 and epitaxial layer 2, resulting in a smoother doping change in the PN junction and forming a gradually changing junction. The doping concentrations of the first Well region 5, the second Well region 6, and the third Well region 7 are approximately 5e⁻¹. 15 1e 16 5e 16 ~5e 17 cm -3 .

[0034] Step six, as follows Figure 6 As shown, ion implantation is performed on epitaxial layer 2 to form a heavily doped source region 8, wherein the doping concentration of source region 8 is higher than that of WELL region 7; the doping concentration of source region 8 is 1.5e 20 .

[0035] Step seven, as Figure 7 As shown, through-hole 9 is etched and filled with metal to finally form a complete MOSFET structure.

[0036] This invention abandons the complex and expensive superjunction epitaxial process and avoids the waste of device area caused by the field plate structure. Through structural optimization, it achieves compatibility with existing processes, improving performance while controlling costs and maintaining a high area utilization rate. The structural design is compatible with existing MOSFET fabrication processes, enabling mass production without large-scale modifications to production lines, accelerating technology implementation and industrial application, and adapting to the development trend of high performance and low cost in power semiconductor devices.

[0037] A trench power MOS device with enhanced breakdown voltage characteristics includes a substrate 1, an epitaxial layer 2, a WELL region and a source region 8 connected sequentially from bottom to top;

[0038] The source region 8 is equipped with:

[0039] Metal layer 9 extends downward from the top surface of source region 8 to third WELL region 7, and is spaced from the bottom surface of third WELL region 7;

[0040] K dielectric layer 3 extends downward from the top surface of the source region 8 to below the WELL region, and the bottom of the K dielectric layer 3 has an arc structure;

[0041] The core idea of ​​high-k dielectric is to replace SiO2 with a thicker insulating layer without sacrificing gate control capability (Cox). According to the capacitance formula C = K / d, a greater thickness of high-k dielectric is needed to maintain the capacitance. At the same voltage, the high-k dielectric layer can have a lower electric field strength (E = V / d, where d is the dielectric thickness and K is the dielectric constant). When the high-k dielectric layer covers the curved bottom, even if there is a gradient in the external electric field distribution, the electric field inside the dielectric layer can be effectively "diluted." At the interface between the high-k dielectric and the epitaxial layer (semiconductor), the curved design combined with the high-k characteristics reduces interface charge accumulation, avoiding local electric field distortion caused by charge accumulation. Therefore, the high-k dielectric layer at the curved bottom disperses the electric field strength at the bottom of the trench, significantly reducing the electric field concentration in the gate oxide region, reducing the risk of gate oxide breakdown, and improving the long-term operating stability of the device.

[0042] The K dielectric layer 3 comprises one or a combination of HfO2, Al2O3, and ZrO2 materials. Silica has a relatively low dielectric constant, approximately 3.9. High-K materials have much higher dielectric constants, typically >10, and can even reach tens to hundreds. These materials are generally metal oxides (such as HfO2 and ZrO2) and composite high-titanium minerals (BST), exhibiting characteristics such as high capacitance density, low leakage current, and good thermal stability. Using high-K materials instead of traditional silica can reduce the electric field strength without increasing the physical thickness.

[0043] The breakdown voltage (breakdown field strength Eb) of the dielectric layer in power devices is an inherent property. When the actual electric field strength E in a certain region of the dielectric layer exceeds Eb, breakdown failure will occur. Since the electric field is naturally concentrated at the bottom of the trench, if a uniformly thick K dielectric layer is used, the overall dielectric layer needs to be thickened to prevent bottom breakdown—but this would result in excessively thick sidewall dielectric layers, increasing not only the gate capacitance (affecting switching speed) but also increasing manufacturing costs. In this case, the thickness of the bottom arc-shaped region of the K dielectric layer 3 is greater than the thickness of the trench sidewall region. The optimal ratio of the thickness of the bottom arc-shaped region of the K dielectric layer to the thickness of the trench sidewall region is 1.2:1 - 1.8:1, which increases the gate oxide breakdown voltage by 20%-40%, effectively solving the key problem of "easy gate oxide breakdown at the bottom of the trench" and improving the long-term reliability of the device. Maintaining a relatively thin K-dielectric layer on the sidewall (in this case, the sidewall thickness ranges from 200 to 800 Å) can reduce Cgs and Cgd by 10%-20% compared to the "uniform thick dielectric layer scheme", and reduce switching losses by 12%-18%. While improving withstand voltage, it ensures that the device has excellent switching speed, which is suitable for the "high frequency and low loss" requirements of electric vehicle drive systems.

[0044] Polycrystalline silicon 4 is disposed within the K dielectric layer 3, and a gap is provided between the bottom of the polycrystalline silicon 4 and the bottom of the K dielectric layer 3.

[0045] In this case, there is a gap between the K dielectric layer 3 and the bottom surface of the epitaxial layer 2; the polycrystalline silicon 4 is inside the K dielectric layer 3, which has a U-shaped cross-section.

[0046] This article only uses Trench MOS as an example. Any discrete product with a trench structure can be made to overcome the poor chip voltage due to the electric field at the bottom corner of the trench.

[0047] Regarding the information disclosed in this case, the following points need to be clarified:

[0048] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0049] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0050] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A trench power MOS device with enhanced breakdown voltage characteristics, characterized in that, It includes a substrate (1), an epitaxial layer (2), a WELL region and a source region (8) connected sequentially from bottom to top. The source region (8) is provided with: A metal layer (9) extends downward from the top surface of the source region (8) to the third WELL region (7); The K dielectric layer (3) extends downward from the top surface of the source region (8), and the bottom of the K dielectric layer (3) has an arc-shaped structure, located below the WELL region; Polycrystalline silicon (4) is disposed within the K dielectric layer (3).

2. The trench power MOS device with enhanced withstand voltage characteristics according to claim 1, characterized in that, The thickness of the epitaxial layer (2) ranges from 4 to 20 μm.

3. A trench power MOS device with enhanced withstand voltage characteristics according to claim 1, characterized in that, The depth of the K dielectric layer (3) ranges from 0.5 to 3 μm.

4. A trench power MOS device with enhanced withstand voltage characteristics according to claim 1, characterized in that, The thickness of the K dielectric layer (3) mentioned in step three ranges from 200 to 1000 Å.

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