A semiconductor device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-09-12
- Publication Date
- 2026-08-07
AI Technical Summary
[0004]本申请的目的在于提供一种半导体器件，以便改善相邻栅极结构之间容易发生短路的问题
[0032] Compared to existing technologies where only the top surface of the isolation layer closest to the active region is lower than the active region, resulting in residues remaining in the recessed area formed by the top surface of a single isolation layer, in one embodiment of this application, the top surfaces of the first and third isolation layers between the active region and the second isolation layer are both lower. This means that at least two isolation layers are reserved between the active region and the second isolation layer, providing a larger space for residues. Thus, even if residues are generated during the formation of the gate structure, they can be removed by subsequent etching processes, solving the problem of short circuits between adjacent gate structures.
Smart Images
Figure CN224611136U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology
[0002] As electronic products trend towards miniaturization, semiconductor device design must also meet the requirements of high integration and high density. Due to its extremely high device density, shallow trench isolation technology is widely used in integrated circuits with process feature sizes of 0.25μm and below.
[0003] When using shallow trench isolation technology, different materials used to fill the isolation layers in the trenches can lead to etching differences. Typically, the top surface of the isolation layer closest to the substrate in the trench isolation will be lower than the top surface of the active region. Subsequently, when forming the gate structure, the gate structure will remain on this isolation layer. Due to the small size of this residue, it is difficult to remove even with subsequent etching processes. This residue can cause short circuits between adjacent gate structures. Utility Model Content
[0004] The purpose of this application is to provide a semiconductor device to improve the problem of short circuits easily occurring between adjacent gate structures.
[0005] This application provides a semiconductor device, including:
[0006] The substrate includes an active region and an isolation trench defined by the active region;
[0007] The first isolation layer is located on the inner side of the isolation trench;
[0008] The second isolation layer is located on top of the first isolation layer;
[0009] A third isolation layer is located between the first isolation layer and the second isolation layer;
[0010] A gate dielectric layer is located on the active region;
[0011] A gate structure is located on the gate dielectric layer;
[0012] The contact surface between the third isolation layer and the second isolation layer has a first highest vertex, and the contact surface between the third isolation layer and the first isolation layer has a second highest vertex, with the first highest vertex being higher than the second highest vertex; the contact surface between the first isolation layer and the active region has a third highest vertex, with the third highest vertex being higher than the second highest vertex;
[0013] The top surface of the active region in contact with the gate dielectric layer is higher than the first highest vertex, the second highest vertex, and the third highest vertex.
[0014] Further, it includes: a recessed region located between the second isolation layer and the active region, wherein the inner surface of the recessed region passes sequentially from the first highest vertex through the second highest vertex and the third highest vertex.
[0015] Furthermore, the upper surface of the first isolation layer and the upper surface of the third isolation layer are both lower than the upper surface of the second isolation layer and the upper surface of the active region.
[0016] Furthermore, along a direction parallel to the substrate, twice the width of the recessed region is greater than the width of the second isolation layer.
[0017] Furthermore, the gate dielectric layer extends to cover the inner side of the recessed region, and the dielectric layer located on the inner side of the recessed region is in direct contact with the upper surface of the first isolation layer and the upper surface of the third isolation layer.
[0018] Furthermore, the semiconductor device further includes a barrier layer that covers the gate structure and extends to cover the gate dielectric layer on the inner side of the recessed region.
[0019] Furthermore, the gate dielectric layer also covers the upper surface of the second isolation layer.
[0020] Furthermore, the semiconductor device also includes
[0021] A barrier layer covers the gate structure and extends to cover the inner side of the recessed region. The barrier layer located on the inner side of the recessed region is in direct contact with the upper surface of the first isolation layer and the upper surface of the third isolation layer.
[0022] Furthermore, the barrier layer also covers the upper surface of the second isolation layer.
[0023] This application also provides another semiconductor device, including:
[0024] The substrate includes an active region and an isolation trench defined by the active region;
[0025] The first isolation layer is located on the inner side of the isolation trench;
[0026] The second isolation layer is located on top of the first isolation layer;
[0027] A third isolation layer is located between the first isolation layer and the second isolation layer;
[0028] A gate dielectric layer is located on the substrate;
[0029] A gate structure is located on the gate dielectric layer;
[0030] The contact surface between the third isolation layer and the second isolation layer has a first highest vertex, and the contact surface between the third isolation layer and the first isolation layer has a second highest vertex, with the first highest vertex being higher than the second highest vertex; the contact surface between the first isolation layer and the active region has a third highest vertex, with the third highest vertex being higher than the second highest vertex;
[0031] The recessed region is located between the second isolation layer and the active region, and the inner surface of the recessed region passes sequentially from the first highest vertex through the second highest vertex and the third highest vertex.
[0032] Compared to existing technologies where only the top surface of the isolation layer closest to the active region is lower than the active region, resulting in residues remaining in the recessed area formed by the top surface of a single isolation layer, in one embodiment of this application, the top surfaces of the first and third isolation layers between the active region and the second isolation layer are both lower. This means that at least two isolation layers are reserved between the active region and the second isolation layer, providing a larger space for residues. Thus, even if residues are generated during the formation of the gate structure, they can be removed by subsequent etching processes, solving the problem of short circuits between adjacent gate structures. Attached Figure Description
[0033] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0034] Figure 1a This is a schematic diagram of a semiconductor device provided in one embodiment of this application;
[0035] Figure 1b for Figure 1a Enlarged view of A in the middle;
[0036] Figure 2 This is a schematic diagram of a semiconductor device provided in another embodiment of this application;
[0037] Figure 3 This is a schematic diagram of a semiconductor device provided in yet another embodiment of this application;
[0038] Figure 4 This is a schematic diagram of a semiconductor device provided in another embodiment of this application;
[0039] Figure 5a This is a schematic diagram of a partial semiconductor device provided in other embodiments of this application;
[0040] Figure 5b for Figure 5a A magnified view of B in the middle.
[0041] Explanation of reference numerals in the attached figures:
[0042] 1. Substrate; 10. First isolation layer; 11. Isolation trench; 12. Active region; 20. Third isolation layer; 30. Second isolation layer; 40. Gate dielectric layer; 50. Gate structure; 501. Capping layer; 502. Metal conductive layer; 503. Semiconductor layer; 60. Barrier layer; 70. Contact plug; 80. Sidewall layer; 90. Interlayer dielectric layer; 100. Recessed region; 110. First highest vertex; 120. Third highest vertex; 130. Second highest vertex. Detailed Implementation
[0043] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only possible technical implementations of this utility model and not all possible implementations. Those skilled in the art can obtain other embodiments in conjunction with the embodiments of this utility model without creative effort, and these embodiments are also within the protection scope of this utility model.
[0044] Please refer to Figure 1a , Figure 1b In some embodiments, the semiconductor device includes a substrate 1, a first isolation layer 10, a second isolation layer 30, a third isolation layer 20, a gate dielectric layer 40, and a gate structure 50; the substrate 1 is a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate 1. The substrate 1 includes an active region 12 and an isolation trench 11 defined by the active region 12; the first isolation layer 10 is located on the inner side of the isolation trench 11, that is, the first isolation layer 10 is located at the innermost side of the isolation trench 11 and is in direct contact with the active region 12; the second isolation layer 30 is located on the first isolation layer 10 and at the innermost side of the isolation trench 11; the third isolation layer 20 is located between the first isolation layer 10 and the second isolation layer 30, and the third isolation layer 20 may be U-shaped and surround the second isolation layer 30.
[0045] A gate dielectric layer 40 is located on the active region 12. A gate structure 50 is provided on the gate dielectric layer 40. The gate structure 50 may include a semiconductor layer 503, a metal conductive layer 502, and a capping layer 501 stacked sequentially from bottom to top. Sidewall layers 80 may be provided on both sides of the gate structure 50, and the sidewall layers 80 are in direct contact with the semiconductor layer 503, the metal conductive layer 502, and the capping layer 501.
[0046] The contact surface between the third isolation layer 20 and the second isolation layer 30 has a first highest vertex 110, and the contact surface between the third isolation layer 20 and the first isolation layer 10 has a second highest vertex 130. The first highest vertex 110 is higher than the second highest vertex 130, that is, the top surface of the second isolation layer 30 is higher than the top surface of the first isolation layer 10. The contact surface between the first isolation layer 10 and the active region 12 has a third highest vertex 120, and the third highest vertex 120 is higher than the second highest vertex 130, that is, the top surface of the active region 12 is higher than the top surface of the first isolation layer 10. The top surface of the active region 12 in contact with the gate dielectric layer 40 is higher than the first highest vertex 110, the second highest vertex 130, and the third highest vertex 120.
[0047] In detail, the first highest vertex 110 and the third highest vertex 120 are both higher than the second highest vertex 130. That is, the top surfaces of the first isolation layer 10 and the third isolation layer 20 located between the second isolation layer 30 and the active region 12 are lower. Compared to the prior art where only the top surface of the isolation layer closest to the active region 12 is lower than the active region 12, in this embodiment, the top surfaces of the first isolation layer 10 and the third isolation layer 20 between the active region 12 and the second isolation layer 30 are both lower. That is, a larger space is reserved between the active region 12 and the second isolation layer 30, so that even if residues are generated during the formation of the gate structure 50, they can be removed by subsequent etching processes. In some embodiments, along the direction parallel to the substrate 1, the width of the double recessed region 100 is greater than the width of the second isolation layer 30.
[0048] Please continue to refer to this. Figure 1a , Figure 1b In some embodiments, a recessed region 100 is provided between the second isolation layer 30 and the active region 12. The inner surface of the recessed region 100 passes sequentially from the first highest vertex 110 through the second highest vertex 130 and the third highest vertex 120. Specifically, the recessed region 100 is provided between the active region 12 and the second isolation layer 30. Compared to the prior art where only the top surface of the isolation layer closest to the active region 12 is lower than the active region 12, in this embodiment, the recessed region 100 is located on the top surface of the first isolation layer 10 and the third isolation layer 20. That is, the width of the recessed region 100 is the width of two isolation layers, which is wider than the top surface of a single isolation layer. This allows any residue generated during the formation of the gate structure 50 to be removed subsequently by an etching process.
[0049] In some embodiments, the material of the third isolation layer 20 is different from the materials of the first isolation layer 10 and the second isolation layer 30. The material of the isolation layer can be silicon oxide or silicon nitride. Preferably, the material of the third isolation layer 20 can be silicon nitride, the material of the first isolation layer 10 can be silicon oxide, and the material of the second isolation layer 30 can be the same as the material of the first isolation layer 10. In some embodiments, the semiconductor device further includes an interlayer dielectric layer 90, which is located on the substrate 1 and covers the gate structure 50, the first isolation layer 10, the second isolation layer 30, and the third isolation layer 20. The top surface of the interlayer dielectric layer 90 located on the isolation trench 11 is lower than the top surface of the interlayer dielectric layer 90 located on the active region 12.
[0050] Please continue to refer to this. Figure 1b In some embodiments, the contact surface between the third isolation layer 20 and the second isolation layer 30 has a first highest vertex 110, which is lower than the top surface of the second isolation layer 30. The distance 1D between the top surface of the second isolation layer 30 and the top surface of the active region 12 is less than the distance 2D between the second highest vertex 130 and the top surface of the active region 12. That is, the heights of the top surface of the second isolation layer 30 and the top surface of the active region 12 are similar. In this way, the height difference between the isolation layer and the active region 12 can be reduced, which is beneficial to the subsequent process.
[0051] The third isolation layer 20 has a similar top surface height to the first isolation layer 10, meaning the bottom of the recessed region 100 is relatively flat, which is beneficial for removing residues of the gate structure 50 in the recessed region 100. The side of the third isolation layer 20 closest to the second isolation layer 30 is higher, meaning the third isolation layer 20 will cover more of the sidewalls of the second isolation layer 30. Furthermore, the material of the third isolation layer 20 is different from that of the second isolation layer 30. This reduces the probability of the sidewalls of the second isolation layer 30 being etched, thus facilitating the obtaining of a second isolation layer 30 that is closer to the height of the substrate 1.
[0052] For details, please refer to Figure 1b , Figure 5a , Figure 5b The top surfaces of the first isolation layer 10 and the third isolation layer 20 are curved rather than flush. The third isolation layer 20 extends along the direction perpendicular to the substrate 1, covering the side surface of the second isolation layer 30, and the first isolation layer 10 extends along the direction perpendicular to the substrate 1, covering the side surface of the active region 12. This protects the side surfaces of the second isolation layer 30 and the active region 12 from etching as much as possible. The junction and perimeter of the top surfaces of the first isolation layer 10 and the third isolation layer 20 can be made relatively flat or flush, which is more conducive to the removal of residues. The perimeter can be half the width 1D of the first isolation layer 10 or half the width 1C of the third isolation layer 20 at the junction.
[0053] Please refer to Figure 2 In some embodiments, the semiconductor device further includes a barrier layer 60 and a contact plug 70. The barrier layer 60 extends sequentially from the isolation trench 11 on one side of the gate structure 50, covering the sidewall layer 80 and the capping layer 501 on one side of the gate structure 50, the sidewall layer 80 on the other side of the gate structure 50, and the isolation trench 11 on the other side of the gate structure 50. The isolation layer completely covers the top surface of the first isolation layer 10, the top surface of the second isolation layer 30, and the top surface of the third isolation layer 20. The contact plug 70 is located on the active region 12 on one side of the gate structure 50, passing through the interlayer dielectric layer 90 and the barrier layer 60, and directly contacts the active region 12.
[0054] Please refer to Figure 2 In some embodiments, the barrier layer 60 covers the gate structure 50 and extends to cover the gate dielectric layer 40 on the inner side of the recessed region 100. After removing the residue in the recessed region 100, there is still a height difference between the recessed region 100 and the top surface of the substrate 1 and the top surface of the second isolation layer 30. Filling the recessed region 100 with the barrier layer 60 can further reduce the height difference between the recessed region 100 and the top surface of the substrate 1 and the top surface of the second isolation layer 30, which is beneficial for subsequent processes. In other embodiments, the gate dielectric layer 40 also covers the upper surface of the second isolation layer 30. The interlayer dielectric layer 90 also covers the barrier layer 60.
[0055] Please refer to Figure 3 In some embodiments, the top surfaces of the first isolation layer 10 and the third isolation layer 20 are both lower than the top surfaces of the second isolation layer 30 and the active region 12. A recessed region 100 is provided between the second isolation layer 30 and the active region 12. The inner surface of the recessed region 100 extends from the first highest vertex 110 through the second highest vertex 130 and the third highest vertex 120. The gate dielectric layer 40 also extends to cover the inner surface of the recessed region 100. The dielectric layer located on the inner surface of the recessed region 100 is in direct contact with the upper surface of the first isolation layer 10 and the upper surface of the third isolation layer 20. The gate dielectric layer 40 is at least one of silicon oxide and silicon nitride. By first providing a gate dielectric layer 40 in the recessed region 100, a portion of the thickness of the recessed region 100 can be filled. Residue remaining in the recessed region 100 will remain on the gate dielectric layer 40. Due to the presence of the gate dielectric layer 40, the proportion of residue in the recessed region 100 will be smaller, which is more conducive to the removal of residue. The gate dielectric layer 40 can extend sequentially from the active region 12 on one side of the isolation trench 11 to the top surface of the isolation layer and the active region 12 on the other side of the isolation trench 11. In some embodiments, a barrier layer 60 can be disposed on the gate dielectric layer 40. For example, the barrier layer 60 extends from the active region 12 to the gate dielectric layer 40 located in a recessed region 100, the top surface of the second isolation layer 30, and the gate dielectric layer 40 located in another recessed region 100.
[0056] Please refer to Figure 4 In some embodiments, the gate dielectric layer is located between the active region 12 and all gate structures 50 in a direction perpendicular to the substrate 1, and the gate dielectric layer also extends to the top surface of the first isolation layer 10 and the top surface of the third isolation layer 20 in a direction parallel to the substrate 1. In some embodiments, the barrier layer 60 covers the gate structure 50 and extends to cover the inner surface of the recessed region 100, and the barrier layer 60 located on the inner surface of the recessed region 100 is in direct contact with the top surface of the first isolation layer 10 and the top surface of the third isolation layer 20. After removing the residue in the recessed region 100, there is still a height difference between the recessed region 100 and the top surface of the active region 12 and the top surface of the second isolation layer 30. Filling the recessed region 100 with the barrier layer 60 can further reduce the height difference between the recessed region 100 and the top surface of the active region 12 and the top surface of the second isolation layer 30, which is beneficial for subsequent processes. In other embodiments, the barrier layer 60 also covers the top surface of the second isolation layer 30.
[0057] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.
Claims
1. A semiconductor device, characterized in that, include: The substrate includes an active region and an isolation trench defined by the active region; The first isolation layer is located on the inner side of the isolation trench; The second isolation layer is located on top of the first isolation layer; A third isolation layer is located between the first isolation layer and the second isolation layer; A gate dielectric layer is located on the active region; A gate structure is located on the gate dielectric layer; The contact surface between the third isolation layer and the second isolation layer has a first highest vertex, and the contact surface between the third isolation layer and the first isolation layer has a second highest vertex, with the first highest vertex being higher than the second highest vertex; the contact surface between the first isolation layer and the active region has a third highest vertex, with the third highest vertex being higher than the second highest vertex; The top surface of the active region in contact with the gate dielectric layer is higher than the first highest vertex, the second highest vertex, and the third highest vertex.
2. The semiconductor device according to claim 1, characterized in that, include: The recessed region is located between the second isolation layer and the active region, and the inner surface of the recessed region passes sequentially from the first highest vertex through the second highest vertex and the third highest vertex.
3. A semiconductor device according to claim 1, characterized in that, The upper surface of the first isolation layer and the upper surface of the third isolation layer are both lower than the upper surface of the second isolation layer and the upper surface of the active region.
4. A semiconductor device according to claim 2, characterized in that, Along a direction parallel to the substrate, twice the width of the recessed region is greater than the width of the second isolation layer.
5. The semiconductor device according to claim 2, characterized in that, The gate dielectric layer also extends to cover the inner side of the recessed region, and the dielectric layer located on the inner side of the recessed region is in direct contact with the upper surface of the first isolation layer and the upper surface of the third isolation layer.
6. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a barrier layer that covers the gate structure and extends to cover the gate dielectric layer on the inner side of the recessed region.
7. The semiconductor device according to claim 1, characterized in that, The gate dielectric layer also covers the upper surface of the second isolation layer.
8. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A barrier layer covers the gate structure and extends to cover the inner side of the recessed region. The barrier layer located on the inner side of the recessed region is in direct contact with the upper surface of the first isolation layer and the upper surface of the third isolation layer.
9. The semiconductor device according to claim 6 or 8, characterized in that, The barrier layer also covers the upper surface of the second isolation layer.
10. A semiconductor device, characterized in that, include: The substrate includes an active region and an isolation trench defined by the active region; The first isolation layer is located on the inner side of the isolation trench; The second isolation layer is located on top of the first isolation layer; A third isolation layer is located between the first isolation layer and the second isolation layer; A gate dielectric layer is located on the substrate; A gate structure is located on the gate dielectric layer; The contact surface between the third isolation layer and the second isolation layer has a first highest vertex, and the contact surface between the third isolation layer and the first isolation layer has a second highest vertex, with the first highest vertex being higher than the second highest vertex; the contact surface between the first isolation layer and the active region has a third highest vertex, with the third highest vertex being higher than the second highest vertex; The recessed region is located between the second isolation layer and the active region, and the inner surface of the recessed region passes sequentially from the first highest vertex through the second highest vertex and the third highest vertex.