A field sequential display array substrate

Abstract

The utility model discloses a field sequential display array substrate, including substrate layer, set up first ITO layer on the substrate layer, set up shading layer on the first ITO layer, set up buffer layer on the shading layer, set up active layer on the buffer layer, first metal layer, set up first insulating layer on the first metal layer, set up second metal layer on the first insulating layer and set up second insulating layer on the second metal layer, set up second ITO layer and third ITO layer on the second insulating layer, the utility model reaches the beneficial effect is: through the prestorage capacitor of forming in first ITO layer and active layer, make the overlapping area of prestorage capacitor that can form increase, make the capacitance value of prestorage capacitor increase, simultaneously prestorage capacitor sets up on signal line and transistor top greatly improved aperture.

Description

Technical Field

[0001] This utility model relates to the field of pixel display technology, and in particular to a field sequence display array substrate. Background Technology

[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, improving light source utilization and reducing power consumption. The backlight can only be turned on after all image data has been written and the liquid crystal has reached a stable state; otherwise, image distortion will occur. Therefore, a significant time must be allowed for the liquid crystal to deflect before the backlight is activated. This makes it difficult to achieve high brightness and high frequency display over an average time, while also increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.

[0003] To ensure image consistency, existing field-sequence driving circuits for intra-pixel capacitors are used. These circuits are primarily found in OLED and Micro-LED display devices. On one hand, the storage capacitor capacity is relatively small; on the other hand, they are self-emissive structures, having minimal impact on the pixel aperture. However, for field-sequence displays with transmissive light sources, the size of the storage capacitor compresses the aperture ratio. When applied to high-PPI small-size products such as AR / VR, the smaller pixel capacitor may exhibit unpredictable voltage accuracy due to weak voltage maintenance and leakage current. Therefore, balancing capacitor size and aperture ratio is a key technological bottleneck affecting future high-PPI product applications.

[0004] Therefore, this utility model proposes a liquid crystal display panel, a field sequence display array substrate and its preparation method, which increases the capacitance value and improves the aperture ratio. Utility Model Content

[0005] The purpose of this invention is to propose a field-sequence display array substrate that improves capacitance and aperture ratio.

[0006] The purpose of this utility model is to achieve a field-sequence display array substrate through the following technical solution, characterized in that it includes: a substrate layer, a first ITO layer, a light-shielding layer, a buffer layer, an active layer, a first metal layer, a second metal layer, a second ITO layer and a third ITO layer disposed sequentially; A first ITO layer is formed on the substrate, the first ITO layer including the lower electrode of the pre-storage capacitor; the substrate is a glass substrate; A light-shielding layer is formed in the first ITO layer; A buffer layer is formed on the light-shielding layer, an active layer is formed on the buffer layer, and a channel region, a first terminal, and a second terminal of a transistor are formed on the active layer. At the same time, an upper plate of a pre-storage capacitor is formed on the active layer, and the buffer layer is used as the dielectric layer of the pre-storage capacitor. A first metal layer is formed on the active layer, the first metal layer including the gate of a first transistor and a second transistor; A first insulating layer is formed on the first metal layer; A second metal layer is formed in the first insulating layer; wherein, multiple signal lines are formed on the second metal layer, and the second metal layer also forms the first and second terminals of a transistor; A second insulating layer is formed on the second metal layer; A second ITO layer is formed on the second insulating layer, wherein a storage capacitor and a lower electrode plate of a pixel electrode are formed on the second ITO layer; A third insulating layer is formed on the second ITO layer; A third ITO layer is formed on the third insulating layer, wherein the third ITO layer includes a common signal line, a storage capacitor, and the upper electrode of the pixel electrode.

[0007] Furthermore, the signal lines include row gate signal lines, data signal lines, transfer signal lines, and reference signal lines.

[0008] This utility model has the following advantages: This invention increases the capacitance value of the pre-storage capacitor without affecting the aperture ratio by setting the first ITO layer on the substrate layer and forming a pre-storage capacitor with the active layer. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of this utility model. Detailed Implementation

[0010] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0011] It should be noted that the orientations or positional relationships indicated by terms such as "left" and "right" are based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships commonly used when the product of this utility model is in use, or the orientations or positional relationships commonly understood by those skilled in the art. These terms are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. It should also be noted that, in the absence of conflict, the embodiments and features and technical solutions in the embodiments of this utility model can be combined with each other. Example

[0012] like Figure 1 As shown, this embodiment provides a field-sequence display array substrate. The substrate includes a substrate layer 1, a first ITO layer 2 disposed on the substrate layer 1, a light-shielding layer 3 disposed on the first ITO layer 2, a buffer layer 4 disposed on the light-shielding layer 3, an active layer 5 disposed on the buffer layer 4, a first metal layer 6, a first insulating layer disposed on the first metal layer 6, a second metal layer 7 disposed on the first insulating layer, a second insulating layer disposed on the second metal layer 7, a second ITO layer 8 disposed on the second insulating layer, and a third ITO layer 9 disposed on the second insulating layer. Specifically, a lower electrode of a pre-storage capacitor Cst1 is formed on the first ITO layer 2, an upper electrode of the pre-storage capacitor Cst1 is formed on the active layer 5, a storage capacitor Cst2 and a lower electrode of a pixel electrode Clc are formed on the second ITO layer 8, and an upper electrode of the storage capacitor Cst2 and a pixel electrode Clc is formed on the third ITO layer 9. The third ITO layer 9 also forms a common signal line.

[0013] The method for preparing the field-sequence display array substrate of this embodiment includes: S1. A first ITO layer 2 is formed on the substrate layer 1. The first ITO layer 2 includes the lower electrode of the pre-storage capacitor Cst1. The substrate layer 1 is a glass substrate, which allows the liquid crystal molecules to be neatly arranged along the trenches. S2. A light-shielding layer 3 is formed in the first ITO layer 2. The light-shielding layer 3 is formed by a molybdenum black metal layer to form a light-shielding pattern, which is used to shield the device channel to avoid device leakage and light leakage in non-opening areas. S3. A buffer layer 4 is formed on the light-shielding layer 3, and an active layer 5 is formed on the buffer layer 4. The channel region, first terminal and second terminal of the first transistor are formed on the active layer 5 using a heavy doping process, and the channel region, first terminal and second terminal of the second transistor are also formed. The active layer 5 also serves as the upper plate of the pre-storage capacitor Cst1. S4. A first metal layer 6 is formed on the active layer 5, the first metal layer 6 including the gates of a first transistor and a second transistor; S5. A first insulating layer is formed on the entire surface of the first metal layer 6.

[0014] S6. A second metal layer 7 is formed on the first insulating layer; wherein, a plurality of signal lines are formed on the second metal layer 7; the signal lines include row gate signal lines, transfer signal lines, data signal lines and reference signal lines; the row gate signal lines are connected to the gate of the first transistor through adapter holes, the transfer signal lines are connected to the gate of the second transistor through adapter holes, the data signal lines are connected to the first terminal of the first transistor through adapter holes, and the reference signal lines are connected to the second terminal of the second transistor through adapter holes.

[0015] S6. A second insulating layer is formed on the second metal layer 7.

[0016] S7. A second ITO layer 8 is formed on the second insulating layer, wherein a storage capacitor Cst2 and a lower electrode of a pixel electrode Clc are formed on the second ITO layer 8. S8. A third insulating layer is formed on the second ITO layer 8; a third ITO layer 9 is formed on the third insulating layer, wherein the third ITO layer 9 includes a common signal line, a storage capacitor Cst2, and the upper electrode of the pixel electrode Clc. The entire surface of the third ITO layer 9 provides a common signal and serves as a shield.

[0017] In the prior art, the storage area formed by the pre-storage capacitor Cst1 overlaps between the signal line and the device, which can cause signal crosstalk and lead to voltage inaccuracy. This invention utilizes a first ITO layer 2 disposed on a glass substrate. The first ITO layer 2 and the active layer 5 form the two plates of the pre-storage capacitor Cst1. The capacitors in the storage area are all located below the signal lines and devices, which greatly improves the aperture ratio. Furthermore, in this way, the capacitance value of the pre-storage capacitor Cst1 can still be maintained in a range that is larger than the capacitance value of the pixel electrode Clc, while ensuring that the overlapping area of ​​the pixel electrode Clc is not affected. In some specific embodiments, the capacitance value of the pre-storage capacitor Cst1 is twice the capacitance value of the pixel electrode Clc or the holding capacitor Cst2.

[0018] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from this utility model, and these all fall within the protection scope of this utility model.

Claims

1. A field-sequence display array substrate, characterized in that: The substrate comprises a substrate layer (1), a first ITO layer (2), a light-shielding layer (3), a buffer layer (4), an active layer (5), a first metal layer (6), a second metal layer (7), a second ITO layer (8), and a third ITO layer (9) disposed sequentially. The first ITO layer (2) is disposed on the substrate layer (1), and the first ITO layer (2) includes the lower electrode of the pre-storage capacitor Cst1; A light-shielding layer (3) is sequentially disposed on the first ITO layer (2), the light-shielding layer (3) including a light-shielding pattern; A buffer layer (4) is provided on the light-shielding layer (3), and an active layer (5) is provided on the buffer layer (4). The active layer (5) includes the upper plate of the pre-storage capacitor Cst1. The active layer (5) also constitutes the channel region, the first terminal and the second terminal of the transistor. A first metal layer (6) is disposed on the active layer (5), the first metal layer (6) including the gates of a first transistor and a second transistor; The second metal layer (7) is disposed on the first metal layer (6), and the second metal layer (7) includes multiple signal lines; A second ITO layer (8) is disposed on the second metal layer (7), the second ITO layer (8) including the storage capacitor Cst2 and the lower electrode of the pixel electrode Clc; A third ITO layer (9) is disposed on the second ITO layer (8), the third ITO layer (9) including the storage capacitor Cst2 and the upper plate of the pixel electrode Clc and the common signal line.

2. The field-sequence display array substrate according to claim 1, characterized in that, The signal lines include row gate signal lines, data signal lines, transfer signal lines, and reference signal lines.

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