Back contact solar cells, cell assemblies, and photovoltaic systems
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG AIKO SOLAR ENERGY TECH CO LTD
- Filing Date
- 2025-07-23
- Publication Date
- 2026-08-07
AI Technical Summary
[0003]在相关技术中,背接触太阳能电池的掺杂层和电极均设计在背面,设置在背面的掺杂层对背面光线的寄生吸收较大,导致背接触太阳能电池的双面率较低
[0071] In the back-contact solar cell, battery module, and photovoltaic system of this application embodiment, a first doped layer and a second doped layer are alternately arranged in a first direction, and the first doped layer has a first side and a second side opposite to each other in the first direction. At least one first doped layer has a first slot and a second slot spaced apart along the first direction, and the silicon substrate is exposed through the first slot and the second slot. The first slot penetrates the first side, and the second slot penetrates the second side. Thus, by forming the first slot and the second slot on the first doped layer, the parasitic absorption of light by the first doped layer on the back side can be reduced, improving the absorption efficiency of the back-contact solar cell for back-side light, thereby improving the bifaciality of the back-contact solar cell. Simultaneously, the first slot and the second slot are spaced apart along the first direction, with the first slot penetrating only the first side and the second slot penetrating only the second side, ensuring that the first doped layer does not break at the positions of the first slot and the second slot, thus guaranteeing the carrier collection efficiency.
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Figure CN224611173U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cell technology, and more particularly to a back-contact solar cell, a cell module, and a photovoltaic system. Background Technology
[0002] In solar cells, back-contact solar cells are cells in which both the emitter and base contact electrodes are placed on the back of the cell. The light-receiving surface of this cell is not blocked by any metal electrodes, resulting in higher power generation efficiency.
[0003] In related technologies, the doped layer and electrodes of back-contact solar cells are designed on the back side. The doped layer on the back side has a large parasitic absorption of light from the back side, resulting in a low bifaciality of the back-contact solar cell. Utility Model Content
[0004] This application provides a back-contact solar cell, a battery module, and a photovoltaic system.
[0005] This application is implemented as follows: the back-contact solar cell of this application embodiment includes:
[0006] A silicon substrate having opposing front and back sides; and
[0007] A plurality of first doped layers and a plurality of second doped layers are stacked on the back side, the plurality of first doped layers and the plurality of second doped layers are alternately arranged along a first direction and all extend along a second direction, the second direction intersecting the first direction;
[0008] The first doped layer has a first side and a second side opposite to each other in the first direction. At least one first doped layer has a first cutout and a second cutout formed thereon. The first cutout and the second cutout are spaced apart along the first direction. The first cutout is located on the side where the first side is located and penetrates the first side. The second cutout is located on the side where the second side is located and penetrates the second side. The silicon substrate is exposed from the first cutout and the second cutout.
[0009] In some embodiments, the area of the back surface exposed from the first and second cutouts is a velvety area; and / or
[0010] The area on the back side covered by the first doped layer is the polished area.
[0011] In some embodiments, the length of the first perforated groove in the second direction is 50 μm-500 μm; and / or
[0012] The length of the second hollow groove in the second direction is 50μm-500μm.
[0013] In some embodiments, the number of the first hollow slot and the second hollow slot are both multiple, the multiple first hollow slots are arranged at intervals along the second direction, and the multiple second hollow slots are also arranged at intervals along the second direction;
[0014] Wherein, in the first doped layer, the spacing between two adjacent first hollow slots in the second direction is 50μm-1000μm; and / or
[0015] In the first doped layer, the spacing between two adjacent second hollow slots in the second direction is 50μm-1000μm.
[0016] In some embodiments, the ratio between the sum of the lengths of the first hollow groove in the first direction and the lengths of the second hollow groove in the first direction and the length of the first doped layer in the first direction is 50%-95%.
[0017] In some embodiments, the first cutout groove and the second cutout groove have the same shape and size and are aligned in the first direction.
[0018] In some embodiments, the first hollow groove and the second hollow groove are symmetrically arranged about the center line of the first doped layer.
[0019] In some embodiments, the portion of the first doped layer located between the first and second cutouts has a length of 5 μm-100 μm in the first direction.
[0020] In some embodiments, the first hollowed-out groove and the second hollowed-out groove partially overlap in the first direction; or the first hollowed-out groove and the second hollowed-out groove do not overlap in the first direction.
[0021] In some embodiments, the back-contact solar cell further includes:
[0022] At least a back passivation layer is stacked over the first doped layer and the second doped layer;
[0023] A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer.
[0024] The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.
[0025] In some embodiments, the first gate electrode is located between the first cutout groove and the second cutout groove.
[0026] In some embodiments, the first hollow groove and the second hollow groove have the same shape and size and are aligned in the first direction;
[0027] The first doped layer includes a first main body segment located on both sides of the first cutout and the second cutout in the second direction, and a first connecting segment located between the first cutout and the second cutout in the first direction, wherein the first connecting segment connects two adjacent first main body segments;
[0028] The first grid line electrode is disposed on the first main body segment and the first connecting segment and does not obstruct the first hollow slot and the second hollow slot.
[0029] In some embodiments, all the first doped layers are provided with a plurality of first hollow grooves and a plurality of second hollow grooves, all the first hollow grooves on the back contact solar cell are arranged in a rectangular array, and all the second hollow grooves on the back contact solar cell are also arranged in a rectangular array.
[0030] In some embodiments, the second doped layer has opposing third and fourth sides in the first direction, and at least one second doped layer has a third and a fourth cutout groove formed thereon, the third cutout groove being located on the side where the third side is located and penetrating the third side, the fourth cutout groove being located on the side where the fourth side is located and penetrating the fourth side, and the silicon substrate being exposed from the third and fourth cutout grooves.
[0031] In some embodiments, the area of the back surface exposed from the third and fourth cutouts is a velvety area; and / or
[0032] The area on the back side covered by the second doped layer is the polished area.
[0033] In some embodiments, the length of the third hollowed-out groove in the second direction is 50μm-500μm; and / or
[0034] The length of the fourth hollowed-out groove in the second direction is 50μm-500μm.
[0035] In some embodiments, the number of the third hollow slot and the fourth hollow slot is multiple, the multiple third hollow slots are arranged at intervals along the second direction, and the multiple fourth hollow slots are also arranged at intervals along the second direction;
[0036] In the second doped layer, the spacing between two adjacent third hollow slots in the second direction is 50 μm-1000 μm; and / or
[0037] In the second doped layer, the spacing between two adjacent fourth hollowed-out grooves in the second direction is 50μm-1000μm.
[0038] In some embodiments, the ratio between the sum of the lengths of the third cutout groove and the fourth cutout groove in the first direction and the length of the second doped layer in the first direction is 50%-95%.
[0039] In some embodiments, the third and fourth cutouts have the same shape and size and are aligned in the first direction.
[0040] In some embodiments, the third and fourth hollow slots are symmetrically arranged about the center line of the second doped layer.
[0041] In some embodiments, the portion of the first doped layer located between the third and fourth cutouts has a length of 5 μm-100 μm in the first direction.
[0042] In some embodiments, the third and fourth hollowed-out grooves partially overlap in the first direction; or the third and fourth hollowed-out grooves do not overlap in the first direction.
[0043] In some embodiments, the back-contact solar cell further includes:
[0044] At least a back passivation layer is stacked over the first doped layer and the second doped layer;
[0045] A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer.
[0046] The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.
[0047] In some embodiments, the second grid line electrode is located between the third and fourth cutout slots.
[0048] In some embodiments, the third and fourth hollow slots have the same shape and size and are aligned in the first direction;
[0049] The second doped layer includes a second main body segment located on both sides of the third and fourth cutouts in the second direction, and a second connecting segment located between the third and fourth cutouts in the first direction, wherein the second connecting segment connects two adjacent second main body segments;
[0050] The second grid line electrode is disposed on the second main body segment and the second connecting segment and does not obstruct the third and fourth hollow slots.
[0051] In some embodiments, all the first doped layers are provided with a plurality of the third hollow grooves and a plurality of the fourth hollow grooves, all the third hollow grooves on the back contact solar cell are arranged in a rectangular array, and all the fourth hollow grooves on the back contact solar cell are also arranged in a rectangular array.
[0052] In some embodiments, the first hollow groove, the second hollow groove, the third hollow groove, and the fourth hollow groove all have the same shape and are aligned in the first direction; or
[0053] The first and second hollow slots are aligned in the first direction, and the third and fourth hollow slots are aligned in the first direction, while the third and second hollow slots are staggered in the first direction.
[0054] In some embodiments, the first doped layer is a P-type doped layer and the second doped layer is an N-type doped layer;
[0055] Wherein, the lengths of the first and second hollow slots in the second direction are less than the lengths of the third and fourth hollow slots in the second direction; and / or
[0056] The spacing between two adjacent first hollow slots and the spacing between two adjacent second hollow slots in the first doped layer are both smaller than the spacing between two adjacent third hollow slots and the spacing between two adjacent fourth hollow slots in the second doped layer; and / or
[0057] The lengths of the first and second hollowed-out grooves in the first direction are less than the lengths of the third and fourth hollowed-out grooves in the first direction.
[0058] In some embodiments, the first doped layer is a P-type doped layer and the second doped layer is an N-type doped layer;
[0059] In the adjacent first doped layer and second doped layer, the distribution density of the first and second cutouts on the first doped layer in the second direction is greater than the distribution density of the third and fourth cutouts on the second doped layer in the second direction.
[0060] In some embodiments, the back side of the silicon substrate has a plurality of first serial connection regions and a plurality of second serial connection regions, the plurality of first serial connection regions and the plurality of second serial connection regions being alternately arranged along the second direction and all extending along the first direction. The first serial connection regions are used to provide a first conductive connector electrically connected to the first gate electrode and insulated from the second gate electrode. The second serial connection regions are used to provide a second conductive connector electrically connected to the second gate electrode and insulated from the first gate electrode. The number of first serial connection regions is less than the number of third cutouts and the number of fourth cutouts, and the number of second serial connection regions is less than the number of first cutouts and the number of second cutouts.
[0061] In some embodiments, the first serialization area and the second serialization area do not have the first hollow slot, the second hollow slot, the third hollow slot, and the fourth hollow slot.
[0062] In some embodiments, the first hollow groove and the second hollow groove have the same size in the second direction and are aligned in the first direction, the third hollow groove and the fourth hollow groove have the same size in the second direction and are aligned in the first direction, and the third hollow groove and the second hollow groove are offset from each other in the first direction.
[0063] The first serial connection area corresponds to one of the third and fourth hollow slots, and the second serial connection area corresponds to one of the first and second hollow slots.
[0064] In some embodiments, the length of the third hollow groove corresponding to the first serial connection area in the second direction is greater than the length of the other third hollow grooves in the second direction;
[0065] The length of the first hollowed-out groove corresponding to the second serial connection area in the second direction is greater than the length of the other first hollowed-out grooves in the second direction.
[0066] In some embodiments, in a single first hollow slot, the area covered by the second conductive connector accounts for less than 10% of the total area; and / or, in a single third hollow slot, the area covered by the first conductive connector accounts for less than 10% of the total area.
[0067] In some embodiments, in the thickness direction of the back contact solar cell, a first wire is correspondingly disposed on the first grid electrode, the first wire is welded to the first grid electrode, and a second wire is correspondingly disposed on the second grid electrode, the second wire is welded to the second grid electrode;
[0068] Specifically, in the thickness direction of the back contact solar cell, the first wire and the first hollow groove do not overlap; and / or the second wire and the second hollow groove do not overlap.
[0069] This application also provides a battery assembly, which includes several back-contact solar cells as described in the embodiments of this application.
[0070] This application also provides a photovoltaic system, which includes the above-described battery components.
[0071] In the back-contact solar cell, battery module, and photovoltaic system of this application embodiment, a first doped layer and a second doped layer are alternately arranged in a first direction, and the first doped layer has a first side and a second side opposite to each other in the first direction. At least one first doped layer has a first slot and a second slot spaced apart along the first direction, and the silicon substrate is exposed through the first slot and the second slot. The first slot penetrates the first side, and the second slot penetrates the second side. Thus, by forming the first slot and the second slot on the first doped layer, the parasitic absorption of light by the first doped layer on the back side can be reduced, improving the absorption efficiency of the back-contact solar cell for back-side light, thereby improving the bifaciality of the back-contact solar cell. Simultaneously, the first slot and the second slot are spaced apart along the first direction, with the first slot penetrating only the first side and the second slot penetrating only the second side, ensuring that the first doped layer does not break at the positions of the first slot and the second slot, thus guaranteeing the carrier collection efficiency.
[0072] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0073] Figure 1 This is a schematic diagram of a photovoltaic system module provided in an embodiment of this application;
[0074] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application;
[0075] Figure 3 This is a schematic diagram of the planar structure of a back-contact solar cell provided in an embodiment of this application;
[0076] Figure 4This is a partial structural schematic diagram of the back-contact solar cell provided in an embodiment of this application;
[0077] Figure 5 yes Figure 3 A schematic cross-sectional view of the back-contact solar cell along line VV;
[0078] Figure 6 yes Figure 3 A cross-sectional view of the back-contact solar cell along line VI-VI;
[0079] Figure 7 This is a schematic diagram of the structure of the first doped layer and the first grid electrode of the back contact solar cell provided in the embodiments of this application;
[0080] Figure 8 This is another structural schematic diagram of the first doped layer and the first grid electrode of the back contact solar cell provided in the embodiments of this application;
[0081] Figure 9 This is a schematic diagram of the structure of the second doped layer and the second gate electrode of the back contact solar cell provided in the embodiments of this application;
[0082] Figure 10 This is another schematic diagram of the structure of the second doped layer and the second gate electrode of the back contact solar cell provided in the embodiments of this application;
[0083] Figure 11 This is a schematic diagram of the structure of a back-contact solar cell provided in an embodiment of this application, which is provided with a first conductive connector and a second conductive connector;
[0084] Figure 12 This is another structural schematic diagram of a back-contact solar cell provided in this application embodiment, which is provided with a first conductive connector and a second conductive connector;
[0085] Figure 13 This is another planar structural schematic diagram of the back-contact solar cell provided in the embodiments of this application. Detailed Implementation
[0086] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.
[0087] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0089] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0090] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0091] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0092] Please see Figures 1-2 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment, and the battery module 200 in this application embodiment may include a plurality of back contact solar cells 100 in this application embodiment.
[0093] In embodiments of this application, multiple back-contact solar cells 100 in the battery assembly 200 can be connected in series to form multiple battery strings. These battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual cells can be achieved by welding conductive connectors, or the connection between battery strings can be achieved by busbars. In some embodiments, the battery strings can form a cell array, and then be encapsulated together by a front panel, a front encapsulant film, a rear encapsulant film, and a back panel to form the battery assembly 200.
[0094] Please see Figures 3-6 The back-contact solar cell 100 in this embodiment may include a silicon substrate 10, a plurality of first doped layers 20 and a plurality of second doped layers 30.
[0095] The silicon substrate 10 has a front side 11 and a back side 12. A first doped layer 20 and a second doped layer 30 are both stacked on the back side 12. A plurality of first doped layers 20 and second doped layers 30 are arranged alternately along a first direction and all extend along a second direction, which intersects with the first direction.
[0096] The first doped layer 20 has a first side 201 and a second side 202 opposite to each other in a first direction. Among the plurality of first doped layers 20, at least one first doped layer 20 has a first hollow groove 21 and a second hollow groove 22 formed thereon, and the silicon substrate 10 is exposed from the first hollow groove 21 and the second hollow groove 22.
[0097] Among them, such as Figure 3 As shown, the first hollow groove 21 and the second hollow groove 22 are spaced apart along the first direction. The first hollow groove 21 is located on the side where the first side 201 is located and passes through the first side 201. The second hollow groove 22 is located on the side where the second side 202 is located and passes through the second side 202.
[0098] Specifically, such as Figure 3As shown, the first doped layer 20 and the second doped layer 30 can be alternately arranged along the longitudinal direction of the silicon substrate 10. Trench isolation can be provided between the first doped layer 20 and the second doped layer 30. The first perforated groove 21 and the second perforated groove 22 on the first doped layer 20 are spaced apart along the longitudinal direction. When there are multiple first perforated grooves 21 and multiple second perforated grooves 22, the multiple first perforated grooves 21 are spaced apart along the transverse direction, and the multiple second perforated grooves 22 are also spaced apart along the transverse direction. That is, the first direction can be the longitudinal direction of the back-contact solar cell 100, and the second direction can be the transverse direction of the back-contact solar cell 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, and no specific limitation is made here.
[0099] Please see Figures 3-6 In some embodiments, the back-contact solar cell 100 may further include a back passivation layer 40, a first grid electrode 50, and a second grid electrode 60. The back passivation layer 40 at least covers the first doped layer 20 and the second doped layer 30.
[0100] Specifically, in this application, the back passivation layer 40 can preferably cover the entire back surface 12 and be located above the first doped layer 20, the second doped layer 30 and the portion not covered by the first doped layer 20 and the second doped layer 30. That is to say, the back passivation layer 40 is also covered on the first cutout groove 21, the second cutout groove 22 and other areas not covered by the first doped layer 20 and the second doped layer 30.
[0101] The back passivation layer 40 is the outermost film layer on the back surface 12, and it covers both the first doped layer 20 and the second doped layer 30. In some possible embodiments, the first doped layer 20 and the second doped layer 30 may be arranged alternately along a first direction, and the back passivation layer 40 may also cover the area between them. In general, the back passivation layer 40 may be uniformly covered on the entire back surface 12.
[0102] The first gate electrode 50 is disposed above the first doped layer 20, and the first gate electrode 50 at least partially penetrates the back passivation layer 40 to conduct electricity with the first doped layer 20 (conductive contact). That is, the first gate electrode 50 can penetrate the back passivation layer 40 above the first doped layer 20 at all locations, or it can only penetrate the back passivation layer 40 above the first doped layer 20 at some locations to conduct electricity with the first doped layer 20, thereby achieving carrier collection.
[0103] The second gate electrode 60 is disposed above the second doped layer 30, and the second gate electrode 60 at least partially penetrates the back passivation layer 40 to conduct electricity with the second doped layer 30 (conductive contact). That is, the second gate electrode 60 may penetrate the back passivation layer 40 above the second doped layer 30 at all locations, or it may only penetrate the back passivation layer 40 above the second doped layer 30 at some locations to conduct electricity with the second doped layer 30, thereby achieving carrier collection.
[0104] like Figure 5 and Figure 6 As shown, in some embodiments, the first gate electrode 50 may form a point contact or line contact with the first doped layer 20 through a local opening in the region directly above the first doped layer 20. The second gate electrode 60 may form a point contact or line contact with the second doped layer 30 through a local opening in the region directly above the second doped layer 30.
[0105] It should be noted that in this article, when a certain membrane layer is stacked or covered on a certain surface or a certain area of a certain membrane layer, it can mean that the membrane layer is directly stacked on the surface or a certain membrane layer, or that other membrane layers are disposed between the membrane layer and the surface or membrane layer. Covering is only used to define the specific setting range of the membrane layer.
[0106] In the back-contact solar cell 100, cell module 200, and photovoltaic system 1000 of this application embodiment, the first doped layer 20 and the second doped layer 30 are alternately arranged in a first direction, and the first doped layer 20 has a first side surface 201 and a second side surface 202 opposite to each other in the first direction. At least one first doped layer 20 has a first slot 21 and a second slot 22 spaced apart along the first direction, and the silicon substrate 10 is exposed from the first slot 21 and the second slot 22. The first slot 21 penetrates the first side surface 201, and the second slot 22 penetrates the second side surface 202. Thus, by forming the first slot 21 and the second slot 22 on the first doped layer 20, the parasitic absorption of light by the first doped layer 20 located on the back surface 12 can be reduced, the absorption efficiency of the back-contact solar cell 100 of the back surface 12 can be improved, thereby improving the bifaciality of the back-contact solar cell 100. Meanwhile, the first hollow groove 21 and the second hollow groove 22 are spaced apart along the first direction. The first hollow groove 21 only penetrates the first side 201, and the second hollow groove 22 only penetrates the second side 202. This ensures that the first doped layer 20 will not be broken at the positions of the first hollow groove 21 and the second hollow groove 22, thus guaranteeing the carrier collection efficiency.
[0107] Specifically, in the embodiments of this application, the first doped layer 20 refers to a doped structure with a specific conductivity type, which can be formed by phosphorus diffusion or boron diffusion to form a P-type or N-type semiconductor doped layer, used to form a carrier transport channel. The second doped layer 30 is a doped structure with the opposite conductivity type to the first doped layer 20, constituting a complementary carrier collection path, that is, one of the first doped layer 20 and the second doped layer 30 is a P-type doped layer, and the other is an N-type doped layer. The silicon substrate 10 can be an N-type silicon substrate or a P-type silicon substrate, that is, the doping type of the silicon substrate 10 can be P-type doping or N-type doping, and there is no specific limitation here.
[0108] In some possible embodiments, the first doped layer 20 may be an emitter doped layer, and its doping type may be opposite to that of the silicon substrate 10. The second doped layer 30 may be a base region doped layer, and its doping type may be the same as that of the silicon substrate 10. For example, when the silicon substrate 10 is an N-type silicon substrate, the first doped layer 20 is a P-type doped layer and the second doped layer 30 is an N-type doped layer; when the silicon substrate 10 is a P-type silicon substrate, the first doped layer 20 is an N-type doped layer and the second doped layer 30 is a P-type doped layer.
[0109] The back passivation layer 40 is an insulating dielectric layer covering the back side 12 of the silicon substrate 10, which may be, for example, a film layer of silicon oxide, silicon nitride, or aluminum oxide. The first gate electrode 50 and the second gate electrode 60 are metal conductive electrodes, both of which may be formed using metal materials such as silver paste, copper, or aluminum through processes such as printing, evaporation, or electroplating.
[0110] The silicon substrate 10 being exposed from the first cutout groove 21 and the second cutout groove 22 means that the first doped layer 20 is not present at the first cutout groove 21 and the second cutout groove 22, and a portion of the first doped layer 20 has been removed at the first cutout groove 21 and the second cutout groove 22. Specifically, the first cutout groove 21 and the second cutout groove 22 can be formed on the first doped layer 20 after the complete first doped layer 20 and the second doped layer 30 have been formed on the back side 12 of the silicon substrate 10, by means of laser etching or the like.
[0111] The first hollow groove 21 and the second hollow groove 22 can be regular or irregular shapes such as rectangles, circles, triangles, and hexagons, and there is no specific limitation here. Of course, in order to reduce manufacturing difficulty, they can preferably be regular shapes, such as rectangles. In the embodiments of this application, in order to simplify the laser etching process and reduce the cost of laser etching, the shape and size of the first hollow groove 21 and the second hollow groove 22 can preferably be the same.
[0112] Please see Figure 3In some embodiments, all first doped layers 20 may have a plurality of first hollow grooves 21 and second hollow grooves 22, and all the first hollow grooves 21 on the back contact solar cell 100 may be arranged in a rectangular array, and all the second hollow grooves 22 may also be arranged in a rectangular array.
[0113] Thus, the rectangular array arrangement of the first hollow groove 21 can make the first hollow groove 21 arranged into several columns, and the rectangular array arrangement of the second hollow groove 22 can make the second hollow groove 22 arranged into several columns. When laser etching is used to form the first hollow groove 21 and the second hollow groove 22, the difficulty of the laser etching process can be reduced and the laser etching process can be simplified.
[0114] Please see Figure 4 , Figure 7 as well as Figure 8 In some embodiments, the first gate electrode 50 is located between the first hollowed-out groove 21 and the second hollowed-out groove 22. That is, the first gate electrode 50 is located on the portion of the first doped layer 20 located between the first hollowed-out groove 21 and the second hollowed-out groove 22, and there is no overlap between the first gate electrode 50 and the first hollowed-out groove 21 and the second hollowed-out groove 22.
[0115] In this way, the first grid line electrode 50 can be prevented from blocking the first cutout groove 21 and the second cutout groove 22, thus affecting the bifaciality.
[0116] In some embodiments, the area of the back surface 12 exposed from the first cutout groove 21 and the second cutout groove 22 is a velvety area.
[0117] Thus, the areas exposed from the first slot 21 and the second slot 22 are textured areas, which can reduce the reflection of light on the back side and further improve the bifaciality of the back contact solar cell 100.
[0118] In some embodiments, the area of the back surface 12 covered by the first doped layer 20 is a polished area.
[0119] Thus, setting the area covered by the first doped layer 20 as a polished surface can improve the passivation effect at the first doped layer 20, while also reducing the surface defect density.
[0120] In some embodiments, the length of the first hollow groove 21 in the second direction (i.e., the length of the first hollow groove 21) is 50μm-500μm; and / or the length of the second hollow groove 22 in the second direction (i.e., the length of the second hollow groove 22) is 50μm-500μm.
[0121] Thus, by optimizing the length range of the first hollow groove 21 and the second hollow groove 22, the bifaciality can be improved while minimizing the impact on the carrier collection efficiency due to excessively long carrier collection paths.
[0122] Specifically, in such an embodiment, the length of the first hollow groove 21 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, or 50μm-500μm, and is not limited herein. The length of the second hollow groove 22 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, or 50μm-500μm, and is not limited herein.
[0123] In some embodiments, the ratio between the sum of the width of the first hollow groove 21 in the first direction (i.e., the width of the first hollow groove 21) and the length of the second hollow groove 22 in the first direction (i.e., the width of the first hollow groove 21) (i.e., the sum of the widths of the first hollow groove 21 and the second hollow groove 22) and the width of the first doped layer 20 in the first direction (i.e., the width of the first doped layer 20) is 50%-95%.
[0124] In this way, the sum of the widths of the first and second slots 21 and 22 can be avoided from being too wide, which would result in the width of the first doped layer 20 at the slots 21 and 22 being too small, thus failing to guarantee the carrier collection efficiency. Simultaneously, the portion of the first doped layer 20 located at the slots has sufficient width to accommodate the first gate electrode 50. Furthermore, the sum of the widths of the first and second slots 21 and 22 can be avoided from being too narrow, which would lead to a poor bifaciality improvement. In other words, by reasonably setting this ratio, the relationship between bifaciality and carrier collection efficiency can be effectively balanced, ensuring carrier collection efficiency while improving bifaciality.
[0125] Specifically, in such embodiments, the ratio can be, for example, any value between 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 50%-95%, without any specific limitation.
[0126] In some embodiments, in the first doped layer 20, there are multiple first hollow grooves 21 and multiple hollow grooves 22, with multiple first hollow grooves 21 arranged at intervals along the second direction, and multiple second hollow grooves 22 also arranged at intervals along the second direction.
[0127] In the first doped layer 20, the spacing between two adjacent first hollowed-out grooves 21 in the second direction is 50μm-1000μm; and / or
[0128] The distance between two adjacent second hollowed-out grooves 22 in the second direction is 50μm-1000μm.
[0129] In this way, the distance between two adjacent first hollow slots 21 and the distance between two adjacent second hollow slots 22 can be avoided from being too close, which would result in poor carrier collection efficiency. It can also avoid the distance between two adjacent first hollow slots 21 and the distance between two adjacent second hollow slots 22 being too large, which would result in too few first hollow slots 21 and second hollow slots 22 on a single first doped layer 20, resulting in poor bifaciality improvement.
[0130] Specifically, in such an embodiment, the spacing between two adjacent first hollow slots 21 in the second direction and the spacing between two adjacent second hollow slots 22 in the second direction can be any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm or 50μm-1000μm, and no specific limitation is made here.
[0131] Please see Figure 3 In some embodiments, the first cutout groove 21 and the second cutout groove 22 may have the same shape and size and be aligned in a first direction.
[0132] Thus, the first hollow groove 21 and the second hollow groove 22 have the same shape and size and are located on the same straight line in the first direction. When laser etching is used for removal, laser production capacity can be increased, manufacturing efficiency can be improved, and costs can be reduced.
[0133] Furthermore, in such an embodiment, the first hollow groove 21 and the second hollow groove 22 may be symmetrically arranged about the center line of the first doped layer 20.
[0134] In this way, the portion of the first doped layer 20 located between the first hollow groove 21 and the second hollow groove 22 can be positioned in the center of the first doped layer 20, which facilitates the setting of the first gate electrode 50.
[0135] Furthermore, in some embodiments, the first hollow groove 21 and the second hollow groove 22 have the same shape and size and are aligned in a first direction, and the portion of the first doped layer 20 located between the first hollow groove 21 and the second hollow groove 22 has a length of 5μm-100μm in the first direction.
[0136] In this way, the width of the portion of the first doped layer 20 located between the first hollow groove 21 and the second hollow groove 22 can be avoided from being too narrow, which would not guarantee the carrier collection efficiency and meet the setting requirements of the second gate electrode 50. It can also avoid the poor bifaciality improvement effect caused by the width of the first hollow groove 21 and the second hollow groove 22 being too narrow.
[0137] Specifically, in such an embodiment, the length of the portion of the first doped layer 20 located between the first cutout groove 21 and the second cutout groove 22 in the first direction can be, for example, any value between 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm or 5μm-100μm, without any specific limitation herein.
[0138] Please see Figure 7 In some embodiments, the first cutout groove 21 and the second cutout groove 22 overlap in the first direction.
[0139] In this way, the narrowest part of the first doped layer 20 (i.e., the part located in the overlapping area of the first slot 21 and the second slot 22) can be shorter, thereby improving the carrier collection efficiency.
[0140] Of course, please see Figure 8 In some embodiments, the first hollow groove 21 and the second hollow groove 22 may not overlap in the first direction, that is, the first hollow groove 21 and the second hollow groove 22 may be completely staggered.
[0141] In this way, the width of the narrowest part of the first doped layer 20 can be ensured to be not too narrow, thereby improving the carrier collection efficiency.
[0142] Please see Figure 4 In some embodiments, the first hollow groove 21 and the second hollow groove 22 have the same shape and size and are aligned in a first direction. The first doped layer 20 may include a first main body segment 23 located on both sides of the first hollow groove 21 and the second hollow groove 22 in a second direction, and a first connecting segment 24 located on the first hollow groove 21 and the second hollow groove 22. The width of the first connecting segment 24 is smaller than the width of the first main body segment 23, and the first connecting segment 24 connects two adjacent first main body segments 23. The first gate electrode 50 may be disposed on the first main body segment 23 and the first connecting segment 24 and does not obstruct the first hollow groove 21 and the second hollow groove 22.
[0143] Thus, by placing the first grid line electrode 50 on the first main body section 23 and the first connecting section 24, the first grid line electrode 50 can be prevented from blocking the first hollow groove 21 and the second hollow groove 22, thereby affecting the double-sided ratio.
[0144] Please see Figure 3 and Figure 4 In some embodiments, the second doped layer 30 has a third side 301 and a fourth side 302 opposite to each other in a first direction. In a plurality of second doped layers 30, at least one second doped layer 30 has a third cutout groove 31 and a fourth cutout groove 32 formed thereon. The third cutout groove 31 is located on the side where the third side 301 is located and penetrates the third side 301. The fourth cutout groove 32 is located on the side where the fourth side 302 is located and penetrates the fourth side 302. The silicon substrate 10 is exposed from the third cutout groove 31 and the fourth cutout groove 32.
[0145] The silicon substrate 10 being exposed from the third and fourth cutouts 31 and 32 means that the second doped layer 30 is not present at the third and fourth cutouts 31 and 32, and a portion of the second doped layer 30 has been removed at the third and fourth cutouts 31 and 32. Specifically, the third and fourth cutouts 31 and 32 can be formed on the second doped layer 30 after a complete second doped layer 30 has been formed on the back side 12 of the silicon substrate 10, by means of laser etching or the like.
[0146] The shapes of the third hollow groove 31 and the fourth hollow groove 32 can be regular or irregular shapes such as rectangles, circles, triangles, and hexagons, and there is no specific limitation here. Of course, to reduce manufacturing difficulty, regular shapes, such as rectangles, are preferred. The shapes of the third hollow groove 31 and the fourth hollow groove 32 can be the same as or different from the shapes of the first hollow groove 21 and the second hollow groove 22, and there is no specific limitation here. In the embodiments of this application, in order to simplify the laser etching process and reduce the cost of laser etching, the shapes and dimensions of the third hollow groove 31 and the fourth hollow groove 32 are preferably the same.
[0147] Thus, by creating the third hollow groove 31 and the fourth hollow groove 32 on the second doped layer 30, the parasitic absorption of light by the second doped layer 30 located on the back side 12 can be reduced, improving the absorption efficiency of the back contact solar cell 100 on the back side 12, thereby increasing the bifaciality of the back contact solar cell 100. Simultaneously, the third hollow groove 31 and the fourth hollow groove 32 are spaced apart along the first direction, with the third hollow groove 31 penetrating only the third side 301 and the fourth hollow groove 32 penetrating only the fourth side 302. This ensures that the second doped layer 30 does not break at the positions of the third hollow groove 31 and the fourth hollow groove 32, guaranteeing the carrier collection efficiency.
[0148] Please see Figure 3In some embodiments, all second doped layers 30 may have a plurality of third hollow grooves 31 and fourth hollow grooves 32, and all the third hollow grooves 31 on the back contact solar cell 100 may be arranged in a rectangular array, and all the fourth hollow grooves 32 may also be arranged in a rectangular array.
[0149] Thus, the rectangular array arrangement of the third hollow groove 31 can make the third hollow groove 31 arranged into several columns, and the rectangular array arrangement of the fourth hollow groove 32 can make the fourth hollow groove 32 arranged into several columns. When laser etching is used to form the third hollow groove 31 and the fourth hollow groove 32, the difficulty of the laser etching process can be reduced and the laser etching process can be simplified.
[0150] Please see Figure 3 , Figure 4 as well as Figure 9 and Figure 10 In some embodiments, the second gate electrode 60 is located between the third cutout groove 31 and the fourth cutout groove 32. That is, the second gate electrode 60 is located on the portion of the second doped layer 30 located between the third cutout groove 31 and the fourth cutout groove 32, and there is no overlap between the second gate electrode 60 and the third cutout groove 31 and the fourth cutout groove 32.
[0151] In this way, the second grid line electrode 60 can be prevented from blocking the third cutout groove 31 and the fourth cutout groove 32, thus affecting the bifaciality.
[0152] In some embodiments, the area of the back surface 12 exposed from the third cutout groove 31 and the fourth cutout groove 32 is a velvety area.
[0153] Thus, the areas exposed from the third and fourth perforated slots 31 and 32 are textured areas, which can reduce the reflection of light on the back side and further improve the bifaciality of the back contact solar cell 100.
[0154] In some embodiments, the area of the back surface 12 covered by the second doped layer 30 is a polished area.
[0155] Thus, setting the area covered by the second doped layer 30 as a polished surface can improve the passivation effect at the second doped layer 30, while also reducing the surface defect density.
[0156] In some embodiments, the length of the third hollow groove 31 in the second direction (i.e., the length of the third hollow groove 31) is 50μm-500μm; and / or the length of the fourth hollow groove 32 in the second direction (i.e., the length of the fourth hollow groove 32) is 50μm-500μm.
[0157] Thus, by optimizing the length range of the third hollow groove 31 and the fourth hollow groove 32, the bifaciality can be improved while minimizing the impact on the carrier collection efficiency due to excessively long carrier collection paths.
[0158] Specifically, in such an embodiment, the length of the third hollow groove 31 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, or 50μm-500μm, and is not limited herein. The length of the fourth hollow groove 32 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, or 50μm-500μm, and is not limited herein.
[0159] In some embodiments, the ratio between the sum of the width of the third hollow groove 31 in the first direction (i.e., the width of the third hollow groove 31) and the length of the fourth hollow groove 32 in the first direction (i.e., the width of the third hollow groove 31) (i.e., the sum of the widths of the third hollow groove 31 and the fourth hollow groove 32) and the width of the second doped layer 30 in the first direction (i.e., the width of the second doped layer 30) is 50%-95%.
[0160] In this way, the sum of the widths of the third and fourth slots 31 and 32 can be avoided from being too wide, which would result in the width of the second doped layer 30 at the third and fourth slots 31 and 32 being too small, thus failing to guarantee the carrier collection efficiency. At the same time, it can also ensure that the portion of the second doped layer 30 located at the slots has sufficient width to accommodate the second gate electrode 60. Furthermore, it can also prevent the sum of the widths of the third and fourth slots 31 and 32 from being too narrow, which would lead to a poor bifaciality improvement effect. In other words, by reasonably setting this ratio, the relationship between bifaciality and carrier collection efficiency can be effectively balanced, ensuring carrier collection efficiency while improving bifaciality.
[0161] Specifically, in such embodiments, the ratio can be, for example, any value between 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 50%-95%, without any specific limitation.
[0162] In some embodiments, in the second doped layer 30, there are multiple third hollow grooves 31 and multiple fourth hollow grooves 32, with the multiple third hollow grooves 31 arranged at intervals along the second direction and the multiple fourth hollow grooves 32 also arranged at intervals along the second direction.
[0163] In the second doped layer 30, the spacing between two adjacent third hollow grooves 31 in the second direction is 50 μm-1000 μm; and / or
[0164] The distance between two adjacent fourth hollow slots 32 in the second direction is 50μm-1000μm.
[0165] In this way, the distance between two adjacent third hollow slots 31 and the distance between two adjacent fourth hollow slots 32 can be avoided, which would result in poor carrier collection efficiency. It can also avoid the distance between two adjacent third hollow slots 31 and the distance between two adjacent fourth hollow slots 32 being too large, which would result in too few third hollow slots 31 and fourth hollow slots 32 on a single second doped layer 30, resulting in poor bifaciality improvement.
[0166] Specifically, in such an embodiment, the spacing between two adjacent third hollow slots 31 in the second direction and the spacing between two adjacent fourth hollow slots 32 in the second direction can be any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm or 50μm-1000μm, and no specific limitation is made here.
[0167] Please see Figure 3 and Figure 4 In some embodiments, the third cutout groove 31 and the fourth cutout groove 32 are the same in shape and size and are aligned in the first direction.
[0168] Thus, the third hollow groove 31 and the fourth hollow groove 32 are identical in shape and size and are located on the same straight line in the first direction. When laser etching is used for removal, laser production capacity can be increased, manufacturing efficiency can be improved, and costs can be reduced.
[0169] Furthermore, in such an embodiment, the third hollow groove 31 and the fourth hollow groove 32 may be symmetrically arranged about the center line of the second doped layer 30.
[0170] In this way, the portion of the second doped layer 30 located between the third hollow groove 31 and the fourth hollow groove 32 can be positioned in the center of the second doped layer 30, which facilitates the setting of the second gate electrode 60.
[0171] Furthermore, in some embodiments, the third hollow groove 31 and the fourth hollow groove 32 have the same shape and size and are aligned in the first direction, and the portion of the second doped layer 30 located between the third hollow groove 31 and the fourth hollow groove 32 has a length of 5μm-100μm in the first direction.
[0172] In this way, the width of the portion of the second doped layer 30 located between the third hollow groove 31 and the fourth hollow groove 32 is avoided from being too narrow, which would prevent the carrier collection efficiency from being compromised and the setting requirements of the second gate electrode 50 from being met. It also avoids the poor bifaciality improvement effect caused by the width of the third hollow groove 31 and the fourth hollow groove 32 being too narrow.
[0173] Specifically, in such an embodiment, the length of the portion of the second doped layer 30 located between the third cutout groove 31 and the fourth cutout groove 32 in the first direction can be, for example, any value between 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm or 5μm-100μm, without any specific limitation herein.
[0174] Please see Figure 9 In some embodiments, the third cutout groove 31 and the fourth cutout groove 32 partially overlap in the first direction.
[0175] This allows the narrowest part of the second doped layer 30 (i.e., the part located in the overlapping area of the third slot 31 and the fourth slot 32) to be shorter, thereby improving the carrier collection efficiency.
[0176] Of course, please see Figure 10 In some embodiments, the third hollow groove 31 and the fourth hollow groove 32 may not overlap in the first direction, that is, the third hollow groove 31 and the fourth hollow groove 32 are completely staggered.
[0177] In this way, the width of the narrowest part of the second doped layer 30 can be ensured to be not too narrow, thereby improving the carrier collection efficiency.
[0178] Please see Figure 4 In some embodiments, the third and fourth cutouts 31 and 32 are identical in shape and size and aligned in a first direction. The second doped layer 30 may include second main body segments 33 located on both sides of the third and fourth cutouts 31 and 32 in a second direction, and second connecting segments 34 located on the third and fourth cutouts 31 and 32. The width of the second connecting segments 34 is smaller than the width of the second main body segments 33, and the second connecting segments 34 connect two adjacent second main body segments 33. The second gate electrode 60 may be disposed on the second main body segments 33 and the second connecting segments 34 and does not obstruct the third and fourth cutouts 31 and 32.
[0179] Thus, by placing the second grid line electrode 60 on the second main body section 33 and the second connecting section 34, the second grid line electrode 60 can be prevented from blocking the third cutout groove 31 and the fourth cutout groove 32, thereby affecting the bifaciality.
[0180] Please see Figure 3 and Figure 4 In some possible embodiments, the first hollow groove 21, the second hollow groove 22, the third hollow groove 31 and the fourth hollow groove 32 are all the same shape and are aligned in the first direction.
[0181] Thus, on the back contact solar cell 100, the first hollow groove 21, the second hollow groove 22, the third hollow groove 31 and the fourth hollow groove 32 are arranged in a rectangular array. In the laser etching process of the manufacturing process, the process can be simplified, the laser production capacity can be increased and the cost can be reduced.
[0182] Of course, please see Figure 12 In other embodiments, the first hollow groove 21 and the second hollow groove 22 may be aligned in the first direction, and the third hollow groove 31 and the fourth hollow groove 32 may be aligned in the first direction and the third hollow groove 31 and the second hollow groove 22 may be staggered in the first direction. No specific restrictions are imposed here.
[0183] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the lengths of the first slot 21 and the second slot 22 in the second direction are less than the lengths of the third slot 31 and the fourth slot 32 in the second direction.
[0184] That is, the length of the first hollow groove 21 in the second direction is less than the length of the third hollow groove 31 in the second direction and the length of the fourth hollow groove 32 in the second direction, and the length of the second hollow groove 22 in the second direction is also less than the length of the third hollow groove 31 in the second direction and the length of the fourth hollow groove 32 in the second direction.
[0185] Thus, the P-type doped layer has a poor ability to collect carriers. By making the lengths of the first and second hollowed-out grooves 21 and 22 shorter than the lengths of the third and fourth hollowed-out grooves 31 and 32, the carrier collection path of the first doped layer 20 can be shortened, thereby improving the carrier collection efficiency of the first doped layer 20 and avoiding excessive carrier loss due to excessive lengths of the first and second hollowed-out grooves 21 and 22.
[0186] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the spacing between two adjacent first slots 21 and the spacing between two adjacent second slots 22 in the first doped layer 20 are both smaller than the spacing between two adjacent third slots 31 and the spacing between two adjacent fourth slots 32 in the second doped layer 30.
[0187] That is, the spacing between two adjacent first hollow slots 21 in the first doped layer 20 is smaller than the spacing between two adjacent third hollow slots 31 and two adjacent fourth hollow slots 32 in the second doped layer 30. The spacing between two adjacent second hollow slots 22 in the first doped layer 20 is also smaller than the spacing between two adjacent third hollow slots 31 and two adjacent fourth hollow slots 32 in the second doped layer 30.
[0188] Thus, the carrier collection capability of the P-type doped layer is poor. By setting the spacing between the first hollow groove 21 and the second hollow groove 22 in the first doped layer 20 to be smaller, the carrier collection efficiency of the first doped layer 20 can be improved.
[0189] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the lengths of the first slot 21 and the second slot 22 in the first direction (i.e., the widths of the first slot 21 and the second slot 22) are less than the widths of the lengths of the third slot 31 and the fourth slot 32 in the first direction (i.e., the widths of the third slot 31 and the fourth slot 32).
[0190] That is, the width of the first hollow groove 21 is smaller than the width of the third hollow groove 31 and the fourth hollow groove 32, and the width of the second hollow groove 22 is also smaller than the width of the third hollow groove 31 and the fourth hollow groove 32.
[0191] Thus, the carrier collection capability of the P-type doped layer is poor. By setting the width of the first slot 21 and the second slot 22 in the first doped layer 20 to be smaller, the carrier collection efficiency of the first doped layer 20 can be improved.
[0192] In some embodiments, the doping type of the first doped layer 20 is opposite to that of the silicon substrate 10, and the doping type of the second doped layer 30 is the same as that of the silicon substrate 10. The sum of the projected areas of all the first doped layers 20 on the back surface 12 is greater than the sum of the projected areas of all the second doped layers 30 on the back surface 12. That is, the first doped layer 20 serves as the emitter doped layer, the second doped layer 30 serves as the base doped layer, and the total area of the emitter doped layer is greater than the total area of the base doped layer.
[0193] Thus, the emitter doped layer has a larger area, which can improve the efficiency of the back contact solar cell 100.
[0194] In some embodiments, the first doped layer 20 is a P-type doped layer and the second doped layer 30 is an N-type doped layer. In adjacent first doped layers 20 and second doped layers 30, the distribution density of the first slot 21 and the second slot 22 in the first doped layer 20 in the second direction is greater than the distribution density of the third slot 31 and the fourth slot 32 in the second doped layer 30 in the second direction.
[0195] That is, the distribution density of the first hollow groove 21 in the first doped layer 20 in the second direction is greater than the distribution density of the third hollow groove 31 in the second direction and the distribution density of the fourth hollow groove 32 in the second direction in the second doped layer 30, and the distribution density of the second hollow groove 22 in the first doped layer 20 in the second direction is greater than the distribution density of the third hollow groove 31 in the second direction and the distribution density of the fourth hollow groove 32 in the second direction in the second doped layer 30.
[0196] It should be noted that "distribution density in the second direction" refers to the number of perforated grooves per unit length (in mm) in the second direction. That is to say, within the same length range, the number of the first perforated groove 21 is greater than the number of the third perforated groove 31 and the fourth perforated groove 32, and the number of the second perforated groove 22 is also greater than the number of the third perforated groove 31 and the fourth perforated groove 32.
[0197] Thus, by setting the density of the slots on the P-type doped layer to be relatively dense, the carrier collection efficiency of the first doped layer 20 can be improved.
[0198] Specifically, the carrier collection capability of the first doped layer 20 of the P-type doped type is relatively poor. If the slots on the first doped layer 20 are arranged too dispersedly, the carrier collection efficiency will be even worse. Therefore, by setting it in this way, the carrier collection efficiency of the first doped layer 20 can be improved.
[0199] Furthermore, in such an embodiment, in the first doped layer 20, the distribution density of the first hollow groove 21 and the second hollow groove 22 in the second direction is 3-60 per mm;
[0200] In the second doped layer 30, the distribution density of the third hollow groove 31 and the fourth hollow groove 32 in the second direction is 2-50 per mm.
[0201] Thus, by controlling the distribution density of the first and second perforated slots 21 and 22, and the third and fourth perforated slots 31 and 32 within the aforementioned ranges, the collection efficiency of holes and electrons can be guaranteed, avoiding excessively low collection efficiencies that would affect overall efficiency. In other words, this configuration balances the relationship between bifaciality and carrier collection efficiency, ensuring the efficiency of the back-contact solar cell 100 while improving bifaciality.
[0202] Please see Figure 11 and Figure 12 In some embodiments, the back surface 12 of the silicon substrate 10 has a plurality of first serial regions 101 and a plurality of second serial regions 102, the plurality of first serial regions 101 and the plurality of second serial regions 102 being alternately arranged along a second direction and all extending along a first direction.
[0203] The first series connection area 101 is used to set a first conductive connector 70 that is electrically connected to the first grid line electrode 50 and insulated from the second grid line electrode 60. The second series connection area 102 is used to set a second conductive connector 80 that is electrically connected to the second grid line electrode 60 and insulated from the first grid line electrode 50. The number of first series connection areas 101 is less than the number of third hollow slots 31 and the number of fourth hollow slots 32. The number of second series connection areas 102 is less than the number of first hollow slots 21 and the number of second hollow slots 22.
[0204] Thus, the series connection between the back-contact solar cells 100 can be achieved through the first conductive connector 70 and the second conductive connector 80.
[0205] Specifically, the first series connection area 101 refers to a specific area on the back side 12 of the silicon substrate 10 used to set the first conductive connector 70 (e.g., main gate and / or solder ribbon). By setting the first conductive connector 70 at the first series connection area 101, conductive contact with the first gate electrode 50 is achieved. The second series connection area 102 refers to a specific area on the back side 12 of the silicon substrate 10 used to set the second conductive connector 80 (e.g., solder ribbon). By setting the second conductive connector 80 at the second series connection area 102, conductive contact with the second gate electrode 60 is achieved, thereby realizing the overall current conduction. The number of first series connection areas 101 is less than the number of third cutouts 31 and fourth cutouts 32, and the number of second series connection areas 102 is less than the number of first cutouts 21 and second cutouts 22. This avoids the risk of leakage caused by an overly dense arrangement of the first conductive connector 70 and the second conductive connector. When the back contact solar cell 100 is a gridless back contact solar cell, both the first conductive connector 70 and the second conductive connector 90 can be solder ribbons. When the back contact solar cell 100 is a grid-connected back contact solar cell, the first conductive connector 70 and the second conductive connector 80 are the grid and the solder ribbon, respectively.
[0206] In some possible embodiments, in order to achieve insulation between the first conductive connector 70 and the second gate electrode 60, insulating adhesive can be provided at the position where the second gate electrode 60 overlaps with the first series connection area 101. In order to achieve insulation between the second conductive connector 80 and the first gate electrode 50, insulating adhesive can be provided at the position where the first gate electrode 50 overlaps with the second series connection area 102.
[0207] Of course, in some embodiments, in order to achieve insulation between the first conductive connector 70 and the second gate electrode 60 and insulation between the second conductive connector 80 and the first gate electrode 50, the second gate electrode 60 can be set to be disconnected at the first serial connection area 101 and the first gate electrode 50 can be set to be disconnected at the second serial connection area 102.
[0208] Please see Figure 11 In some embodiments, the first serial connection area 101 and the second serial connection area 102 do not have the first hollow groove 21, the second hollow groove 22, the third hollow groove 31 and the fourth hollow groove 32.
[0209] Thus, after the component is formed, the first conductive connector 70 in the first serial connection area 101 and the second conductive connector 80 in the second serial connection area 102 will not block the first hollow groove 21, the second hollow groove 22, the third hollow groove 31 and the fourth hollow groove 32, thereby ensuring the double-sidedness of the component.
[0210] Of course, please see Figure 12 In some embodiments, the first hollow groove 21 and the second hollow groove 22 have the same size in the second direction and are aligned in the first direction, the third hollow groove 31 and the fourth hollow groove 32 have the same size in the second direction and are aligned in the first direction, and the third hollow groove 31 and the second hollow groove 22 are staggered in the first direction.
[0211] The first serial connection area 101 corresponds to a third hollow groove 31 and a fourth hollow groove 32, and the second serial connection area 102 corresponds to a first hollow groove 21 and a second hollow groove 22.
[0212] Specifically, in this embodiment, the first gate electrode 50 can be disconnected at the first slot 21 and the second slot 22 corresponding to the second serial connection area 102, and the second gate electrode 60 can be disconnected at the third slot 31 and the fourth slot 32 corresponding to the first serial connection area 101. The first serial connection area 101 corresponds to one third slot 31 and one fourth slot 32; that is, each first serial connection area 101 corresponds to one third slot 31 and one fourth slot 32, and the positions corresponding to a portion of the third slot 31 and the fourth slot 32 are the first serial connection areas 101. The second serial connection area 102 corresponds to one first slot 21 and one second slot 22; that is, each second serial connection area 102 corresponds to one first slot 21 and one second slot 22, and the positions corresponding to a portion of the first slot 21 and the second slot 22 are the second serial connection areas 102.
[0213] In this way, a portion of the first hollowed-out groove 21 and the second hollowed-out groove 22 can be used as the second serial connection area 102, and a portion of the third hollowed-out groove 31 and the fourth hollowed-out groove 32 can be used as the first serial connection area 101. It is only necessary to set the first grid line electrode 50 to be discontinuous in the portion of the first hollowed-out groove 21 and the second hollowed-out groove 22, and set the second grid line electrode 60 to be discontinuous in the portion of the third hollowed-out groove 31 and the fourth hollowed-out groove 32 to achieve insulation between the grid line electrode and the conductive connectors of different polarities.
[0214] Furthermore, in such an embodiment, the length of the third hollow groove 31 corresponding to the first serial connection area 101 in the second direction may be greater than the length of the other third hollow grooves 31 in the second direction.
[0215] The length of the first hollowed-out groove 21 corresponding to the second serial connection area 102 in the second direction can be greater than the length of the other first hollowed-out grooves 21 in the second direction.
[0216] Thus, making the slots for setting the conductive connectors wider allows them to accommodate wider main grids and / or solder strips without the need for extremely fine main grids and / or solder strips, reducing the difficulty of the manufacturing process.
[0217] In some embodiments, in a single first hollow groove 21, the area covered by the second conductive connector 80 accounts for less than 10% of the total area. That is, the ratio between the area of the first hollow groove 21 covered by the second conductive connector 80 and the total area of the first hollow groove 21 is less than 10%, such as 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, or other values less than 10%, which are not specifically limited herein; and / or, in a single third hollow groove 31, the area covered by the first conductive connector 70 accounts for less than 10% of the total area. That is, the ratio between the area of the third hollow groove 31 covered by the first conductive connector 70 or the second conductive connector 80 and the total area of the third hollow groove 31 is less than 10%, such as 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, or other values less than 10%, which are not specifically limited herein.
[0218] Thus, when the first conductive connector 70 and the second conductive connector 80 are respectively disposed at the first hollow groove 21 and the third hollow groove 31, the proportion of the area of the first hollow groove 21 and the third hollow groove 31 that is blocked is set to be less than 10%. This can avoid the first conductive connector 70 and the second conductive connector 80 blocking too large an area, which would result in a poor double-sidedness improvement effect.
[0219] Specifically, in such an embodiment, the first hollow groove 21 and the third hollow groove 31 may be aligned in the first direction, and the first conductive connector 70 and the second conductive connector 80 may each have a corresponding first hollow groove 21, a second hollow groove 22, a third hollow groove 31 and a fourth hollow groove 32. The second grid electrode 60 is disconnected at the first series connection area 101 where the first conductive connector 70 is provided, or an insulating adhesive is provided at that location. The first grid electrode 50 is disconnected at the second series connection area 102 where the second conductive connector 80 is provided, or an insulating adhesive is provided at that location.
[0220] Of course, in some embodiments, the first hollow groove 21 and the third hollow groove 31 may be staggered in the first direction, and the position of the first conductive connector 70 may only have the third hollow groove 31 and the fourth hollow groove 32. The second grid electrode 60 may be disconnected at the first series connection area 101 corresponding to the first conductive connector 70 or may have insulating glue at that position. The position of the second conductive connector 80 may only have the first hollow groove 21 and the second hollow groove 22, and the first grid electrode 50 may be disconnected at the second series connection area 102 corresponding to the second conductive connector 80 or may have insulating glue at that position.
[0221] In some embodiments, in the same first doped layer 20, the proportion of first hollowed-out grooves 21 that are at least partially blocked by the first conductive connector 70 or the second conductive connector 80 is less than 50%; and / or
[0222] In the same second doped layer 30, the number of third hollow grooves 31 that are at least partially blocked by the first conductive connector 70 or the second conductive connector 80 accounts for less than 50%.
[0223] Thus, by controlling the number of the first cutout groove 21 and the third cutout groove 31 that are blocked to less than 50%, the double-sided ratio can be effectively improved.
[0224] Specifically, in such embodiments, the percentage of the number of first hollow slots 21 at least partially blocked by the first conductive connector 70 or the second conductive connector 80 may be, for example, 49%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, or other values less than 50%, and no specific limitation is imposed here. Similarly, in such embodiments, the percentage of the number of third hollow slots 31 at least partially blocked by the first conductive connector 70 or the second conductive connector 80 may be, for example, 49%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, or other values less than 50%, and no specific limitation is imposed here.
[0225] In some embodiments, the first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer. Specifically, in adjacent first doped layers 20 and second doped layers 30, the number of first slots 21 and second slots 22 that are at least partially blocked by the first conductive connector 70 and the second conductive connector 80 is greater than the number of third slots 31 and fourth slots 32 that are at least partially blocked by the first conductive connector 70 and the second conductive connector 80.
[0226] This configuration allows for a higher distribution density of the first and second slots 21 on the P-type doped layer, which can improve the carrier collection efficiency.
[0227] In some embodiments, the back surface 12 of the silicon substrate 10 may not have a first series connection region 101 and a second series connection region 102, but instead, a first wire is correspondingly provided on each first gate electrode 50, and a second wire is correspondingly provided on each second gate electrode 60. That is, in the thickness direction of the back contact solar cell 100, a first wire is correspondingly provided on the first gate electrode 50 and the first wire is welded to the first gate electrode 50, and a second wire is correspondingly provided on the second gate electrode 60 and the second wire is welded to the second gate electrode 60;
[0228] In this case, in the thickness direction of the back contact solar cell 100, the first conductor does not overlap with the first slot 21 and the second slot 22; and / or the second conductor does not overlap with the third slot 31 and the fourth slot 32.
[0229] Specifically, in this embodiment, each first doped layer 20 is provided with a first grid electrode 50 and a first conductive wire, and each second doped layer 30 is provided with a second grid electrode 60 and a second conductive wire. That is, the first conductive wire is stacked on the first grid electrode 50, and the second conductive wire is stacked on the second grid electrode 60. In the battery assembly 200, the back-contact solar cells 100 in the battery string are connected in series through the first conductive wire and the second conductive wire.
[0230] In this way, the back-contact solar cells 100 in the battery string can be directly connected in series through the first and second conductors stacked on the grid electrodes, without the need for additional first conductive connectors 70 and second conductive connectors 80 as described above. This reduces the area of the back side 12 that is blocked and improves the bifaciality. At the same time, the first and second conductors will not block the first and second hollow slots 21 and 22, the third and fourth hollow slots 31, further improving the bifaciality.
[0231] Please see Figure 13 In some embodiments, the first doped layer 20 and the second doped layer 30 are arranged alternately along a first direction and both extend along a second direction. Figure 13 In the illustrated embodiment, the first direction is the lateral direction of the back-contact solar cell 100, and the second direction is the longitudinal direction of the back-contact solar cell 100. In this embodiment, the back-contact solar cell 100 may further include a third doped layer 110 and a fourth doped layer 120 arranged alternately along the second direction, and both the third doped layer 110 and the fourth doped layer 120 extend along the first direction. The third doped layer 110 is connected to the first doped layer 20 and disconnected at the second doped layer 30, and the third doped layer 110 and the first doped layer 20 have the same doping type. The fourth doped layer 120 is connected to the second doped layer 30 and disconnected at the first doped layer 20, and the fourth doped layer 120 and the second doped layer 30 have the same doping type. Figure 13 As shown, the first doped layer 20 and the third doped layer 110 constitute doped layers of the same polarity, while the second doped layer 30 and the fourth doped layer 120 constitute doped layers of the opposite polarity. The first slot 21 and the second slot 22 can be formed in... Figure 13 On the first doped layer 20 shown, the third cutout groove 31 and the fourth cutout groove 32 can be formed. Figure 13 On the second doped layer 30 shown.
[0232] Specifically, in some possible embodiments, in Figure 13 Fine gates can be provided on the third doped layer 110 and the fourth doped layer 120, and main gates can be provided on the first doped layer 20 and the second doped layer 30. The main gate on the first doped layer 20 is connected to the fine gate on the third doped layer 110, and the main gate on the second doped layer 30 is connected to the fine gate on the fourth doped layer 120.
[0233] In some possible embodiments, the main gate on the first doped layer 20 may not overlap with the first cutout 21 and the second cutout 22; that is, in the thickness direction, the main gate on the first doped layer 20 does not overlap with the first cutout 21 and the second cutout 22. This avoids the main gate obstructing the first cutout 21 and the second cutout 22.
[0234] In some embodiments, the main gate on the second doped layer 30 may not overlap with the third cutout 31 and the fourth cutout 32; that is, in the thickness direction, the main gate on the second doped layer 30 does not overlap with the third cutout 31 and the fourth cutout 32. This avoids the main gate obstructing the third cutout 31 and the fourth cutout 32.
[0235] In the description of this specification, the use of terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., refers to specific features, structures, materials, or characteristics described in connection with the embodiments or examples, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0236] Furthermore, the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A back-contact solar cell, characterized in that, include: A silicon substrate having opposing front and back sides; and A plurality of first doped layers and a plurality of second doped layers are stacked on the back side, the plurality of first doped layers and the plurality of second doped layers are alternately arranged along a first direction and all extend along a second direction, the second direction intersecting the first direction; The first doped layer has a first side and a second side opposite to each other in the first direction. At least one first doped layer has a first cutout and a second cutout formed thereon. The first cutout and the second cutout are spaced apart along the first direction. The first cutout is located on the side where the first side is located and penetrates the first side. The second cutout is located on the side where the second side is located and penetrates the second side. The silicon substrate is exposed from the first cutout and the second cutout.
2. The back-contact solar cell according to claim 1, characterized in that, The area exposed on the back from the first and second cutouts is a velvety surface; and / or The area on the back side covered by the first doped layer is the polished area.
3. The back-contact solar cell according to claim 1, characterized in that, The length of the first hollowed-out groove in the second direction is 50μm-500μm; and / or The length of the second hollow groove in the second direction is 50μm-500μm.
4. The back-contact solar cell according to claim 1, characterized in that, The number of the first hollow slot and the number of the second hollow slot are both multiple, the multiple first hollow slots are arranged at intervals along the second direction, and the multiple second hollow slots are also arranged at intervals along the second direction; Wherein, in the first doped layer, the spacing between two adjacent first hollow slots in the second direction is 50μm-1000μm; and / or In the first doped layer, the spacing between two adjacent second hollow slots in the second direction is 50μm-1000μm.
5. The back-contact solar cell according to claim 1, characterized in that, The ratio between the sum of the lengths of the first hollow groove and the second hollow groove in the first direction and the length of the first doped layer in the first direction is 50%-95%.
6. The back-contact solar cell according to claim 1, characterized in that, The first and second hollowed-out grooves have the same shape and size and are aligned in the first direction.
7. The back-contact solar cell according to claim 6, characterized in that, The first and second hollowed-out grooves are symmetrically arranged about the center line of the first doped layer.
8. The back-contact solar cell according to claim 6, characterized in that, The portion of the first doped layer located between the first and second hollowed-out grooves has a length of 5 μm-100 μm in the first direction.
9. The back-contact solar cell according to claim 1, characterized in that, The first hollowed-out groove and the second hollowed-out groove partially overlap in the first direction; or the first hollowed-out groove and the second hollowed-out groove do not overlap in the first direction.
10. The back-contact solar cell according to claim 1, characterized in that, The back-contact solar cell also includes: At least a back passivation layer is stacked over the first doped layer and the second doped layer; A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer. The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.
11. The back-contact solar cell according to claim 10, characterized in that, The first grid line electrode is located between the first hollowed-out groove and the second hollowed-out groove.
12. The back-contact solar cell according to claim 11, characterized in that, The first and second hollowed-out grooves have the same shape and size and are aligned in the first direction; The first doped layer includes a first main body segment located on both sides of the first cutout and the second cutout in the second direction, and a first connecting segment located between the first cutout and the second cutout in the first direction, wherein the first connecting segment connects two adjacent first main body segments; The first grid line electrode is disposed on the first main body segment and the first connecting segment and does not obstruct the first hollow slot and the second hollow slot.
13. The back-contact solar cell according to claim 1, characterized in that, All of the first doped layers are provided with a plurality of first hollow grooves and a plurality of second hollow grooves. All of the first hollow grooves on the back contact solar cell are arranged in a rectangular array, and all of the second hollow grooves on the back contact solar cell are also arranged in a rectangular array.
14. The back-contact solar cell according to claim 1, characterized in that, The second doped layer has opposing third and fourth sides in the first direction, and at least one second doped layer has a third and a fourth cutout groove formed thereon. The third cutout groove is located on the side where the third side is located and extends through the third side, and the fourth cutout groove is located on the side where the fourth side is located and extends through the fourth side. The silicon substrate is exposed from the third and fourth cutout grooves.
15. The back-contact solar cell according to claim 14, characterized in that, The area exposed on the back side from the third and fourth cutouts is a velvety surface area; and / or The area on the back side covered by the second doped layer is the polished area.
16. The back-contact solar cell according to claim 14, characterized in that, The length of the third hollowed-out groove in the second direction is 50μm-500μm; and / or The length of the fourth hollowed-out groove in the second direction is 50μm-500μm.
17. The back-contact solar cell according to claim 14, characterized in that, The number of the third hollow slot and the fourth hollow slot are both multiple, and the multiple third hollow slots are arranged at intervals along the second direction, and the multiple fourth hollow slots are also arranged at intervals along the second direction; In the second doped layer, the spacing between two adjacent third hollow slots in the second direction is 50 μm-1000 μm; and / or In the second doped layer, the spacing between two adjacent fourth hollowed-out grooves in the second direction is 50μm-1000μm.
18. The back-contact solar cell according to claim 14, characterized in that, The ratio between the sum of the lengths of the third hollow groove and the fourth hollow groove in the first direction and the length of the second doped layer in the first direction is 50%-95%.
19. The back-contact solar cell according to claim 14, characterized in that, The third and fourth hollowed-out grooves have the same shape and size and are aligned in the first direction.
20. The back-contact solar cell according to claim 19, characterized in that, The third and fourth hollowed-out grooves are symmetrically arranged about the center line of the second doped layer.
21. The back-contact solar cell according to claim 19, characterized in that, The portion of the first doped layer located between the third and fourth hollow slots has a length of 5 μm-100 μm in the first direction.
22. The back-contact solar cell according to claim 14, characterized in that, The third and fourth hollowed-out grooves partially overlap in the first direction; or the third and fourth hollowed-out grooves do not overlap in the first direction.
23. The back-contact solar cell according to claim 14, characterized in that, The back-contact solar cell also includes: At least a back passivation layer is stacked over the first doped layer and the second doped layer; A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer. The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.
24. The back-contact solar cell according to claim 23, characterized in that, The second grid line electrode is located between the third and fourth hollow slots.
25. The back-contact solar cell according to claim 24, characterized in that, The third and fourth hollow slots have the same shape and size and are aligned in the first direction; The second doped layer includes a second main body segment located on both sides of the third and fourth cutouts in the second direction, and a second connecting segment located between the third and fourth cutouts in the first direction, wherein the second connecting segment connects two adjacent second main body segments; The second grid line electrode is disposed on the second main body segment and the second connecting segment and does not obstruct the third and fourth hollow slots.
26. The back-contact solar cell according to claim 14, characterized in that, All of the first doped layers are provided with a plurality of the third hollow grooves and a plurality of the fourth hollow grooves. All of the third hollow grooves on the back contact solar cell are arranged in a rectangular array, and all of the fourth hollow grooves on the back contact solar cell are also arranged in a rectangular array.
27. The back-contact solar cell according to claim 14, characterized in that, The first, second, third, and fourth hollow slots are all identical in shape and aligned in the first direction; or The first and second hollow slots are aligned in the first direction, and the third and fourth hollow slots are aligned in the first direction, while the third and second hollow slots are staggered in the first direction.
28. The back-contact solar cell according to claim 14, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; Wherein, the lengths of the first and second hollow slots in the second direction are less than the lengths of the third and fourth hollow slots in the second direction; and / or The spacing between two adjacent first hollow slots and the spacing between two adjacent second hollow slots in the first doped layer are both smaller than the spacing between two adjacent third hollow slots and the spacing between two adjacent fourth hollow slots in the second doped layer; and / or The lengths of the first and second hollowed-out grooves in the first direction are less than the lengths of the third and fourth hollowed-out grooves in the first direction.
29. The back-contact solar cell according to claim 14, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; In the adjacent first doped layer and second doped layer, the distribution density of the first and second cutouts on the first doped layer in the second direction is greater than the distribution density of the third and fourth cutouts on the second doped layer in the second direction.
30. The back-contact solar cell according to claim 23, characterized in that, The back side of the silicon substrate has a plurality of first serial connection areas and a plurality of second serial connection areas. The plurality of first serial connection areas and the plurality of second serial connection areas are alternately arranged along the second direction and all extend along the first direction. The first serial connection areas are used to provide a first conductive connector electrically connected to the first gate electrode and insulated from the second gate electrode. The second serial connection areas are used to provide a second conductive connector electrically connected to the second gate electrode and insulated from the first gate electrode. The number of first serial connection areas is less than the number of third cutouts and the number of fourth cutouts, and the number of second serial connection areas is less than the number of first cutouts and the number of second cutouts.
31. The back-contact solar cell according to claim 30, characterized in that, The first serial connection area and the second serial connection area do not have the first hollow groove, the second hollow groove, the third hollow groove and the fourth hollow groove.
32. The back-contact solar cell according to claim 30, characterized in that, The first and second hollow slots have the same size in the second direction and are aligned in the first direction. The third and fourth hollow slots have the same size in the second direction and are aligned in the first direction. The third and second hollow slots are staggered in the first direction. The first serial connection area corresponds to one of the third and fourth hollow slots, and the second serial connection area corresponds to one of the first and second hollow slots.
33. The back-contact solar cell according to claim 32, characterized in that, The length of the third hollowed-out groove corresponding to the first serial connection area in the second direction is greater than the length of the other third hollowed-out grooves in the second direction; The length of the first hollowed-out groove corresponding to the second serial connection area in the second direction is greater than the length of the other first hollowed-out grooves in the second direction.
34. The back-contact solar cell according to claim 32, characterized in that, In a single first hollow slot, the area covered by the second conductive connector accounts for less than 10% of the total area; and / or, in a single third hollow slot, the area covered by the first conductive connector accounts for less than 10% of the total area.
35. The back-contact solar cell according to claim 23, characterized in that, In the thickness direction of the back contact solar cell, a first wire is correspondingly disposed on the first grid line electrode, and the first wire is welded to the first grid line electrode; a second wire is correspondingly disposed on the second grid line electrode, and the second wire is welded to the second grid line electrode. Specifically, in the thickness direction of the back contact solar cell, the first wire and the first hollow groove do not overlap; and / or the second wire and the second hollow groove do not overlap.
36. A battery assembly, characterized in that, Includes the back-contact solar cell as described in any one of claims 1-35.
37. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 36.