Stacked battery and photovoltaic module

Abstract

The utility model discloses laminated battery and photovoltaic module. Laminated battery includes bottom battery, top battery and connecting layer, and connecting layer is located between bottom battery and top battery, bottom battery includes: crystalline silicon substrate, first tunneling oxide layer is located between crystalline silicon substrate and top battery, first doped polysilicon layer is located between first tunneling oxide layer and top battery, positive film is located between first doped polysilicon layer and top battery, and positive film includes positive silicon nitride layer, and positive silicon nitride layer includes at least two laminatedly arranged silicon nitride sub -film layers, the refractive index of any two adjacent silicon nitride sub -film layers is different, and positive film has a plurality of openings, a plurality of openings are arranged along the first direction, and connecting layer fills a plurality of openings and contacts with first doped polysilicon layer. Therefore, positive film can improve the passivation performance of bottom battery, improve the light absorption capacity of bottom battery, thereby being favorable to improving the performance of laminated battery.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically to tandem solar cells and photovoltaic modules. Background Technology

[0002] For decades, crystalline silicon (c-Si) solar cells have maintained a dominant position in the photovoltaic market due to their superior efficiency, abundant material supply, and long-term reliability. The photoelectric conversion efficiency (PCE) of crystalline silicon solar cells has exceeded 27%. To further enhance the efficiency of solar cells, integrating wide-bandgap metal halide perovskites in a tandem configuration on top of monocrystalline silicon solar cells to maximize light absorption has become a highly effective strategy. However, further improvements in the performance of crystalline silicon cells are primarily influenced by their non-radiative recombination properties. Therefore, the passivation performance and light absorption capacity of the crystalline silicon bottom cell are crucial for improving the performance of perovskite / crystalline silicon tandem cells.

[0003] For two-terminal perovskite / crystalline silicon tandem solar cells, the bottom cell is typically a Topcon (Tunnel Oxide Passivated Contact) cell or a heterojunction (SHJ) cell. For Topcon bottom cells, to allow carrier transport between the bottom and top cells, the connecting layer is directly disposed on the doped polycrystalline silicon layer on the front side of the Topcon bottom cell. Compared to a normal Topcon cell, the passivation effect and light absorption capacity of the Topcon bottom cell in a tandem solar cell are poorer.

[0004] Therefore, current tandem solar cells and photovoltaic modules still need improvement. Utility Model Content

[0005] This invention aims to at least alleviate or solve at least one of the aforementioned problems to some extent.

[0006] In one aspect, this utility model proposes a stacked solar cell. In some embodiments of this utility model, the stacked solar cell includes a bottom cell, a top cell, and a connecting layer, with the connecting layer located between the bottom cell and the top cell. The bottom cell includes: a crystalline silicon substrate; a first tunneling oxide layer located between the crystalline silicon substrate and the top cell; a first doped polycrystalline silicon layer located between the first tunneling oxide layer and the top cell; and a positive film located between the first doped polycrystalline silicon layer and the top cell. The positive film includes a front-side silicon nitride layer, which comprises at least two stacked silicon nitride sub-films. Any two adjacent silicon nitride sub-films have different refractive indices. The positive film has multiple openings arranged along a first direction. The connecting layer fills the multiple openings and contacts the first doped polycrystalline silicon layer. Therefore, the positive film can improve the passivation performance of the bottom cell and enhance its light absorption capacity, thereby improving the performance of the stacked solar cell.

[0007] In some embodiments of this invention, along the first direction, the length of each opening is 'a', the spacing between two adjacent openings is 'b', and the stacked battery satisfies at least one of the following conditions: a / b is 0.3-1; b is 0.9μm-2μm. This facilitates carrier transport between the top and bottom cells, thereby further improving the performance of the stacked battery.

[0008] In some embodiments of this invention, the front-side silicon nitride layer includes a first silicon nitride sub-film layer and a second silicon nitride sub-film layer. The second silicon nitride sub-film layer is located on the surface of the first silicon nitride sub-film layer away from the crystalline silicon substrate. The first silicon nitride sub-film layer has a thickness of 40nm-60nm and a refractive index of 2.2-2.4. The second silicon nitride sub-film layer has a thickness of 30nm-80nm and a refractive index of 1.9-2.0. This is beneficial for further improving the passivation performance and light absorption capability of the bottom solar cell.

[0009] In some embodiments of this invention, the thickness of the front silicon nitride layer is 90nm-120nm.

[0010] In some embodiments of this utility model, the connecting layer includes at least one of a transparent conductive oxide layer and a doped polycrystalline silicon layer.

[0011] In some embodiments of this invention, the positive film further includes a front alumina layer, which is located between the first doped polycrystalline silicon layer and the front silicon nitride layer; optionally, the thickness of the front alumina layer is 4nm-7nm. This is beneficial for further improving the passivation effect of the bottom cell.

[0012] In some embodiments of this utility model, the bottom cell further includes: a second tunneling oxide layer located on the side of the crystalline silicon substrate away from the top cell; and a second doped polycrystalline silicon layer located on the side of the second tunneling oxide layer away from the top cell, wherein the doping type of the second doped polycrystalline silicon layer is opposite to that of the first doped polycrystalline silicon layer.

[0013] In some embodiments of this invention, the top cell includes a hole transport layer, a perovskite light-absorbing layer, and an electron transport layer. The perovskite light-absorbing layer is located between the hole transport layer and the electron transport layer. The stacked cell satisfies one of the following conditions: the first doped polysilicon layer is an N-type doped polysilicon layer, the second doped polysilicon layer is a P-type doped polysilicon layer, and the hole transport layer is located between the perovskite light-absorbing layer and the bottom cell; or the first doped polysilicon layer is a P-type doped polysilicon layer, the second doped polysilicon layer is an N-type doped polysilicon layer, and the electron transport layer is located between the perovskite light-absorbing layer and the bottom cell.

[0014] In another aspect, this utility model provides a photovoltaic module. In some embodiments of this utility model, the photovoltaic module includes the aforementioned tandem solar cell. Therefore, this photovoltaic module possesses all the features and advantages of the aforementioned tandem solar cell, which will not be repeated here. Attached Figure Description

[0015] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0016] Figure 1 A schematic diagram of a stacked battery according to an embodiment of the present invention is shown;

[0017] Figure 2 A schematic diagram of the structure of a stacked battery according to another embodiment of the present invention is shown;

[0018] Figure 3 The diagram shows a laser-aperture area and a non-laser-aperture area in one embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures:

[0020] 1: Bottom cell; 2: Connecting layer; 3: Top cell; 10: Crystalline silicon substrate; 20: First tunneling oxide layer; 30: First doped polycrystalline silicon layer; 40: Front film; 41: Front silicon nitride layer; 41': First silicon nitride sub-film layer; 42”: Second silicon nitride sub-film layer; 42: Front alumina layer; 50: Second tunneling oxide layer; 60: Second doped polycrystalline silicon layer; 70: Back film; 90: First electrode; 4: Laser-aperture area; 5: Non-laser-aperture area. Detailed Implementation

[0021] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0022] In one aspect, this utility model provides a stacked battery. In some embodiments of this utility model, reference is made to... Figure 1 and Figure 2 The stacked battery includes a bottom battery 1, a top battery 3 and a connecting layer 2, with the connecting layer 2 located between the bottom battery 1 and the top battery 3.

[0023] In some embodiments, reference Figure 1 and Figure 2 The bottom cell 1 includes a crystalline silicon substrate 10, a first tunneling oxide layer 20, a first doped polycrystalline silicon layer 30, and a positive film 40. The first tunneling oxide layer 20 is located between the crystalline silicon substrate 10 and the top cell 3; the first doped polycrystalline silicon layer 30 is located between the first tunneling oxide layer 20 and the top cell 3; the positive film 40 is located between the first doped polycrystalline silicon layer 30 and the top cell 3, and the positive film 40 includes a front-side silicon nitride layer 41. The front-side silicon nitride layer 41 includes at least two stacked silicon nitride sub-films, and any two adjacent silicon nitride sub-films have different refractive indices. The positive film 40 has multiple openings, and these openings are along a first direction (e.g., ...). Figure 1 and Figure 2 Arranged in the X direction as shown, the connecting layer 2 fills multiple openings and contacts the first doped polycrystalline silicon layer 30. Thus, by setting a positive film on the front side of the silicon substrate, the passivation effect of the front side of the bottom cell can be improved. Furthermore, the positive film can play an anti-reflection role, enhancing the light absorption capacity of the bottom cell, thereby improving the overall performance of the tandem cell.

[0024] In some embodiments of this utility model, the crystalline silicon substrate 10 can be a monocrystalline silicon substrate.

[0025] In some embodiments of this invention, the crystalline silicon substrate 10 can be an N-type substrate.

[0026] In some specific embodiments, the crystalline silicon substrate 10 can be an N-type single-crystal silicon substrate, and the thickness of the crystalline silicon substrate 10 can be 130-150 micrometers.

[0027] In some embodiments of this invention, the connecting layer 2 may include at least one of a transparent conductive oxide (TCO) layer, a doped polysilicon layer, etc., without limitation by this invention. Specifically, the TCO layer may be indium tin oxide (ITO, In₂O₃:Sn), aluminum-doped zinc oxide (AZO, ZnO:Al), fluorine-doped tin oxide (FTO, SnO₂:F), antimony-doped tin oxide (ATO, SnO₂:Sb), indium-doped zinc oxide (IZO, ZnO:In), etc. The doped polysilicon layer may be P-type doped polysilicon (e.g., boron-doped polysilicon) or N-type doped polysilicon (e.g., phosphorus-doped polysilicon). It is understood that the doped polysilicon layer serving as the connecting layer has the opposite polarity to the first doped polysilicon layer 30. For example, if the first doped polysilicon layer 30 is P-type, then the doped polysilicon layer of the connecting layer is N-type, and vice versa. The aforementioned film layer exhibits good electrical conductivity, which is beneficial for improving the carrier transport and collection capabilities of the tandem solar cell. In some specific embodiments, the connecting layer 2 can be an ITO layer or an FTO layer.

[0028] In some embodiments of the present invention, the first tunneling oxide layer 20 may include a silicon oxide layer.

[0029] In some embodiments of this utility model, the thickness of the first tunneling oxide layer 20 can be 1.5nm-2.3nm. For example, the thickness of the first tunneling oxide layer 20 can be 1.5nm, 1.7nm, 1.9nm, 2nm, 2.1nm, 2.3nm, etc. Therefore, the first tunneling oxide layer can play a better tunneling and passivation role, which is beneficial to further improve the performance of the stacked battery.

[0030] In some embodiments, the first tunneling oxide layer 20 may be a silicon oxide layer with a thickness of 1.5 nm to 2.3 nm.

[0031] In some embodiments, the thickness of the first tunneling oxide layer 20 can be 1.5 nm to 1.9 nm. In other embodiments, the thickness of the first tunneling oxide layer 20 can be 1.9 nm to 2.3 nm.

[0032] In some embodiments of this invention, the first doped polysilicon layer 30 can be an N-type doped polysilicon layer, and the doping element can include phosphorus, with a doping concentration of 2 × 10⁻⁶. 20 cm -3 -8×10 20 cm -3In some embodiments, the thickness of the first doped polysilicon layer 30 can be 30 nm to 150 nm.

[0033] In some other embodiments of this invention, the first doped polysilicon layer 30 can be a P-type doped polysilicon layer, and the doping element can include boron, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 -8×10 19 cm -3 In some embodiments of this invention, the thickness of the first doped polycrystalline silicon layer 30 can be 230nm-360nm.

[0034] In some embodiments of this utility model, reference is made to Figure 1 and Figure 2 The positive film 40 may include a front silicon nitride layer 41, and the front silicon nitride layer may include two or more silicon nitride sub-films.

[0035] In some specific embodiments of this utility model, reference is made to Figure 1 and Figure 2 The front silicon nitride layer 41 may include a first silicon nitride sub-film layer 41' and a second silicon nitride sub-film layer 41', the second silicon nitride sub-film layer 41' being located on the surface of the first silicon nitride sub-film layer 41' away from the crystalline silicon substrate 10.

[0036] In some embodiments, the thickness of the first silicon nitride sub-film layer 41' can be 40nm-60nm, and the refractive index of the first silicon nitride sub-film layer 41' can be 2.2-2.4. For example, the thickness of the first silicon nitride sub-film layer 41' can be 40nm, 45nm, 50nm, 55nm, 60nm, etc., and the refractive index can be 2.2, 2.25, 2.3, 2.35, 2.4, etc.; the thickness of the second silicon nitride sub-film layer 41" is 30nm-80nm, and the refractive index of the second silicon nitride sub-film layer 41" is 1.9-2.0. For example, the thickness of the second silicon nitride sub-film layer 41" can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, etc., and the refractive index of the second silicon nitride sub-film layer 41" can be 1.9, 1.93, 1.95, 1.98, 2.0, etc. The first silicon nitride sub-film layer can enhance passivation performance and reduce interface state density; the second silicon nitride sub-film layer can optimize antireflection performance and improve light-harvesting capability.

[0037] In some embodiments, the thickness of the front silicon nitride layer 41 can be 90nm-120nm, for example, the thickness of the front silicon nitride layer 41 can be 90nm, 95nm, 100nm, 105nm, 120nm, etc. The front silicon nitride layer of the above thickness can improve passivation and light absorption capabilities, thereby helping to improve the overall performance of the tandem solar cell.

[0038] In some embodiments of this utility model, reference is made to Figure 1 The positive film may consist solely of the front silicon nitride layer 41, which is composed of multiple silicon nitride sub-films. In some specific embodiments, the front silicon nitride layer 41 may include two (e.g., Figure 1 and Figure 2 (as shown), 3, 4, 5 or 6 silicon nitride sub-films.

[0039] In other embodiments of this utility model, reference is made to Figure 2 In addition to the front silicon nitride layer 41, the front film 40 may also include a front aluminum oxide layer 42, which is located between the first doped polycrystalline silicon layer 30 and the front silicon nitride layer 41. The front aluminum oxide layer can play a certain passivation role, and setting the front aluminum oxide layer is beneficial to further improve the passivation effect of the tandem solar cell.

[0040] In some embodiments of this invention, the thickness of the front alumina layer 42 can be 4nm-7nm. An alumina layer of this thickness can at least partially improve the passivation effect of the bottom cell, thereby contributing to further improvements in the overall performance of the stacked battery.

[0041] refer to Figure 1 and Figure 2 Along the first direction (e.g.) Figure 1 and Figure 2 In the X direction (as shown), the length of each opening is a, and the distance between two adjacent openings is b.

[0042] In some embodiments of this utility model, reference is made to Figure 1 and Figure 2 The ratio a / b can be between 0.3 and 1, for example, a / b can be 0.3, 0.4, 0.5, 0.7, 0.9, 1, etc. Therefore, the connecting layer can form a good contact with the first doped polycrystalline silicon layer, thus giving the tandem solar cell good carrier collection capability.

[0043] In some embodiments of this utility model, reference is made to Figure 1 and Figure 2 The spacing b between two adjacent openings can be 0.9 μm to 2 μm. For example, the spacing b between two adjacent openings can be 0.9 μm, 1 μm, 1.3 μm, 1.5 μm, 1.8 μm, 2 μm, etc. This allows for the improvement of both the passivation capability and the carrier collection capability of the battery.

[0044] In some embodiments of this utility model, reference is made to Figure 1 and Figure 2The bottom cell 1 also includes a second tunneling oxide layer 50 and a second doped polysilicon layer 60. The second tunneling oxide layer 50 is located on the side of the crystalline silicon substrate 10 away from the top cell 3; the second doped polysilicon layer 60 is located on the side of the second tunneling oxide layer 50 away from the top cell 3, and the doping type of the second doped polysilicon layer 60 is opposite to that of the first doped polysilicon layer 30. Thus, the second tunneling oxide layer can perform tunneling and passivation functions, and the second doped polysilicon layer can improve the contact performance of the bottom cell.

[0045] It should be noted that the doping types of the second doped polysilicon layer 60 and the first doped polysilicon layer 30 are opposite. That is, when the first doped polysilicon layer 30 is an N-type doped layer (the doping element can be phosphorus), the second doped polysilicon layer 60 is a P-type doped layer (the doping element can be boron); when the first doped polysilicon layer 30 is a P-type doped layer, the second doped polysilicon layer 60 is an N-type doped layer.

[0046] In some embodiments of this utility model, reference is made to Figure 1 and Figure 2 The bottom cell 1 may also include a back film 70 and a first electrode 90. The back film 70 is located on the side of the second doped polysilicon layer 60 away from the crystalline silicon substrate 10, and the first electrode 90 penetrates the back film 70 and contacts the second doped polysilicon layer 60.

[0047] In some embodiments, the first electrode 90 may be a silver electrode. In some specific embodiments, the first electrode 90 may include a main gate and fine gate lines.

[0048] In some embodiments of this invention, the back film 70 may include a back aluminum oxide layer and a back silicon nitride layer, with the back aluminum oxide layer located between the second doped polycrystalline silicon layer 60 and the back silicon nitride layer. This is beneficial for further improving the passivation performance and anti-reflection capability of the bottom cell, thereby further enhancing the overall performance of the tandem cell.

[0049] In some embodiments, the thickness of the back alumina layer can be 4nm-7nm.

[0050] In some embodiments, the thickness of the back silicon nitride layer can be 80nm-100nm. In some specific embodiments, the back silicon nitride layer may include multiple silicon nitride sub-films.

[0051] In some embodiments of this invention, the thickness of the connecting layer 2 can be 100nm-200nm. A thickness within this range is beneficial for improving the light absorption capacity of the bottom cell and the carrier collection capacity of the stacked cell.

[0052] In some embodiments of this invention, the top battery 3 may include a hole transport layer, a perovskite light-absorbing layer, and an electron transport layer, with the perovskite light-absorbing layer located between the hole transport layer and the electron transport layer.

[0053] In some embodiments of this invention, the first doped polysilicon layer 30 is an N-type doped polysilicon layer, the second doped polysilicon layer 60 is a P-type doped polysilicon layer, and the hole transport layer is located between the perovskite light-absorbing layer and the bottom cell 1. In some specific embodiments, the first doped polysilicon layer 30 is an N-type doped polysilicon layer with a thickness of 30nm-150nm, and the second doped polysilicon layer 60 is a P-type doped polysilicon layer with a thickness of 230nm-360nm.

[0054] In some embodiments of this invention, the first doped polysilicon layer 30 is a P-type doped polysilicon layer, the second doped polysilicon layer 30 is an N-type doped polysilicon layer, and the electron transport layer is located between the perovskite light-absorbing layer and the bottom cell 1. In some embodiments, the first doped polysilicon layer 30 is a P-type doped polysilicon layer with a thickness of 230 nm-360 nm, and the second doped polysilicon layer 30 is an N-type doped polysilicon layer with a thickness of 30 nm-150 nm.

[0055] In some embodiments, the top cell 3 may further include a second electrode located on the side of the perovskite light-absorbing layer away from the bottom cell.

[0056] The present invention does not impose specific limitations on the material, thickness, and other characteristics of the hole transport layer, perovskite light-absorbing layer, electron transport layer, and second electrode; those skilled in the art can select and set them as needed.

[0057] This invention provides a method for preparing the aforementioned stacked battery. In some embodiments of this invention, the method for preparing the aforementioned stacked battery may include the following steps:

[0058] S10: Forms the bottom cell.

[0059] In some embodiments, forming the bottom cell includes:

[0060] S11: A first tunneling oxide layer is formed on one side of a crystalline silicon substrate.

[0061] In some embodiments, the crystalline silicon substrate can be an N-type single-crystal silicon layer with a thickness of 130-150 micrometers.

[0062] In some embodiments, the silicon substrate may be polished before forming the tunneling oxide layer to remove the mechanical damage layer on the silicon wafer surface.

[0063] In some embodiments, the front side of the crystalline silicon substrate (the surface of the crystalline silicon substrate near the top cell) can be textured, and the first tunneling oxide layer, the first doped polycrystalline silicon layer, and the positive film formed thereafter can all have textured structures.

[0064] In some embodiments, a silicon oxide layer can be deposited on the surface of a crystalline silicon substrate. In some specific embodiments, a silicon oxide layer can be deposited on the front side of the crystalline silicon substrate using an LPCVD (low-pressure chemical vapor deposition) method.

[0065] In some embodiments, the thickness of the first tunneling oxide layer can be 1.5 nm to 1.9 nm.

[0066] S12: A first doped polycrystalline silicon layer is formed on the side of the first tunneling oxide layer away from the crystalline silicon substrate.

[0067] In some embodiments, a polycrystalline silicon layer can be deposited on the side of the first tunneling oxide layer away from the crystalline silicon substrate using the LPCVD method, and then the polycrystalline silicon layer can be doped to form a first doped polycrystalline silicon layer.

[0068] In some embodiments, after depositing a polycrystalline silicon layer, phosphorus diffusion can be performed to form an N-type doped polycrystalline silicon layer. In other embodiments, after depositing a polycrystalline silicon layer, boron diffusion can be performed to form a P-type doped polycrystalline silicon layer.

[0069] S13: Form the original positive film on the side of the first doped polycrystalline silicon layer away from the crystalline silicon substrate.

[0070] In some embodiments of this invention, a full-layer front alumina layer can be formed on the side of the first doped polycrystalline silicon layer away from the crystalline silicon substrate, and then a full-layer front silicon nitride layer can be formed on the side of the front alumina layer away from the crystalline silicon substrate. The front silicon nitride layer includes at least two stacked silicon nitride sub-films.

[0071] In some embodiments of this invention, the total thickness of the front silicon nitride layer is 90nm-120nm, which is thicker than the silicon nitride layer of a normal Topcon battery, and can serve as a protective film during subsequent wet processing.

[0072] In some embodiments of this invention, the front-side alumina layer can be prepared using the ALD (Atomic Layer Deposition) method: An aluminum source, TMA (trimethylaluminum), is introduced into the reaction chamber, where aluminum source molecules are adsorbed onto the surface of the first doped polycrystalline silicon layer. Purging: Nitrogen gas is used to remove unreacted aluminum source and byproducts. Oxygen source pulse: H2O is introduced to react with the aluminum source adsorbed on the surface of the first doped polycrystalline silicon layer to generate alumina. Purging: Nitrogen gas is used again to remove unreacted oxygen source and byproducts. The temperature for each step is 150℃-400℃, the time is 5s-20s, and the cycle is 10-50 times, depositing a 4nm-7nm thick Al2O3 layer on the front side of the silicon wafer.

[0073] S14: Laser drilling is performed on the original positive membrane to obtain a positive membrane with multiple openings.

[0074] In some embodiments of this invention, a picosecond laser with a wavelength of 355 nm can be used to laser-drill holes in the original positive film, exposing the first doped polysilicon layer. Using a laser of the aforementioned wavelength to drill holes in the original positive film can completely remove the required portion of the positive film, and minimizes the damage to the underlying first doped polysilicon layer caused by the laser drilling.

[0075] In some embodiments of this invention, the laser spot size is 100μm-180μm, for example, the spot size can be 100μm, 120μm, 150μm, 160μm, 180μm, etc.

[0076] In some embodiments of this invention, the single pulse energy is 55μJ-100μJ. For example, the single pulse energy can be 55μJ, 60μJ, 70μJ, 80μJ, 90μJ, 100μJ, etc., thereby reducing the damage to the first doped polysilicon layer while removing the positive film.

[0077] In some embodiments of this invention, the laser frequency can be 400kHz-800kHz, for example, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, etc. This facilitates the removal of the positive film, thereby exposing the first doped polycrystalline silicon layer.

[0078] In some embodiments of this invention, the laser power can be 22W-80W, for example, 22W, 35W, 50W, 70W, or 80W. This allows for the thorough removal of the positive film while minimizing damage to the underlying film.

[0079] In some embodiments of this invention, the pulse width of the laser is 10ps-20ps, for example, the pulse width can be 10ps, 12ps, 15ps, 17ps, 20ps, etc.

[0080] In some embodiments of this utility model, the laser scanning speed is 40m / s-65m / s. For example, the scanning speed can be 40m / s, 45m / s, 50m / s, 55m / s, 60m / s, 65m / s, etc., which is beneficial for quickly and thoroughly removing the positive film that needs to be removed.

[0081] In some embodiments of this utility model, reference is made to Figure 3 Laser-drilled area 4 along the first direction (e.g.) Figure 3 Arranged in the X direction as shown, along the second direction (such as... Figure 3 The second direction extends from the Y direction shown, and intersects the first direction. In some embodiments, the second direction is perpendicular or substantially perpendicular to the first direction; for example, the acute angle between the second direction and the first direction can be ≥85 degrees and <90 degrees.

[0082] In some embodiments, reference Figure 3 The ratio of the length 'a' of each laser-aperture region 4 along the first direction (X direction) to the distance 'b' between two adjacent laser-aperture regions 4 is 0.3-1. The area between two adjacent laser-aperture regions 4 is a non-laser-aperture region 5, and the distance 'b' between two adjacent laser-aperture regions 4 refers to the length 'b' of the non-laser-aperture region 5 along the first direction (X direction). Therefore, while ensuring the passivation effect of the positive film, the tandem solar cell also possesses good lateral transport and collection capabilities, guaranteeing the transport of charge carriers from the bottom cell to the top cell.

[0083] In some embodiments, reference Figure 3 The spacing b between two adjacent laser-aperture regions 4 is 0.9μm-2μm, meaning the length of the non-laser-aperture region 5 along the first direction (X direction) is 0.9μm-2μm. This is beneficial for improving the passivation effect of the positive film and the carrier transport performance from the bottom cell to the top cell.

[0084] For the back side of the crystalline silicon substrate (the surface of the crystalline silicon substrate away from the top cell), a second tunneling oxide layer can be formed first, and then a second doped polycrystalline silicon layer can be formed on the side of the second tunneling oxide layer away from the crystalline silicon substrate; then, a back film can be formed on the side of the second doped polycrystalline silicon layer away from the crystalline silicon substrate, and then a first electrode can be formed, with the first electrode in contact with the second doped polycrystalline silicon layer.

[0085] In some embodiments of this invention, a back aluminum oxide layer can be formed first on the side of the second doped polycrystalline silicon layer away from the crystalline silicon substrate, and then a back silicon nitride layer can be formed on the side of the back aluminum oxide layer away from the crystalline silicon substrate to obtain a back film. In some embodiments, the back silicon nitride layer may include multiple stacked silicon nitride sub-films. The back aluminum oxide layer can be prepared using the same steps as the front aluminum oxide layer, which will not be described again here.

[0086] In some embodiments of this invention, the first electrode can be a silver electrode, which can be obtained by printing silver paste and sintering.

[0087] S20: Form a bonding layer, which fills multiple openings and contacts the first doped polysilicon layer.

[0088] In some embodiments of this invention, a PVD (physical vapor deposition) method can be used to deposit a connecting layer with a thickness of 100nm-200nm, so that the connecting layer fills multiple openings and contacts the first doped polysilicon layer.

[0089] In some specific embodiments of this invention, an ITO layer with a thickness of 100nm-200nm can be deposited on the side of the positive film away from the crystalline silicon substrate using magnetron sputtering. The target material contains In₂O₃:SnO₂ at a mass ratio of 90:10, Ar is the sputtering gas, and the pressure inside the deposition chamber is controlled at 1×10⁻⁶. -6 -5×10 -6 For sputtering, the sputtering power is controlled between 50W and 200W.

[0090] S30: A top cell is formed on the side of the connecting layer away from the bottom cell.

[0091] This invention does not impose specific limitations on the materials, thicknesses, and formation methods of each film layer in the top battery. Those skilled in the art can make settings and adjustments according to actual needs.

[0092] The tandem solar cell is fabricated using the above method. A positive film is used to improve the passivation and anti-reflection effects of the bottom cell. Laser-assisted delamination exposes a portion of the surface of the first doped polysilicon layer, allowing the connecting layer to form good contact with the first doped polysilicon layer, thereby improving the overall performance of the tandem solar cell. Furthermore, by designing the laser wavelength and laser energy used for laser delamination, damage to the lower film can be minimized while ensuring thorough removal of the positive film. The area ratio (or length ratio along the first direction) of the laser-apertured area and the retained area (non-laser-apertured area), as well as the spacing between adjacent laser-apertured areas, are designed to retain the passivation effect of the positive film while also providing good lateral carrier transport and collection capabilities, ensuring carrier transport from the bottom cell to the top cell.

[0093] In another aspect, this utility model provides a photovoltaic module. In some embodiments of this utility model, the photovoltaic module includes the aforementioned tandem solar cells. Therefore, the photovoltaic module has good passivation effect and light absorption capacity, which is beneficial to improving the overall performance of the photovoltaic cells.

[0094] In some embodiments of this invention, the photovoltaic module may include multiple stacked cells.

[0095] The present invention will be described below through specific embodiments. Those skilled in the art will understand that the following specific embodiments are merely illustrative and do not limit the scope of the present invention in any way. Furthermore, in the following embodiments, unless otherwise specified, the materials and equipment used are commercially available. If specific processing conditions and methods are not explicitly described in the later embodiments, conditions and methods known in the art can be used for processing.

[0096] Example 1

[0097] 1. First polishing: Remove the mechanical damage layer on the surface of the silicon wafer (crystalline silicon substrate). The silicon wafer used is an N-type monocrystalline silicon wafer with a thickness of 150 micrometers.

[0098] 2. First low-pressure chemical vapor deposition (LP1): A second tunneling oxide layer (silicon oxide layer with a thickness of 2.1 nm) and an intrinsic polycrystalline silicon layer are prepared on the back side of the crystalline silicon substrate. The intrinsic polycrystalline silicon layer is located on the side of the second tunneling oxide layer away from the crystalline silicon substrate.

[0099] 3. Boron diffusion: Boron doping is performed to prepare a P-type doped polysilicon layer and a PN junction; oxidation is then performed to form a BSG layer, which is located on the side of the P-type doped polysilicon layer away from the crystalline silicon substrate. During this step, a P-type doped polysilicon layer and a BSG layer are also formed on the front side of the crystalline silicon substrate.

[0100] 4. Removal of BSG layer using a chain machine: The BSG layer on the front side is removed using an HF solution.

[0101] 5. Texturing: Remove the P-type doped polycrystalline silicon layer on the front side of the crystalline silicon substrate and prepare a textured surface structure on the front side of the crystalline silicon substrate.

[0102] 6. Second low-pressure chemical vapor deposition (LP2): A first tunneling oxide layer (silicon oxide layer with a thickness of 1.7 nm) and an intrinsic polycrystalline silicon layer are prepared on the front side of the crystalline silicon substrate. The intrinsic polycrystalline silicon layer is located on the side of the first tunneling oxide layer away from the crystalline silicon substrate.

[0103] 7. Phosphorus diffusion: Phosphorus doping is performed to convert the intrinsic polycrystalline silicon layer prepared by LP2 into an N-type doped polycrystalline silicon layer; oxidation is then performed to form a PSG layer, which is located on the side of the N-type doped polycrystalline silicon layer away from the crystalline silicon substrate. During this step, an N-type doped polycrystalline silicon layer and a PSG layer are also formed on the back side.

[0104] 8. Chain machine for removing PSG layer: Removes the PSG layer on the back side of the crystalline silicon substrate.

[0105] 9. RCA: Remove the N-type doped polysilicon layer and BSG layer on the back side of the crystalline silicon substrate, and remove the PSG layer on the front side.

[0106] 10. ALD: The aluminum source TMA is introduced into the reaction chamber, where aluminum source molecules adsorb onto the substrate surface. Purging: Nitrogen gas is used to remove unreacted aluminum source and byproducts. Oxygen source pulse: H2O is introduced to react with the adsorbed aluminum source to form alumina. Purging: Nitrogen gas is used again to remove unreacted oxygen source and byproducts. The temperature for each step is 295℃, with an aluminum source pulse of 10s and an oxygen source pulse of 9s, repeated 50 times to deposit a 5nm layer of Al2O3 on both sides of the silicon wafer.

[0107] 11. Front-side silicon nitride layer: A 110nm SiNx antireflective film is deposited using PECVD. The bottom layer has a thickness of 50nm and a refractive index of 2.3; the top layer has a thickness of 60nm and a refractive index of 1.95.

[0108] 12. Laser Aperture: A laser is used to etch the positive SiNx layer and Al2O3 to expose the N-type doped polycrystalline silicon layer. The laser used is a 355nm picosecond laser with a single-pulse energy of 80μJ, a laser power of 48W, a spot size of 150μm, a frequency of 600kHz, a pulse width of 10ps, and a scanning speed of 40m / s. The aperture pattern is shown below. Figure 3 As shown, the ratio of the length a of the laser-aperture region along the X direction to the length b of the non-laser-aperture region along the X direction is 0.6, and the spacing between adjacent laser-aperture regions is 1.5 μm.

[0109] 13. Chain cleaning: Use a mixture of HF and nitric acid to perform chain cleaning on the positive film to remove laser residue.

[0110] 14. Backside silicon nitride layer: SiNx is deposited on the backside using PECVD.

[0111] 15. Printing and sintering: Printing and sintering the back electrode of the bottom cell to form the first electrode.

[0112] 16. PVD: A 150 nm thick ITO layer is deposited on the front side using magnetron sputtering. The target material has an In₂O₃:SnO₂ ratio of 90:10 (mass ratio), and Ar is used as the sputtering gas. The chamber pressure is controlled at 1 × 10⁻⁶. -6 -5×10 -6 The sputtering power is controlled at 100W.

[0113] Example 2

[0114] Unlike Example 1, in Example 2, no aluminum oxide layer was formed on the front side of the crystalline silicon substrate. The remaining parameters and steps were the same as in Example 1.

[0115] Example 3

[0116] Unlike Example 1, in Example 3, the ratio of the length 'a' of the laser-aperture region along the X direction to the length 'b' of the non-laser-aperture region along the X direction is 0.3. The remaining parameters and steps are the same as in Example 1.

[0117] Example 4

[0118] Unlike Example 1, in Example 4, the ratio of the length a of the laser-aperture region along the X direction to the length b of the non-laser-aperture region along the X direction is 1. The remaining parameters and steps are the same as in Example 1.

[0119] Example 5

[0120] Unlike Example 1, in Example 5, the spacing between adjacent laser-aperture regions is 0.9 μm. The remaining parameters and steps are the same as in Example 1.

[0121] Example 6

[0122] Unlike Example 1, in Example 6, the spacing between adjacent laser-aperture regions is 2 μm. The remaining parameters and steps are the same as in Example 1.

[0123] Example 7

[0124] Unlike Example 1, in Example 7, the single pulse energy is 55 μJ, the laser power is 44 W, the spot size is 150 μm, the frequency is 800 kHz, the pulse width is 10 ps, ​​and the scanning speed is 40 m / s. The remaining parameters and steps are the same as in Example 1.

[0125] Example 8

[0126] Unlike Example 1, in Example 8, the single pulse energy is 100 μJ, the laser power is 50 W, the spot size is 150 μm, the frequency is 500 kHz, the pulse width is 10 ps, ​​and the scanning speed is 50 m / s. The remaining parameters and steps are the same as in Example 1.

[0127] Example 9

[0128] Unlike Example 1, in Example 9, the front silicon nitride layer is a 90nm SiNx antireflective film deposited using PECVD. The bottom layer has a thickness of 60nm and a refractive index of 2.2; the top layer has a thickness of 30nm and a refractive index of 1.9. All other parameters and steps are the same as in Example 1.

[0129] Example 10

[0130] Unlike Example 1, in Example 10, the front silicon nitride layer is a 120 nm SiNx antireflective film deposited using PECVD. The bottom layer has a thickness of 40 nm and a refractive index of 2.4; the top layer has a thickness of 80 nm and a refractive index of 2. All other parameters and steps are the same as in Example 1.

[0131] Comparative Example 1

[0132] Unlike Example 1, in Comparative Example 1, no front alumina layer and silicon nitride layer were prepared on the front side of the crystalline silicon substrate; instead, an ITO layer was deposited directly on the N-type doped polycrystalline silicon layer.

[0133] The bottom cells prepared in each embodiment and comparative example were subjected to PL (photoluminescence) testing, open-circuit voltage (iVOC) testing, and fill factor (pFF) testing. The test results are recorded in Table 1. Among them, the PL test was performed using a PL-EL integrated tester, and the average gray value of the bottom cell was recorded; iVoc and pFF were tested using a WCT-120lifetime (minority carrier lifetime tester).

[0134] Table 1. Battery performance test results for each embodiment and comparative example.

[0135] Example 1 23593 741.6 86.81 Example 2 22168 739.8 86.56 Example 3 22872 740.4 86.96 Example 4 24366 743.2 86.88 Example 5 23112 741.2 86.94 Example 6 23862 741.6 86.78 Example 7 23679 741.9 86.85 Example 8 23477 741.6 86.86 Example 9 22541 741.1 86.71 Example 10 24132 742.5 86.92 Comparative Example 1 20012 737.4 86.23

[0136] In Table 1, the PL test data are grayscale values. A higher PL grayscale value indicates a higher relative minority carrier lifetime. The bottom cell in Comparative Example 1 did not have a positive film, while Examples 1-10 all had a positive film. The positive film was patterned using laser perforation, allowing the connecting layer to form good contact with the doped polycrystalline silicon layer on the front side. Compared to Comparative Example 1, the cells in Examples 1-10 have higher minority carrier lifetime, open-circuit voltage, and fill factor. This demonstrates that by setting a positive film, the passivation effect can be effectively improved, enhancing the overall performance of the cell. The positive film in Example 2 consists of multiple silicon nitride sub-film layers, while the positive films in Examples 1 and 3-10 consist of an aluminum oxide layer and multiple silicon nitride sub-film layers. Compared to Example 2, the cells in Examples 1 and 3-10 exhibit superior passivation performance.

[0137] In the description of this utility model, the terms "front", "back", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and do not require that this utility model must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this utility model.

[0138] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," and "other embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the description of this specification, "a plurality of" means two or more, unless otherwise explicitly defined.

[0139] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A stacked battery, characterized in that, It includes a bottom battery, a top battery, and a connecting layer, wherein the connecting layer is located between the bottom battery and the top battery; The bottom battery includes: Crystalline silicon substrate; A first tunneling oxide layer is located between the crystalline silicon substrate and the top cell; A first doped polysilicon layer is located between the first tunneling oxide layer and the top cell; A positive film is located between the first doped polycrystalline silicon layer and the top cell. The positive film includes a front silicon nitride layer, which includes at least two stacked silicon nitride sub-film layers. Any two adjacent silicon nitride sub-film layers have different refractive indices. The positive film has multiple openings, which are arranged along a first direction. The connecting layer fills the multiple openings and contacts the first doped polycrystalline silicon layer.

2. The stacked battery according to claim 1, characterized in that, Along the first direction, the length of each opening is a, the spacing between two adjacent openings is b, and the stacked battery satisfies at least one of the following conditions: a / b is 0.3-1; b is 0.9μm-2μm.

3. The stacked battery according to claim 1, characterized in that, The front silicon nitride layer includes a first silicon nitride sub-film layer and a second silicon nitride sub-film layer. The second silicon nitride sub-film layer is located on the surface of the first silicon nitride sub-film layer away from the crystalline silicon substrate. The thickness of the first silicon nitride sub-film layer is 40nm-60nm, and the refractive index of the first silicon nitride sub-film layer is 2.2-2.

4. The thickness of the second silicon nitride sub-film layer is 30nm-80nm, and the refractive index of the second silicon nitride sub-film layer is 1.9-2.

0.

4. The stacked battery according to claim 1, characterized in that, The thickness of the front silicon nitride layer is 90nm-120nm.

5. The stacked battery according to claim 1, characterized in that, The connecting layer includes at least one of a transparent conductive oxide layer and a doped polycrystalline silicon layer.

6. The stacked battery according to claim 1, characterized in that, The positive film also includes a front alumina layer, which is located between the first doped polysilicon layer and the front silicon nitride layer.

7. The stacked battery according to claim 6, characterized in that, The thickness of the front alumina layer is 4nm-7nm.

8. The stacked battery according to any one of claims 1-7, characterized in that, The bottom battery also includes: A second tunneling oxide layer is located on the side of the crystalline silicon substrate away from the top cell; The second doped polysilicon layer is located on the side of the second tunneling oxide layer away from the top cell, and the doping type of the second doped polysilicon layer is opposite to that of the first doped polysilicon layer.

9. The stacked battery according to claim 8, characterized in that, The top-mounted solar cell includes a hole transport layer, a perovskite light-absorbing layer, and an electron transport layer, wherein the perovskite light-absorbing layer is located between the hole transport layer and the electron transport layer, and the stacked solar cell satisfies one of the following conditions: The first doped polysilicon layer is an N-type doped polysilicon layer, the second doped polysilicon layer is a P-type doped polysilicon layer, and the hole transport layer is located between the perovskite light-absorbing layer and the bottom cell. The first doped polycrystalline silicon layer is a P-type doped polycrystalline silicon layer, the second doped polycrystalline silicon layer is an N-type doped polycrystalline silicon layer, and the electron transport layer is located between the perovskite light-absorbing layer and the bottom cell.

10. A photovoltaic module, characterized in that, The tandem battery includes any one of claims 1-9.

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