Semiconductor die transfer assembly

Abstract

A semiconductor die transfer assembly includes a carrier wafer, a semiconductor die oriented with a proximal surface of the semiconductor die facing the carrier wafer, and a plurality of posts. The posts have distal ends that fill recesses in the proximal surface of the semiconductor die.

Description

Technical Field

[0001] This disclosure relates to a semiconductor die transfer assembly. Background Technology

[0002] The following text is about semiconductor manufacturing technology, semiconductor die transfer technology, and semiconductor die placement technology. Utility Model Content

[0003] One embodiment of this disclosure is a semiconductor die transfer assembly comprising: a carrier wafer; a semiconductor die oriented such that the proximal surface of the semiconductor die faces the carrier wafer; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the semiconductor die.

[0004] One embodiment of this disclosure is a semiconductor die transfer assembly comprising: a carrier wafer; semiconductor dies oriented with the proximal surface of the semiconductor dies facing the carrier wafer, wherein the semiconductor dies are a plurality of light-emitting diode (LED) drivers; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the LED driver.

[0005] One embodiment of this disclosure is a semiconductor die transfer assembly comprising: a carrier wafer; semiconductor dies oriented with the proximal surface of the semiconductor dies facing the carrier wafer, wherein the semiconductor dies are a plurality of light-emitting diode (LED) drivers; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the LED driver. The groove has a plurality of depths between 0.5 micrometers and 6 micrometers. Attached Figure Description

[0006] The various features of this disclosure are best understood by reading in conjunction with the accompanying drawings and the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A A schematic top view of a semiconductor grain transfer structure including semiconductor grains on a bottom holder;

[0008] Figure 1B A schematic side cross-sectional view of the pick-up and placement tool during the process of picking up the target µLED driver from the semiconductor die transfer structure;

[0009] Figure 2A and Figure 2B A semiconductor grain transfer structure is schematically shown, wherein Figure 2A schematically showing along Figure 2B The view AA shown in the figure is a bottom view of the semiconductor grain transfer structure observed in the semiconductor grain transfer structure.

[0010] Figure 2B schematically showing along Figure 2A The cross-sectional view of section BB, as indicated in the figure, shows a portion of the semiconductor grain transfer structure, including representative grains.

[0011] Figure 3A and Figure 3B schematically shown Figure 2A and Figure 2B A view of a representative semiconductor grain in a semiconductor grain transfer structure, wherein... Figure 3A A schematic bottom view of a semiconductor die is shown; and Figure 3B schematically showing along Figure 3A The cross-sectional view of the semiconductor die taken by section CC as indicated in the figure;

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E A side cross-sectional view schematically illustrating the continuous stages of fabrication of a semiconductor grain transfer structure;

[0013] Figure 5A and Figure 5B A schematic view of a representative semiconductor die in a semiconductor die transfer structure according to another embodiment is shown, wherein... Figure 5A A schematic bottom view of a semiconductor die is shown; and Figure 5B schematically showing along Figure 5A The section DD indicated in the figure is a cross-sectional view of the semiconductor die.

[0014] Figure 6A and Figure 6B A schematic view of a representative semiconductor die in a semiconductor die transfer structure according to another embodiment is shown, wherein... Figure 6A A schematic bottom view of a semiconductor die is shown; and Figure 6B schematically showing along Figure 6A The section EE indicated in the figure is a cross-sectional view of the semiconductor die.

[0015] Figure 7A and Figure 7B A schematic view of a representative semiconductor die in a semiconductor die transfer structure according to another embodiment is shown, wherein... Figure 7A A schematic bottom view of a semiconductor die is shown; and Figure 7B schematically showing along Figure 7A The section FF indicated in the figure is a cross-sectional view of the semiconductor die.

[0016] [Symbol Explanation]

[0017] 10: Semiconductor grain transfer structure

[0018] 12: Semiconductor die / µLED driver

[0019] 12A: Semiconductor die

[0020] 12B: Semiconductor die

[0021] 12C: Semiconductor die

[0022] 12T: Target semiconductor die

[0023] 14: Bottom retainer

[0024] 16: Pick-up and Placement Tools

[0025] 18: Package surface

[0026] 20: Groups

[0027] 22: Micro-driver Components

[0028] 24: Electronic Components / Integrated Circuit Systems

[0029] 26: Top metal contact pad

[0030] 30: Carrier wafer

[0031] 34: Organic polymer layer / continuous layer

[0032] 36: Organic polymer column / column

[0033] 40: Proximal surface

[0034] 400: Flat proximal surface

[0035] 44: Groove

[0036] 44A: Groove

[0037] 44B: Groove

[0038] 44C: Groove

[0039] 46: Remote

[0040] 50: Wafer

[0041] 52: Dielectric layer

[0042] 54: Opening

[0043] AA: View

[0044] BB: Section

[0045] CC: Section

[0046] D: Depth

[0047] DD: Section

[0048] dp: diameter

[0049] EE: Section

[0050] FF: Section

[0051] H: Total height

[0052] HD: Distance Detailed Implementation

[0053] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0054] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0055] Semiconductor dies manufactured at semiconductor manufacturing facilities can be transported to customer locations or to the packaging assembly sections of these facilities, where they are placed onto the packaging surface of a semiconductor device package being manufactured. The packaging surface can be a printed circuit board, the surface of an LED display, another semiconductor wafer or die used to assemble a multi-chip package, etc. In commercial environments, this transfer process may require transferring a large number of semiconductor dies produced by dicing semiconductor wafers on which numerous integrated circuit (IC) dies have already been manufactured. Furthermore, the individual semiconductor dies transferred may be very small; for example, one side of a given semiconductor die may be a few micrometers or millimeters. The transfer process is automated using robots or other automated pick-and-place tools to provide rapid semiconductor die transfer while minimizing the possibility of contamination by human workers.

[0056] Figure 1A A schematic top view of a semiconductor die transfer structure 10 including a semiconductor die 12 disposed on a bottom holder 14 is illustrated. In this non-limiting illustrative example, the semiconductor die 12 is a micro-light emitting diode (µLED) driver (or more generally, an LED driver). However, more generally, the semiconductor die 12 may be an integrated circuit (IC) die or other types of semiconductor dies. In the illustrative example, the semiconductor die 12 is a silicon die (i.e., the IC, µLED driver, or other electronic or optoelectronic device of the semiconductor die 12 is made of silicon-based material). However, the semiconductor die 12 may be other types of semiconductor dies, such as gallium arsenide (GaAs) dies (i.e., the IC, µLED driver, or other electronic or optoelectronic device of the semiconductor die 12 is made of GaAs-based material), silicon germanium (Si... 1-x Ge x The chip (i.e., the IC, µLED driver, or other electronic or optoelectronic device of semiconductor chip 12) is Si 1-x Ge x (Made from base materials, etc.)

[0057] Pick-and-place tool 16 is used to transfer semiconductor die 12 from semiconductor die transfer structure 10 to package surface 18. In this non-limiting illustrative example, package surface 18 is the surface of LED display, and µLED drivers 12 are placed in 2×2 groups 20, with four µLED drivers 12 in each group. Subsequently, red, green, blue, and white LEDs (e.g., µLEDs) are placed on the four µLED drivers 12 in each of the 2×2 groups of µLED drivers 12 (step not shown) to form full-color pixels of the LED display being assembled. Figure 1A The pick-and-place tool 16 is shown in a side view, carrying the picked-up target semiconductor die (e.g., µLED driver) 12T. It should be understood that this process will be repeated to transfer a large number (possibly all) of the semiconductor dies 12 from the semiconductor die transfer structure 10 to the package surface 18. While in this example the package surface 18 is the surface of an LED display, more generally, the package surface 18 can be another package surface, such as a printed circuit board, another semiconductor wafer or die for assembling a multi-chip package, etc.

[0058] Figure 1B A side cross-sectional view of a pick-up and placement tool 16 is schematically illustrated during the process of picking up a target semiconductor die 12T from a semiconductor die transfer structure 10. In this non-limiting illustrative example, each semiconductor die 12 is a µLED driver, which includes a microdriver assembly 22 (such as a transistor or transistor-based LED driver) and is operatively coupled to, where appropriate, additional electronic components or integrated circuit systems 24. Each µLED driver further includes one or more top metal contact pads 26 through which the µLED (not shown) is electrically connected when the µLED is subsequently placed on the µLED driver 12. In some non-limiting illustrative embodiments, the one or more top contact pads 26 may be aluminum / copper (AlCu) pads, aluminum (Al) pads, copper (Cu) pads, etc. It should be noted that the configurations shown for elements 22, 24, and 26 are merely non-limiting illustrative examples, and more generally, semiconductor die 12 may be or include any type of semiconductor device, integrated circuit, etc.

[0059] Continue to refer to Figure 1BThe semiconductor die transfer structure 10 further includes a bottom holder 14 on which the semiconductor die 12 is disposed. The illustrative bottom holder 14 includes: a carrier wafer 30 coated with an organic polymer layer 34 made of an organic polymer material such as benzocyclobutene (BCB); and organic polymer pillars 36 made of an organic polymer material such as BCB. In an illustrative example, both the organic polymer layer 34 and the organic polymer pillars 36 are made of the same organic polymer material (e.g., BCB layer 34 and BCB pillars 36 in an illustrative example); however, it is conceivable that the organic polymer pillars are made of a different organic polymer material than the organic polymer layer. In an illustrative example, the carrier wafer 30 is a silicon wafer; however, it is conceivable that the carrier wafer is made of another material, such as sapphire or gallium arsenide (GaAs). The semiconductor die 12 is oriented such that the proximal surface 40 of the semiconductor die 12 faces the carrier wafer. The pillars 36 support the semiconductor die 12 on the carrier wafer 30 (in... Figure 1B In the embodiment, via the intermediate organic polymer layer 34).

[0060] The pick-and-place tool 16 picks up the target semiconductor die 12T by means of an electrostatic attraction between the pick-and-place tool 16 and the target semiconductor die 12T. This has the advantage of not applying strong force to the potentially fragile target semiconductor die 12T and not transferring adhesive or other bonding materials onto the target semiconductor die 12T. However, it should be understood that the electrostatic attraction between the pick-and-place tool 16 and the target semiconductor die 12T is relatively weak. Therefore, the engagement between the target semiconductor die 12T and the bottom holder 14 should be weak enough that the electrostatic attraction of the pick-and-place tool 16 can overcome this engagement and peel the target semiconductor die 12T from the bottom holder 14. The semiconductor die 12 is secured to the bottom holder 14 by using a post 36 to achieve a weak engagement between the semiconductor die 12T and the bottom holder 14. Compared to the large contact area present when the proximal surface 40 of the semiconductor die 12 directly contacts the continuous layer 34 of the organic polymer material, the pillar 36 provides a relatively small contact area with the proximal surface 40 of the semiconductor die 12. For example... Figure 1B As can be seen, the relatively small contact area provided by post 36 provides a contact that can be overcome by the electrostatic attraction between the target semiconductor die 12T and the pick-and-place tool 16, so as to disrupt the bonding between the proximal surface 40 of the target semiconductor die 12T and post 36.

[0061] On the other hand, the bonding between the semiconductor die 12 and the bottom holder 14 should be strong enough to prevent the semiconductor die 12 from unintentionally detaching from the bottom holder 14. Such semiconductor die detachment events are referred to as flyers and reduce the yield of the effective device because any semiconductor die 12 detached from the bottom holder 14 may be lost, or at least damaged or potentially damaged, and therefore considered unusable. The relatively low bonding strength provided by the post 36, while advantageously facilitating electrostatic pickup by the pick-and-place tool 16, may also have the disadvantage of increasing the flyer rate.

[0062] Continue to refer to Figure 1A and Figure 1B And now for further reference Figure 2A , Figure 2B , Figure 3A and Figure 3B By providing a groove 44 in the proximal surface 40 of the semiconductor die 12 and filling the groove 44 in the proximal surface 40 of the semiconductor die 12 with the distal end 46 of the post 36, the possibility of die flyaway is suppressed. (It should be noted that...) Figure 2B and Figure 3B Drawing and Figure 1B (Compared to semiconductor grains 12 with different aspect ratios, this illustrates that the disclosed semiconductor grains and grain transfer assemblies are not limited to conductor grains having any particular grain aspect ratio.) Figure 2A schematically showing along Figure 2B View AA, as indicated in the figure, is a bottom view of the semiconductor grain 12 of the semiconductor grain transfer structure 10. Conversely, Figure 2B schematically showing along Figure 2A The cross section BB shown in the figure is a side cross section view of a portion of the semiconductor grain transfer structure 10, including a representative semiconductor grain 12. Figure 3A and Figure 3B schematically shown Figure 2A and Figure 2B A view of a representative semiconductor die 12 of the semiconductor die transfer structure 10, wherein: Figure 3A A schematic bottom view of semiconductor die 12 is shown; and Figure 3B schematically showing along Figure 3A The section CC indicated in the figure is a cross-sectional view of the semiconductor die 12. Figure 3A and Figure 3B A view of the semiconductor die 12 is illustrated, showing a groove 44 in the proximal surface 40 of the illustrative semiconductor die 12. (See diagram below.) Figure 3B As indicated, groove 44 has Figure 3B The depth D marked in the middle. Figure 3AA non-limiting illustrative embodiment is shown, wherein there are five grooves 44 on the proximal surface 40 of the illustrative semiconductor die 12, such that the posts 36 engaging with the grooves 44 (in) Figure 2A and Figure 2B (shown in the figure) provides balanced support for the illustrative semiconductor die 12 on the bottom holder 14. Although five grooves 44 in the proximal surface 40 of the illustrative semiconductor die 12 are shown, this is merely a non-limiting illustrative example, and more generally, the number of grooves 44 and corresponding support posts 36 may be two, three, four, five, six, seven or more, and may have various geometric configurations.

[0063] Figure 2A and Figure 2B The pillars 36 supporting the illustrative semiconductor die 12 are shown. Especially in... Figure 2B As can be seen, the distal end 46 of each pillar 36 fills the corresponding groove 44 in the proximal surface 40 of the semiconductor die 12. Therefore, the distal end 46 of the polymer pillar 36 engages with the groove 44 in the proximal surface 40 of the semiconductor die 12. For a given diameter or other cross-sectional size of the pillar 36, this configuration of the distal end 46 engaging with the individual groove 44 in the proximal surface 40 of the semiconductor die 12 advantageously increases the total contact surface area between the distal end 46 of the polymer pillar 36 and the silicon or other material of the proximal surface 40 of the semiconductor die 12, compared to the case where the groove 44 is omitted and the distal end of the polymer pillar is adjacent to the flat proximal surface of the semiconductor die.

[0064] For example, if the diameter of each column 36 is d p Without groove 44, the total contact area of ​​this column should be: Since the groove depth of groove 44 is D, the contact area increases to The additional contact area The lateral area of ​​the cylinder of the groove 44 is given. Furthermore, the arrangement of the distal end 46 of the pillar 36 engaging with the individual grooves 44 in the proximal surface 40 of the semiconductor die 12 can further enhance the retention strength of the semiconductor die 12 on the bottom holder 14 through the three-dimensional surface contact geometry (i.e., contact at both the top and the side of the distal end 46).

[0065] Therefore, the configuration of the distal end 46 of the pillar 36 filling the corresponding groove 44 in the proximal surface 40 supporting the semiconductor die 12 (i.e., the distal end 46 of the organic polymer pillar 36 engages with the groove 44 in the proximal surface 40 of the semiconductor die 12) advantageously increases the retention strength of the semiconductor die 12 on the bottom holder 14. This reduces die fly defects and improves the yield of the semiconductor die 12 transferred from the semiconductor die transfer structure 10 to the package surface 18.

[0066] Another advantage of this method is that the additional holding force provided by the grooves 44 in the proximal surface 40 of the semiconductor die 12 can be adjusted by adjusting the depth D of the grooves 44 and / or by adjusting the geometry of the grooves 44, as referred to later herein. Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A and Figure 7B As described. This is advantageous because it allows for adjustment of the holding force to balance the reduction (or elimination) of flyaway defects, while ensuring that the holding force is not too strong, thereby preventing the pick-up and placement tool 16 (see...) Figure 1A and Figure 1B The semiconductor die 12 can be reliably picked up from the semiconductor die transfer structure 10 by the relatively weak electrostatic attraction of the semiconductor die 12. In some embodiments, the groove 44 in the proximal surface 40 of the semiconductor die 12 has a depth D greater than zero and 6 micrometers or less. In some embodiments, the groove 44 in the proximal surface 40 of the semiconductor die 12 has a depth D between 0.5 micrometers and 6 micrometers. It is expected that these depth ranges will provide an appropriate balance between minimizing or eliminating flyaways (by increasing the holding force) and enabling the pick-and-place tool 16 to reliably pick up the semiconductor die 12 (by ensuring that the holding force is not too strong). However, it should be understood that these illustrative depth ranges are not limiting, and larger or smaller values ​​of the depth D of the groove 44 in the proximal surface 40 of the semiconductor die 12 can be considered. For example, if in a particular design of the semiconductor die transfer structure 10 the diameter d of the organic polymer pillar 36 is... p A smaller diameter allows for the use of a greater groove depth D to compensate for the reduced holding force caused by the smaller diameter of the organic polymer pillar 36. As another example, if the area of ​​the semiconductor die 12 is larger, a greater holding force can be provided by increasing the groove depth D (while a larger semiconductor die can provide a higher electrostatic attraction, ensuring that the increased holding force provided by the increased groove depth D does not adversely affect the reliability of the pick-and-place tool 16 in picking up the semiconductor die 12). These are merely some non-limiting examples of groove depth ranges and some possible relevant criteria for optimizing the groove depth of a particular semiconductor die transfer structure 10. It should be understood that the groove depth D of a given semiconductor die transfer structure 10 can also be empirically optimized by constructing test semiconductor die transfer structures with different groove depth D values ​​and experimentally evaluating the flyaway rate and efficiency of picking up semiconductor dies using the pick-and-place tool.

[0067] refer to Figure 2BIf the organic polymer pillar 36 has a total height H from its connection with the continuous layer 34 of the organic polymer material to its distal end 46 (the very end), and the groove 44 in the proximal surface 40 of the semiconductor die 12 has a depth D, then the organic polymer pillar 36 spacees the proximal surface 40 of the semiconductor die 12 from the continuous layer 34 of the organic polymer material by a distance HD, such as... Figure 2B As indicated. In some non-limiting illustrative examples, the organic polymer column 36 may have a diameter d between 0.5 micrometers and 0.7 micrometers. P However, this is merely a non-limiting example. In some non-limiting illustrative examples, the thickness of the continuous layer 34 of organic material can be in the range of 3 micrometers to 5 micrometers, but this is also merely a non-limiting example.

[0068] Now for reference Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E A non-limiting example of a method for manufacturing a semiconductor grain transfer structure 10 is schematically shown using a side cross-sectional view of the continuous manufacturing stage of the semiconductor grain transfer structure 10.

[0069] Figure 4A The manufactured semiconductor die 12 is illustrated. The manufactured semiconductor die 12 is substantially similar to the semiconductor die 12 of the final semiconductor die transfer structure 10, except that it has a flat proximal surface 400 (wherein the flat proximal surface 400 corresponds to the proximal surface 40 of the final semiconductor die transfer structure 10). Figure 4A During the manufacturing stage, the semiconductor die 12 has a flat proximal surface 400 because the groove 44 has not yet been formed. Figure 4A The illustrative semiconductor die 12 shown is fully fabricated and includes a micro-driver assembly 22, additional electronic components or integrated circuit systems 24 (optional), and one or more top metal contact pads 26.

[0070] Another difference between the semiconductor die 12 of the final semiconductor die transfer structure 10 and the choice thereof is that, in Figure 4A During the manufacturing stage, the semiconductor die 12 may not yet be monomerized (e.g., cut using a cutting saw, laser dicing, etc.). This is due to Figure 4A The wafer 50 indicated by the dashed line is schematically shown. For example, wafer 50 may be a silicon wafer, on which semiconductor dies 12 are fabricated. In some such embodiments, wafer 50 may be thinned or otherwise processed (other than the process of forming semiconductor dies 12).

[0071] refer to Figure 4BA dielectric layer 52 is disposed on the flat near-side surface 400 of the semiconductor die 12. If the semiconductor die 12 has not yet been monomerized, the dielectric layer 52 is suitably disposed as a continuous layer above the entire corresponding surface of the wafer 50. The dielectric layer 52 may be an oxide, such as silicon dioxide (SiO2), silicon oxynitride (SiON), etc., or may be a nitride, such as silicon nitride (Si3N4), etc.

[0072] refer to Figure 4C Photolithography-controlled etching is performed to etch openings 54 in the dielectric layer 52. These openings 54 correspond to predetermined pillars 36. Etching continues into the (flat) proximal surface 400 to form grooves 44 in the (finally non-flat) proximal surface 40 of the semiconductor die 12. Figure 4C If the semiconductor die 12 has not yet been monomerized at the processing stage shown, then the continuous dielectric layer 52 spanning the corresponding surface of the wafer 50 is etched, wherein the openings 54 in the dielectric layer 52 are etched at positions corresponding to the predetermined organic polymer pillars 36 of the final semiconductor die transfer structure 10.

[0073] Etching may be performed in various ways to form an opening 54 in the dielectric layer 52 and to continue forming a groove 44 in the proximal surface 40 of the semiconductor die 12. In one method, a photomask is formed by photoresist deposition, photolithography, and development, such that the developed photomask has an opening corresponding to the opening 54. Subsequently, wet or dry etching is performed using the developed photomask to confine the etching to the opening 54. The etchant is effective for etching the dielectric material of the dielectric layer 52. If the etchant is also effective for etching the silicon (or other material) of the proximal surface 40 of the semiconductor die 12, the etching can be timed to etch completely through the opening 54 of the dielectric layer 52 and further into the proximal surface 40 of the semiconductor die 12 to form a groove 44 in the proximal surface 40 of the semiconductor die 12. In this method, the opening 54 through the dielectric layer 52 is self-aligned with the groove 44 in the proximal surface 40 of the semiconductor die 12.

[0074] In a variant of the method, the etching used to form the opening 54 through the dielectric layer 52 may be ineffective for etching the material of the proximal surface 40 of the semiconductor die 12. In this case, the flat proximal surface 400 of the semiconductor die 12 serves as an etch stop layer for etching the opening 54 through the dielectric layer 52. Subsequently, different wet or dry etchants can be applied to effectively etch the material of the proximal surface 40 of the semiconductor die 12, thereby forming a groove 44 in the proximal surface 40 of the semiconductor die 12. In this second etching step, the opening 54 through the dielectric layer 52 serves as a self-aligning mask to align the etched groove 44 with the previously etched opening 54 through the dielectric layer 52.

[0075] These are merely some non-limiting illustrative methods for etching openings 54 in dielectric layer 52 and continuing etching into the proximal surface 40 of semiconductor die 12 to form grooves 44 in the proximal surface 40 of semiconductor die 12. Other methods may be considered, such as employing a dedicated thin etch stop layer applied to the flat proximal surface 400 of semiconductor die 12 to provide etch depth control.

[0076] Now for reference Figure 4D An organic polymer material is used to bond the dielectric layer 52 (with etched openings 54) to the carrier wafer 30. The organic polymer material used in this bonding forms a continuous layer 34 of organic polymer material. Furthermore, during bonding, the organic polymer material also flows into and fills the openings 54 in the dielectric layer 52, and continues to flow into and fill the grooves 44 in the proximal surface 40 of the semiconductor die 12 to form pillars 36 with distal ends 46 filling the grooves 44 in the proximal surface 40 of the semiconductor die 12. Figure 4D If the semiconductor die 12 has not yet been monomerized at the processing stage shown, this bonding constitutes a wafer bonding of the wafer 50 containing or including the semiconductor die 12 (and more specifically, the dielectric layer 52 disposed thereon) to the carrier wafer 30. Organic polymer materials such as BCB are effective for wafer-to-wafer or die-to-wafer bonding, and thus the continuous organic polymer layer 34 provides a suitable bonding between the semiconductor die 12 (or wafer 50) and the carrier wafer 30.

[0077] refer to Figure 4E The dielectric layer 52 is removed to complete the fabrication of the final semiconductor die transfer structure 10. For example, this can be achieved using an etchant that selectively etches the material of the dielectric layer 52 without etching the BCB or other organic polymer materials constituting the continuous organic polymer layer 34 and organic polymer pillars 36. If the semiconductor die 12 has not yet been monomerized, monomerization can be performed using a dicing saw, laser dicing, or the like. If monomerization is completed before removing the dielectric layer 52, the dielectric layer 52 can provide structural support during dicing, laser dicing, etc.; furthermore, the removed material provides an enhanced pathway for the selective etchant to reach and dissolve the dielectric layer 52 during monomerization.

[0078] It should be understood that this article references... Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The manufacturing process described is merely a non-limiting illustrative example, and other manufacturing workflows or processes may be used to manufacture the semiconductor die transfer structure 10.

[0079] In the illustrative examples to date, the organic polymer pillar 36 has a circular cross-section, and the groove 44 in the proximal surface 40 of the semiconductor die 12 has an aligned circular cross-section. However, more generally, the groove in the proximal surface 40 of the semiconductor die 12 may be a circular groove (e.g., groove 44), an annular groove, a cross-shaped groove, a parallel strip groove, or other cross-sections.

[0080] For example, Figure 5A and Figure 5B A schematic view of a representative semiconductor die 12A of a semiconductor die transfer structure 10 according to another embodiment is shown. Figure 5A A bottom view of the semiconductor die 12A, including the proximal surface 40 of the semiconductor die 12A, is schematically shown. Figure 5B schematically showing along Figure 5A The section DD shown is a cross-sectional view of semiconductor die 12A taken from the section indicated in the figure. Figure 5A and Figure 5B The semiconductor die 12A is similar to the previous reference, for example Figure 3A and Figure 3B The semiconductor die 12 described is identical, except that the groove 44A in the proximal surface 40 of the semiconductor die 12A has a different cross-sectional geometry than the circular cross-sectional groove 44 in the proximal surface 40 of the semiconductor die 12. The groove 44A in the proximal surface 40 of the semiconductor die 12A is a cross-shaped groove. This advantageously increases the contact area between the silicon (or other material) of the proximal surface 40 of the semiconductor die 12A and the organic polymer of the distal end 46 of the organic polymer pillar 36, thereby (further) increasing the holding force for holding the semiconductor die 12 to the bottom holder 14. The groove 44A has an indicated groove depth D. In some embodiments, the depth D of the cross-shaped groove 44A is greater than zero and is 6 micrometers or less. In some embodiments, the depth D of the cross-shaped groove 44A is between 0.5 micrometers and 6 micrometers. These are also merely non-limiting illustrative examples of suitable depths for certain particular embodiments. The corresponding organic polymer pillar 36 may also have a cross-shaped cross-section that matches the cross-shaped cross-section of the groove 44A, but this is not required.

[0081] Figure 6A and Figure 6B A schematic view of a representative semiconductor die 12B of a semiconductor die transfer structure 10 according to another embodiment is shown. Figure 6A A bottom view of the semiconductor die 12B, including the proximal surface 40 of the semiconductor die 12B, is schematically shown. Figure 6B schematically showing along Figure 6A The section EE shown in the figure is a cross-sectional view of semiconductor die 12B. Figure 6A and Figure 6B The semiconductor die 12B is similar to the previous reference, for example Figure 3A and Figure 3B The semiconductor die 12 described is identical except that the groove 44B in the proximal surface 40 of the semiconductor die 12B has a different cross-sectional geometry than the circular cross-sectional groove 44 in the proximal surface 40 of the semiconductor die 12. The groove 44B in the proximal surface 40 of the semiconductor die 12B is an annular groove. This advantageously increases the contact area between the silicon (or other material) of the proximal surface 40 of the semiconductor die 12B and the organic polymer of the distal end 46 of the organic polymer pillar 36, thereby (further) increasing the holding force for holding the semiconductor die 12 to the bottom holder 14. The groove 44B has an indicated groove depth D. In some embodiments, the depth D of the annular groove 44B is greater than zero and is 6 micrometers or less. In some embodiments, the depth D of the annular groove 44B is between 0.5 micrometers and 6 micrometers. These are also merely non-limiting illustrative examples of suitable depths for certain particular embodiments. The corresponding organic polymer pillar 36 may also have an annular cross-section that matches the annular cross-section of the groove 44B, but this is not required.

[0082] Figure 7A and Figure 7B A schematic view of a representative semiconductor die 12C of a semiconductor die transfer structure 10 according to another embodiment is shown. Figure 7A A bottom view of a semiconductor die 12C, including its proximal surface 40, is schematically shown. Figure 7B schematically showing along Figure 7A The section FF shown is a cross-sectional view of semiconductor die 12C taken from the section indicated in the figure. Figure 7A and Figure 7B The semiconductor die 12C is similar to the previous reference, for example Figure 3A and Figure 3B The semiconductor die 12 described is identical except that the groove 44C in the proximal surface 40 of the semiconductor die 12C has a different cross-sectional geometry than the circular cross-sectional groove 44 in the proximal surface 40 of the semiconductor die 12.

[0083] The groove 44C in the proximal surface 40 of the semiconductor die 12C is a parallel strip groove. This advantageously increases the contact area between the silicon (or other material) of the proximal surface 40 of the semiconductor die 12C and the organic polymer of the distal end 46 of the organic polymer pillar 36, thereby (further) increasing the holding force for holding the semiconductor die 12 to the bottom holder 14. The groove 44C has an indicated groove depth D. In some embodiments, the depth D of the parallel strip groove 44C is greater than zero and is 6 micrometers or less. In some embodiments, the depth D of the parallel strip groove 44C is between 0.5 micrometers and 6 micrometers. These are also merely non-limiting illustrative examples of suitable depths for certain particular embodiments. The corresponding organic polymer pillar 36 may also have a parallel strip cross-section that matches the parallel strip cross-section of the groove 44C, but this is not required.

[0084] Some other embodiments are described below.

[0085] In a non-limiting illustrative embodiment, a semiconductor die transfer assembly includes: a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and pillars comprising an organic polymer material supporting the semiconductor die on the carrier wafer. The pillars have distal ends that fill grooves in the proximal surface of the semiconductor die. In some embodiments, the grooves in the proximal surface of the semiconductor die have multiple depths between 0.5 micrometers and 6 micrometers. In some embodiments, the semiconductor die transfer assembly further includes a continuous layer of organic polymer material disposed on the carrier wafer, wherein multiple proximal ends of the organic polymer pillars are connected to the continuous layer of organic polymer material. In some embodiments, the pillars have a height H from the connection point between the pillar and the continuous layer of organic polymer material to the distal end of the pillar, the grooves in the proximal surface of the semiconductor die have a depth D, and the pillars space the proximal surface of the semiconductor die from the continuous layer of organic polymer material by a distance HD. In some embodiments, the grooves in the proximal surface of the semiconductor die are multiple circular grooves, multiple annular grooves, multiple cross-shaped grooves, or multiple parallel strip grooves. In some embodiments, the organic polymer material is benzocyclobutene (BCB). In some embodiments, the carrier wafer is a silicon wafer. In some embodiments, the semiconductor die is a plurality of light-emitting diode drivers.

[0086] In a non-limiting illustrative embodiment, a semiconductor die transfer method includes: providing a semiconductor die transfer structure, the semiconductor die transfer structure including: a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a pillar comprising an organic polymer material supporting the semiconductor die on the carrier wafer, the pillar having a distal end that fills a groove in the proximal surface of the semiconductor die; and picking up a target semiconductor die of the semiconductor die transfer structure using a pick-and-place tool, the pick-and-place tool electrostatically attracting the target semiconductor die to the pick-and-place tool and placing the target semiconductor die on a package surface. In some embodiments, the step of providing a semiconductor die transfer structure includes forming a dielectric layer on a proximal surface of a semiconductor die; etching a plurality of openings in the dielectric layer and continuing etching into the proximal surface of the semiconductor die to form grooves in the proximal surface of the semiconductor die; bonding the dielectric layer to a carrier wafer using an organic polymer material, wherein the organic polymer material also fills the openings in the dielectric layer and the grooves in the proximal surface of the semiconductor die to form pillars having a plurality of distal ends filling the grooves in the proximal surface of the semiconductor die; and removing the dielectric layer. In some embodiments, the step of bonding the dielectric layer to the carrier wafer using an organic polymer material further forms a continuous layer of organic polymer material on the carrier wafer. In some embodiments, the grooves in the proximal surface of the semiconductor die are a plurality of circular grooves, a plurality of annular grooves, a plurality of cross-shaped grooves, or a plurality of parallel strip grooves. In some embodiments, the step of picking up a target semiconductor die includes separating the distal ends of the pillars supporting the target semiconductor die from the grooves in the proximal surface of the target semiconductor die. In some embodiments, the organic polymer material is benzocyclobutene (BCB). In some embodiments, the semiconductor die includes a plurality of light-emitting diode (LED) drivers, and a target LED driver is placed on the surface of the LED display. In some embodiments, a pick-and-place tool is repeatedly used to pick up the target semiconductor die of the semiconductor die transfer structure to transfer a plurality of semiconductor dies from the semiconductor die transfer structure to the package surface.

[0087] In a non-limiting illustrative embodiment, a semiconductor die transfer method includes: providing a semiconductor die transfer structure, the semiconductor die transfer structure including: a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a pillar comprising an organic polymer material supporting the semiconductor die on the carrier wafer, the pillar having a distal end that fills a groove in the proximal surface of the semiconductor die; and picking up a target semiconductor die of the semiconductor die transfer structure using a pick-and-place tool, the pick-and-place tool electrostatically attracting the target semiconductor die to the pick-and-place tool and placing the target semiconductor die on a package surface. Providing a semiconductor die transfer structure includes: depositing a dielectric layer on a proximal surface of a semiconductor die; etching an opening in the dielectric layer and continuing etching into the proximal surface of the semiconductor die to form a groove in the proximal surface of the semiconductor die; bonding the dielectric layer to a carrier wafer using an organic polymer material, wherein the polymer material also fills the opening in the dielectric layer and the groove in the proximal surface of the semiconductor die to form a pillar having a distal end filled with the groove in the proximal surface of the semiconductor die; and removing the dielectric layer.

[0088] In a non-limiting illustrative embodiment, a semiconductor structure includes: a semiconductor die having a flat surface; and a groove disposed in the flat surface of the semiconductor die. In some embodiments, the groove in the flat surface of the semiconductor die has a depth between 0.5 micrometers and 6 micrometers. In some embodiments, the semiconductor die includes a light-emitting diode (LED) driver. In some embodiments, the groove in the flat surface of the semiconductor die is a circular groove, an annular groove, a cross-shaped groove, or a parallel strip groove.

[0089] In a non-limiting illustrative embodiment, an assembly for semiconductor die transfer includes: a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a pillar comprising an organic polymer material supporting the semiconductor die on the carrier wafer. The pillar has a distal end that fills a groove in the proximal surface of the semiconductor die. The semiconductor die in the semiconductor die transfer structure is picked up using a pick-and-place tool. To fabricate the structure, a dielectric layer is disposed on the proximal surface of the semiconductor die, and openings are etched in the dielectric layer, and etching continues into the proximal surface of the semiconductor die to form grooves therein. The dielectric layer is bonded to the carrier wafer using an organic polymer material, which also fills the openings in the dielectric layer and the grooves in the proximal surface of the semiconductor die. The dielectric layer is then removed.

[0090] In a non-limiting illustrative embodiment, a semiconductor die transfer assembly includes a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the semiconductor die. In some embodiments, the groove in the proximal surface of the semiconductor die has a plurality of depths between 0.5 micrometers and 6 micrometers. In some embodiments, the semiconductor die transfer assembly further includes a continuous layer disposed on the carrier wafer, wherein a plurality of proximal ends of the plurality of pillars are connected to the continuous layer. In some embodiments, the plurality of pillars have a height from their connection to the continuous layer to the distal ends of the plurality of pillars, the grooves in the proximal surface of the semiconductor die have depths, and the plurality of pillars space the proximal surface of the semiconductor die from the continuous layer by a distance. In some embodiments, the grooves in the proximal surface of the semiconductor die are a plurality of circular grooves, a plurality of annular grooves, a plurality of cross-shaped grooves, or a plurality of parallel strip grooves.

[0091] In a non-limiting illustrative embodiment, a semiconductor die transfer assembly includes a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the semiconductor die. The semiconductor die is a plurality of light-emitting diode drivers. In some embodiments, the grooves in the proximal surface of the semiconductor die have a plurality of depths between 0.5 micrometers and 6 micrometers. In some embodiments, the semiconductor die transfer assembly further includes a continuous layer disposed on the carrier wafer, wherein the plurality of proximal ends of the plurality of pillars are connected to the continuous layer.

[0092] In a non-limiting illustrative embodiment, a semiconductor die transfer assembly includes a carrier wafer; a semiconductor die oriented with its proximal surface facing the carrier wafer; and a plurality of pillars. Each pillar has a distal end that fills a groove in the proximal surface of the semiconductor die. The grooves have a plurality of depths between 0.5 micrometers and six micrometers. In some embodiments, the grooves in the proximal surface of the semiconductor die are a plurality of circular grooves, a plurality of annular grooves, a plurality of cross-shaped grooves, or a plurality of parallel strip grooves.

[0093] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor die transfer assembly, characterized in that, Include: One carrier wafer; Multiple semiconductor grains are oriented such that multiple proximal surfaces of the multiple semiconductor grains face the carrier wafer; and A plurality of pillars having a plurality of distal ends having a plurality of grooves in a plurality of proximal surfaces of a plurality of semiconductor grains.

2. The semiconductor die transfer assembly as described in claim 1, characterized in that, The plurality of grooves in the plurality of proximal surfaces of the plurality of semiconductor grains have a plurality of depths between 0.5 micrometers and 6 micrometers.

3. The semiconductor die transfer assembly as described in claim 1, characterized in that, Further includes: A continuous layer is disposed on the carrier wafer, wherein the proximal ends of the plurality of pillars are connected to the continuous layer.

4. The semiconductor die transfer assembly as described in claim 3, characterized in that, in: The plurality of columns have a height from their connection point with the continuous layer to their plurality of distal ends. The plurality of grooves in the plurality of proximal surfaces of the plurality of semiconductor grains have depth, and The plurality of pillars space the plurality of proximal surfaces of the plurality of semiconductor grains apart from the continuous layer by a distance.

5. The semiconductor die transfer assembly as described in claim 1, characterized in that, The plurality of grooves in the plurality of proximal surfaces of the plurality of semiconductor grains are plurality of circular grooves, plurality of annular grooves, plurality of cross-shaped grooves, or plurality of parallel strip grooves.

6. A semiconductor die transfer assembly, characterized in that, Include: One carrier wafer; Multiple semiconductor dies are oriented such that multiple proximal surfaces of the multiple semiconductor dies face the carrier wafer, wherein the multiple semiconductor dies are multiple light-emitting diode drivers; and A plurality of pillars having a plurality of distal ends that fill a plurality of grooves in a plurality of proximal surfaces of a plurality of light-emitting diode drivers.

7. The semiconductor die transfer assembly as described in claim 6, characterized in that, The plurality of grooves in the plurality of proximal surfaces of the plurality of semiconductor grains have a plurality of depths between 0.5 micrometers and 6 micrometers.

8. The semiconductor die transfer assembly as described in claim 6, characterized in that, Further includes: A continuous layer is disposed on the carrier wafer, wherein the proximal ends of the plurality of pillars are connected to the continuous layer.

9. A semiconductor die transfer assembly, characterized in that, Include: One carrier wafer; Multiple semiconductor dies are oriented such that multiple proximal surfaces of the multiple semiconductor dies face the carrier wafer, wherein the multiple semiconductor dies are multiple light-emitting diode drivers; and Multiple pillars having multiple distal ends of multiple grooves filling multiple proximal surfaces of multiple light-emitting diode drivers, wherein the multiple grooves have multiple depths between 0.5 micrometers and 6 micrometers.

10. The semiconductor die transfer assembly as claimed in claim 9, characterized in that, The plurality of grooves in the plurality of proximal surfaces of the plurality of semiconductor grains are plurality of circular grooves, plurality of annular grooves, plurality of cross-shaped grooves, or plurality of parallel strip grooves.

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