A power semiconductor module package structure

Abstract

The application provides a power semiconductor module packaging structure, which comprises a substrate and a heat dissipation structure, and a three-phase circuit is arranged on the substrate; wherein the three-phase circuit comprises a first-phase bridge, a second-phase bridge and a third-phase bridge; and the included angle between the first-phase bridge, the second-phase bridge and the third-phase bridge is 120 DEG; the heat dissipation structure is arranged on at least one side of the substrate and is used for dissipating heat of the three-phase circuit. Specifically, in the power semiconductor module packaging structure provided by the application, the included angle between the first-phase bridge, the second-phase bridge and the third-phase bridge of the three-phase circuit is 120 DEG and arranged in an isosceles triangle, so that the layout among the three-phase bridges is more compact, the floor area is reduced, and the power density of the system is improved; and further, the heat dissipation structure is arranged on at least one side of the substrate, and the heat dissipation structure can improve the heat conduction capacity of the three-phase circuit and improve the heat exchange efficiency between the three-phase circuit and the outside.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power semiconductor module packaging structure. Background Technology

[0002] Power semiconductor module packaging structure is the process of packaging a manufactured bare chip (die) into a complete electronic component through specific technologies and processes to facilitate installation, protection and electrical connection.

[0003] However, the heat dissipation capacity of the power semiconductor module packaging structure in the related technology is insufficient; and the size of its internal three-phase circuit is large, which is not conducive to improving the power density of the system. Utility Model Content

[0004] To address the aforementioned problems, this application provides a solution that resolves the issues of large three-phase circuit size and insufficient heat dissipation in power semiconductor module packaging structures.

[0005] To address the aforementioned problems, the first technical solution provided in this application is: to provide a power semiconductor module packaging structure, comprising:

[0006] A substrate on which a three-phase circuit is disposed; wherein the three-phase circuit includes a first phase bridge, a second phase bridge and a third phase bridge; and the included angle between each pair of the first phase bridge, the second phase bridge and the third phase bridge is 120°.

[0007] A heat dissipation structure is disposed on at least one side of the substrate for dissipating heat from the three-phase circuit.

[0008] In one embodiment, the heat dissipation structure includes a plurality of heat dissipation fins, which are located on the side of the substrate away from the three-phase circuit, and at least one end of the plurality of heat dissipation fins extends toward the edge of the substrate.

[0009] In one embodiment, a plurality of heat dissipation fins are arranged in parallel and spaced apart, and both ends of each heat dissipation fin extend toward the edge of the substrate.

[0010] In one embodiment, the first ends of the plurality of heat dissipation fins are connected and have an included angle, and the second ends of the plurality of heat dissipation fins extend toward the edge of the substrate.

[0011] In one embodiment, the heat dissipation structure further includes a base plate and an annular portion, the substrate and the plurality of heat dissipation fins are located on opposite sides of the base plate, and the annular portion extends from the edge of the base plate toward one side of the substrate.

[0012] In one embodiment, the substrate has mounting holes; a portion of the base plate is exposed through the mounting holes.

[0013] In one embodiment, the first phase bridge, the second phase bridge, and the third phase bridge each include an upper-side chip and a lower-side chip;

[0014] Both the upper-side chip and the lower-side chip are formed by connecting multiple semiconductor chips in parallel.

[0015] In one embodiment, the first phase bridge, the second phase bridge, and the third phase bridge each include a plurality of electrically insulated conductive regions; the plurality of conductive regions include a positive conductive region, a negative conductive region, an intermediate conductive region, an upper gate drive conductive region, a lower gate drive conductive region, and an AC conductive region;

[0016] The upper transistor chip is disposed in the positive conductive region so that the drain of the upper transistor chip is connected to the positive conductive region, and the gate of the upper transistor chip is connected to the upper transistor gate drive conductive region through a bonding wire. The power source of the upper transistor chip is also connected to the AC conductive region.

[0017] The lower transistor chip is disposed in the intermediate electrode conductive region so that the drain of the lower transistor chip is connected to the intermediate electrode conductive region, and the drain of the lower transistor chip is also connected to the AC conductive region. The gate of the lower transistor chip is connected to the lower transistor gate drive conductive region through a bonding wire, and the power source of the lower transistor chip is connected to the negative electrode conductive region through a bonding wire.

[0018] In one embodiment, the plurality of conductive regions further include an inlet current detection conductive region connected to the intermediate electrode conductive region and an outlet current detection conductive region connected to the AC conductive region;

[0019] The first phase bridge, the second phase bridge, and the third phase bridge all include a current sampling resistor. One end of the current sampling resistor is connected to the intermediate electrode conductive region, and the other end of the current sampling resistor is connected to the AC conductive region.

[0020] The power source of the upper transistor chip and the drain of the lower transistor chip are both connected to the AC conductive region through the current sampling resistor.

[0021] In one embodiment, the insulating layer in the substrate includes a first side, a second side, and a third side; and a first transition edge connecting the first side and the second side, a second transition edge connecting the second side and the third side, and a third transition edge connecting the first side and the third side;

[0022] The included angle between each pair of the first side, the second side, and the third side is 60°, and the extensions of the first side, the second side, and the third side intersect each other to form an equilateral triangle.

[0023] The beneficial effects of this application are that, unlike the prior art, in the power semiconductor module packaging structure provided by this application, the first phase bridge, the second phase bridge, and the third phase bridge of the three-phase circuit are arranged in an isosceles triangle with an angle of 120° between each pair, which makes the layout between the three phase bridges more compact, reduces the floor space, and helps to improve the power density of the system; and furthermore, a heat dissipation structure is provided on at least one side of the substrate, which can improve the heat conduction capacity of the three-phase circuit and improve the heat exchange efficiency between the three-phase circuit and the outside world. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0025] Figure 1 A perspective view of a power semiconductor module package structure provided in an embodiment of this application;

[0026] Figure 2 A side view of a substrate provided in an embodiment of this application;

[0027] Figure 3 A perspective view of a substrate provided in an embodiment of this application;

[0028] Figure 4 A bottom view of a power semiconductor module package structure provided in an embodiment of this application;

[0029] Figure 5 A bottom view of a power semiconductor module package structure provided in another embodiment of this application;

[0030] Figure 6 A top view of a portion of the structure of a substrate provided in an embodiment of this application;

[0031] Figure 7 A top view of a portion of the structure of a substrate provided in another embodiment of this application;

[0032] Figure 8 A top view of a portion of the structure of a substrate provided in yet another embodiment of this application;

[0033] Figure 9A top view of a portion of the structure of a substrate provided in another embodiment of this application;

[0034] Figure 10 A top view of a power semiconductor module package structure provided in an embodiment of this application;

[0035] Figure 11 A perspective view of a power semiconductor module package structure provided in another embodiment of this application;

[0036] Figure 12 The circuit topology diagram of a power semiconductor module package structure provided in an embodiment of this application is shown. Specific Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0041] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0042] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0043] See Figures 1-6 , Figure 1 A perspective view of a power semiconductor module package structure provided in an embodiment of this application; Figure 2 A side view of a substrate provided in an embodiment of this application; Figure 3 A perspective view of a substrate provided in an embodiment of this application; Figure 4 A bottom view of a power semiconductor module package structure provided in an embodiment of this application; Figure 5 A bottom view of a power semiconductor module package structure provided in another embodiment of this application; Figure 6 This is a top view of a portion of the structure of a substrate provided in an embodiment of this application.

[0044] In this embodiment, the power semiconductor module packaging structure includes a substrate 1 and a heat dissipation structure 2; wherein, the substrate 1 includes a first metal layer 1-3, an insulating layer 1-1, and a second metal layer 1-2 stacked sequentially. The insulating layer 1-1 provides mechanical support, heat transfer, and insulation for the upper and lower metal layers, and the second metal layer 1-2 is divided into multiple conductive regions (see...). Figure 6Multiple semiconductor chips are soldered onto at least a portion of the conductive regions to be electrically connected to the multiple conductive regions, and the multiple semiconductor chips are also electrically connected to other conductive regions via micron-sized bonding wires to form a corresponding circuit topology (see the description below for details). The first metal layer 1-3 can be used as a thermally conductive layer. After the power semiconductor module packaging structure is packaged, the first metal layer 1-3 is in contact with the heat dissipation structure 2. The heat from the multiple semiconductor chips and the second metal layer 1-2 can be transferred through the insulating layer 1-1 to the first metal layer 1-3 and the heat dissipation structure 2 and then dissipated.

[0045] See Figure 2 In one embodiment, substrate 1 can be a copper-clad ceramic substrate (or DBC substrate), which comprises three layers: an upper copper layer, a middle ceramic layer, and a lower copper layer. The upper copper layer serves as the second metal layer 1-2 and is divided into multiple sub-regions to serve as multiple conductive regions. These conductive regions are designed with minimal electrical clearance, and the main circuit commutation path of the three-phase circuit is identical, thereby achieving the same parasitic inductance for each phase and ensuring consistency in switching speed and output current for each phase. Furthermore, the corners of the multiple conductive regions are arc-shaped to reduce stress concentration during soldering. In addition, multiple vias (e.g., dimple holes, not shown) are formed on some conductive regions of the second metal layer 1-2 and on the lower copper layer serving as the first metal layer 1-3, further reducing stress concentration. Additionally, in some embodiments, solder resist (not shown) is provided on the multiple conductive regions. The solder resist prevents solder overflow during soldering of semiconductor chips, resistors, etc., and the multiple conductive regions, and also prevents electrical short circuits during use.

[0046] In some embodiments, the thickness design of the upper copper layer, the middle ceramic layer, and the lower copper layer can be optimally selected based on constraints such as cost, application conditions, and mature processing thickness, using finite element simulation technology.

[0047] In some embodiments, depending on actual machinability and insulation withstand voltage requirements, multiple conductive areas and the lower copper layer are all at a certain distance from the edge of the central ceramic; and a certain gap is also maintained between the multiple conductive areas.

[0048] In some embodiments, the central ceramic layer serves as the insulating layer 1-1. The materials of the central ceramic layer include, but are not limited to, alumina, aluminum nitride, alumina doped with zirconium oxide, and silicon nitride. Among these, aluminum nitride is preferred as the material for the central ceramic layer because it has the highest thermal conductivity, thereby improving the heat dissipation performance of the packaging structure.

[0049] Further, see Figure 3The insulating layer 1-1 includes a first side L1, a second side L2, and a third side L3; and a first transition edge S1 connecting the first side L1 and the second side L2, a second transition edge S2 connecting the second side L2 and the third side L3, and a third transition edge S3 connecting the first side L1 and the third side L3. The included angle between any two of the first side L1, the second side L2, and the third side L3 is 60°, and the extensions of the first side L1, the second side L2, and the third side L3 intersect each other to form an equilateral triangle.

[0050] Wherein, the first transition edge S1, the second transition edge S2, and the third transition edge S3 can be arc-shaped edges; or, the first transition edge S1, the second transition edge S2, and the third transition edge S3 can be formed by splicing together multiple straight line segments (e.g., Figure 3 As shown, the insulating layer 1-1 is arranged in a pear-shaped structure. Compared to the existing rectangular structure, this structure reduces the volume of the power semiconductor module package. Furthermore, connectors can be placed on the outer sides of the first side L1, the second side L2, and the third side L3, improving module space utilization. Additionally, the first transition edge S1, the second transition edge S2, and the third transition edge S3 are formed by splicing multiple straight segments, which reduces manufacturing complexity.

[0051] In addition, it is understandable that the outer contours of the first metal layer 1-3 and the second metal layer 1-2 are basically consistent with the shape of the insulating layer 1-1.

[0052] In one embodiment, see Figure 1 The substrate 1 has a mounting hole H located at the center of the substrate 1, through which at least a portion of the heat dissipation structure 2 is exposed. The mounting hole H can be circular, polygonal, or other shapes, and is not limited thereto. The mounting hole H is used for mounting and fixing the substrate 1 to the heat dissipation structure 2.

[0053] See Figure 1 , Figure 4 and Figure 5 In this embodiment, the heat dissipation structure 2 is located at least on the side of the first metal layer 1-3 opposite to the insulating layer 1-1. The heat dissipation structure 2 can be integrally formed with the first metal layer 1-3; alternatively, the heat dissipation structure 2 can be connected to the first metal layer 1-3 through welding, bonding with thermally conductive materials, magnetic connection, snap-fit ​​connection, or other methods. By further forming the heat dissipation structure 2 on the first metal layer 1-3, the heat dissipation capability of the power semiconductor module packaging structure can be improved.

[0054] In some embodiments, the heat dissipation structure 2 may include metallic materials, phase change materials, etc.

[0055] See Figure 4 or Figure 5 The heat dissipation structure 2 includes a plurality of heat dissipation fins 2-1, which are located on the side of the substrate 1 away from the three-phase circuit, and at least one end of the plurality of heat dissipation fins 2-1 extends to the edge direction of the substrate 1.

[0056] Specifically, by setting heat dissipation fins 2-1 in contact with the first metal layer 1-3 on the side of the substrate 1 away from the three-phase circuit, the heat dissipation fins 2-1 can simultaneously achieve both longitudinal and lateral heat dissipation paths. Longitudinal heat dissipation involves rapidly conducting heat to the bottom of the substrate 1 through the first metal layer 1-3 and the heat dissipation fins 2-1 before dissipation, while lateral heat dissipation utilizes the ends of the heat dissipation fins 2-1 for heat dissipation, maximizing heat dissipation and significantly improving heat dissipation efficiency. This eliminates the need for additional liquid cooling, air cooling, or other heat dissipation devices, and the design of the heat dissipation fins 2-1 also increases the structural stability of the substrate 1.

[0057] The diverse design of the heat dissipation fins 2-1 can also adapt to the needs of different power levels. For example, by increasing the number of heat dissipation fins 2-1, adjusting the spacing between heat dissipation fins 2-1, or adjusting the arrangement of heat dissipation fins 2-1, different heat dissipation requirements can be met.

[0058] For example, see Figure 4 Multiple heat dissipation fins 2-1 can be set in parallel and spaced apart, and both ends of each heat dissipation fin 2-1 extend toward the edge of the substrate 1.

[0059] Specifically, the parallel spacing of the heat dissipation fins 2-1 can significantly increase the heat dissipation surface area and improve heat dissipation efficiency. Furthermore, the structural design of the heat dissipation fins 2-1 extending towards the edge of the substrate 1 at both ends provides multiple heat dissipation paths, allowing for more efficient heat exchange with the outside environment.

[0060] For example, see Figure 5 Multiple heat dissipation fins 2-1 can be configured such that their first ends are connected and have an included angle, and the second ends of the multiple heat dissipation fins 2-1 extend toward the edge of the substrate 1.

[0061] The included angle between two adjacent heat dissipation fins 2-1 can be designed based on the number of heat dissipation fins 2-1, module power, etc.

[0062] Specifically, by setting the first ends of multiple heat dissipation fins 2-1 to be connected, and the second ends of multiple heat dissipation fins 2-1 to extend toward the edge of the substrate 1, the heat on different heat dissipation fins 2-1 can be conducted to each other and dissipated through multiple heat dissipation paths. This design has a better heat dissipation effect for power semiconductor module packaging structures with uneven heat generation.

[0063] See Figure 1In this embodiment of the application, the heat dissipation structure 2 further includes a base plate 2-2 and an annular portion 2-3. The substrate 1 and a plurality of heat dissipation fins 2-1 are located on opposite sides of the base plate 2-2, and the annular portion 2-3 extends from the edge of the base plate 2-2 toward one side of the substrate 1.

[0064] The base plate 2-2 and multiple heat dissipation fins 2-1 can be integrally molded; or, the multiple heat dissipation fins 2-1 can be set on the side of the base plate 2-2 away from the substrate 1 by means of snap-fit, welding, bonding, etc.

[0065] The base plate 2-2 and the annular portion 2-3 form a receiving cavity, and the substrate 1 is located in the receiving cavity and disposed on the base plate 2-2. At least a portion of the base plate 2-2 is exposed through the mounting hole H.

[0066] Specifically, by setting the base plate 2-2 and the annular part 2-3, the base plate 2-2 and the annular part 2-3 can increase the heat dissipation path and heat dissipation area of ​​the three-phase circuit, thereby improving the heat exchange efficiency between the three-phase circuit and the outside world.

[0067] In this embodiment of the application, a three-phase circuit is formed on the second metal layer 1-2, wherein the three-phase circuit includes a first phase bridge, a second phase bridge and a third phase bridge; and the included angle between each pair of the first phase bridge, the second phase bridge and the third phase bridge is 120°.

[0068] Specifically, each phase bridge is obtained by a 120° replication rotation, so the parasitic parameters of the power circuit of each phase bridge are basically the same, thus achieving consistent three-phase current sharing. Furthermore, the first, second, and third phase bridges are arranged in an isosceles triangle with an angle of 120° between each pair, making the layout of the three phase bridges more compact, reducing the footprint, and improving the power density of the system.

[0069] In addition, by providing a three-phase circuit and a heat dissipation structure 2 on opposite sides of the substrate 1, the heat generated by the three-phase circuit on the second metal layer 1-2 can be transferred to the first metal layer 1-3 and the heat dissipation structure 2 through the insulating layer 1-1, and then heat exchange with the outside through the first metal layer 1-3 and the heat dissipation structure 2, ensuring the safe operation of the module.

[0070] See Figures 6-12 , Figure 6 A top view of a portion of the structure of a substrate provided in an embodiment of this application; Figure 7 A top view of a portion of the structure of a substrate provided in another embodiment of this application;

[0071] Figure 8 A top view of a portion of the structure of a substrate provided in yet another embodiment of this application; Figure 9 A top view of a portion of the structure of a substrate provided in another embodiment of this application; Figure 10A top view of a power semiconductor module package structure provided in an embodiment of this application; Figure 11 A perspective view of a power semiconductor module package structure provided in another embodiment of this application; Figure 12 The circuit topology diagram of a power semiconductor module package structure provided in an embodiment of this application is shown.

[0072] In this embodiment, the first phase bridge, the second phase bridge, and the third phase bridge all include multiple conductive regions on the second metal layer 1-2. These multiple conductive regions include a positive conductive region, a negative conductive region, an intermediate conductive region, an upper gate drive conductive region, a lower gate drive conductive region, and an AC conductive region.

[0073] Among them, see Figure 6 The positive conductive regions in the first phase bridge, the second phase bridge, and the third phase bridge are shared and represented by D; the negative conductive regions in the first phase bridge, the second phase bridge, and the third phase bridge are shared and represented by E.

[0074] In this embodiment, the negative conductive region is located at the center of the insulating layer 1-1 and is triangular in shape, the positive conductive region is located at the edge of the insulating layer 1-1 and is annular in shape, and the other conductive regions of the first phase bridge, the second phase bridge and the third phase bridge are located between the positive conductive region and the negative conductive region.

[0075] Of course, in other embodiments, the positive conductive regions in the first phase bridge, the second phase bridge, and the third phase bridge can be set separately; the negative conductive regions in the first phase bridge, the second phase bridge, and the third phase bridge can be set separately, and no limitation is made here.

[0076] In the attached diagram, the upper gate drive conductive region of the first phase bridge is represented by A1; the upper gate drive conductive region of the second phase bridge is represented by B1; and the upper gate drive conductive region of the third phase bridge is represented by C1.

[0077] In the attached diagram, the intermediate conductive region of the first phase bridge is represented by A2; the intermediate conductive region of the second phase bridge is represented by B2; and the intermediate conductive region of the third phase bridge is represented by C2.

[0078] In the attached diagram, the lower gate drive conductive region in the first phase bridge is represented by A3; the lower gate drive conductive region in the second phase bridge is represented by B3; and the lower gate drive conductive region in the third phase bridge is represented by C3.

[0079] In the attached diagram, the AC conduction area in the first phase bridge is represented by A6; the AC conduction area in the second phase bridge is represented by B6; and the AC conduction area in the third phase bridge is represented by C6.

[0080] Please continue reading Figure 6 In this embodiment of the application, the multiple conductive regions in the first phase bridge, the second phase bridge and the third phase bridge also include an inlet current detection conductive region connected to the intermediate electrode conductive region and an outlet current detection conductive region connected to the AC conductive region.

[0081] In the attached diagram, the current detection conductive area at the input end of the first phase bridge is represented by A4; the current detection conductive area at the input end of the second phase bridge is represented by B4; and the current detection conductive area at the input end of the third phase bridge is represented by C4. The current detection conductive area at the output end of the first phase bridge is represented by A5; the current detection conductive area at the output end of the second phase bridge is represented by B5; and the current detection conductive area at the output end of the third phase bridge is represented by C5.

[0082] Further, see Figure 7 The first, second, and third phase bridges all include current sampling resistors. In the attached diagram, the current sampling resistor in the first phase bridge is represented by AR; the current sampling resistor in the second phase bridge by BR; and the current sampling resistor in the third phase bridge by CR. One end of the current sampling resistor in each phase bridge is connected to the intermediate conductive region, and the other end is connected to the AC conductive region. Furthermore, the power source of the upper-phase transistor in each phase bridge is first connected to the intermediate conductive region via bonding wires (A-HQ2, B-HQ2, C-HQ2), and then connected to the AC conductive region through the intermediate conductive region and the current sampling resistor; the drain of the lower-phase transistor in each phase bridge is connected to the AC conductive region through the current sampling resistor.

[0083] Specifically, by directly integrating the current sampling resistor between the conductive areas, the current changes of the corresponding phase bridge can be monitored accurately in real time. The direct connection between the conductive areas and the current sampling resistor shortens the current path. Moreover, compared to the traditional method of soldering the current sampling resistor onto the PCB (printed circuit board), this embodiment solders the current sampling resistor onto the second metal layer 1-2, which helps with heat dissipation and improves the reliability of the current sampling resistor.

[0084] Please continue reading Figure 7 The first, second, and third phase bridges each include upper-level and lower-level transistor chips. In the attached diagram, the upper-level transistor chip of the first phase bridge is represented by A-HQ, and the lower-level transistor chip of the first phase bridge is represented by A-LQ; the upper-level transistor chip of the second phase bridge is represented by B-HQ, and the lower-level transistor chip of the second phase bridge is represented by B-LQ; the upper-level transistor chip of the third phase bridge is represented by C-HQ, and the lower-level transistor chip of the third phase bridge is represented by C-LQ.

[0085] Both the upper-side chip and the lower-side chip are formed by connecting multiple semiconductor chips in parallel.

[0086] In this embodiment, the semiconductor chip is a power semiconductor chip, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chip, an IGBT (Insulated Gate Bipolar Transistor) chip, or an SBD (Schottky Barrier Diode) chip, and the material of the semiconductor chip includes silicon carbide. Specifically, compared with silicon-based chips, silicon carbide-based chips have lower power loss, faster switching speed, and higher operating temperature, thereby improving chip performance.

[0087] Specifically, both the upper and lower power transistors are integrated using multiple semiconductor chips connected in parallel. This design improves the overall current-carrying capacity of the power semiconductor module package structure, meeting the needs of high-current applications. Furthermore, the distributed layout of the parallel chips reduces the current density of a single chip, improving heat dissipation performance. Simultaneously, the multi-path heat dissipation design of heat dissipation structure 2 enhances thermal management efficiency.

[0088] Combination Figures 6 to 9 In each phase bridge, the upper transistor chip is located in the positive conductive region so that the drain of the upper transistor chip is connected to the positive conductive region. The gate of the upper transistor chip in each phase bridge is connected to the gate drive conductive region via bonding wires (A-HQ1, B-HQ1, C-HQ1). The power source of the upper transistor chip in each phase bridge is also connected to the AC conductive region. The power source of the upper transistor chip in each phase bridge can be directly connected to the AC conductive region via bonding wires. In this embodiment, the power source of the upper transistor chip in each phase bridge is connected to the AC conductive region via an intermediate conductive region, an inlet current detection conductive region, a current sampling resistor, and an outlet current detection conductive region. The lower transistor chip in each phase bridge is located in the intermediate conductive region. The domain connects the drain of the lower transistor chip to the intermediate conductive region, and the drain of the lower transistor chip in each phase bridge is also connected to the AC conductive region. The drain of the lower transistor chip in each phase bridge can be directly connected to the AC conductive region via bonding wires. In this embodiment, the power source of the lower transistor chip in each phase bridge is connected to the AC conductive region via the intermediate conductive region, the inlet current detection conductive region, the current sampling resistor, and the outlet current detection conductive region. The gate of the lower transistor chip in each phase bridge is connected to the lower transistor gate drive conductive region via bonding wires (A-LQ1, B-LQ1, C-LQ1), and the power source of the lower transistor chip is connected to the negative conductive region via bonding wires (A-LQ2, B-LQ2, C-LQ2).

[0089] Since the driving circuit operates at low voltage and low current, the diameter of the driving bonding wire is 5 mil or 8 mil. However, since the power circuit operates at high voltage and high current, the diameter of the power bonding wire is 12 mil or 15 mil, and each semiconductor chip uses multiple power bonding wires connected in parallel.

[0090] Specifically, in this embodiment, the first phase bridge, the second phase bridge, and the third phase bridge are configured with the same structure and layout. Therefore, the parasitic parameters of the main power circuit from the positive input to the negative output of each phase bridge are exactly the same, thereby achieving consistent three-phase current sharing.

[0091] Further, see Figure 10 and Figure 11 The three-phase circuit also has multiple connection terminals. In the attached diagram, DCP represents the positive connection terminal; DCN represents the negative connection terminal; A-P1 represent the gate connection terminals of the upper transistor chip of the first phase bridge; B-P1 represent the gate connection terminals of the upper transistor chip of the second phase bridge; C-P1 represents the gate connection terminals of the upper transistor chip of the third phase bridge; A-P2 represent the middle terminal of the first phase bridge (also called the drain connection terminal of the lower transistor chip of the first phase bridge or the power source connection terminal of the upper transistor chip of the first phase bridge); B-P2 represent the middle terminal of the second phase bridge (also called the drain connection terminal of the lower transistor chip of the second phase bridge or the power source connection terminal of the upper transistor chip of the second phase bridge). The three phase bridge terminals are: C-P2 (also known as the drain terminal of the lower transistor chip of the third phase bridge or the power source terminal of the upper transistor chip of the third phase bridge); A-P3 (the gate terminal of the lower transistor chip of the first phase bridge), B-P3 (the gate terminal of the lower transistor chip of the second phase bridge), and C-P3 (the gate terminal of the lower transistor chip of the third phase bridge); A-P4 (the AC output terminal of the first phase bridge), B-P4 (the AC output terminal of the second phase bridge), and C-P4 (the AC output terminal of the third phase bridge); AR-P1 and AR-N1 (the measurement terminals of the current sampling resistor AR of the first phase bridge), BR-P1 and BR-N1 (the measurement terminals of the current sampling resistor BR of the second phase bridge), and CR-P1 and CR-N1 (the measurement terminals of the current sampling resistor CR of the third phase bridge).

[0092] The lengths of the aforementioned connection terminals can be determined based on a combination of the external driver board and power board. The terminals are made of conductive metal, such as copper. To prevent corrosion and oxidation in harsh environments, the surfaces of the connection terminals are plated with nickel or gold. The connection terminals are ultrasonically welded to the conductive areas, reducing the need for welding positioning fixtures and saving manufacturing costs.

[0093] Combination Figures 6 to 12 For ease of description, the circuit topology of the first phase bridge will be used as an example:

[0094] The drain of the upper-side transistor (A-HQ) of the first phase bridge is soldered to the positive conductive region (D), and then connected to the external circuit through the positive connection terminal (DCP). The gate of the upper-side transistor (A-HQ) of the first phase bridge is connected to the gate drive conductive region (A1) through a bonding wire (A-HQ1), and then connected to the external circuit through the gate connection terminal (A-P1). The power source of the upper-side transistor (A-HQ) of the first phase bridge is connected to the intermediate conductive region (A2) through a bonding wire (A-HQ2), and then connected to the AC conductive region (A6) through the current sampling resistor (AR), and finally connected to the external circuit through the AC output connection terminal (A-P4). Simultaneously, the measurement terminals (AR-P1, AR-N1) on the input current detection conductive region (A4) and the output current detection conductive region (A5) of the current sampling resistor (AR) are connected to the external circuit to measure the actual output current.

[0095] The drain of the lower transistor chip (A-LQ) of the first phase bridge is soldered to the intermediate conductive region (A2), and then connected to the external circuit through the intermediate terminal (A-P2). The gate of the lower transistor chip (A-LQ) of the first phase bridge is connected to the gate drive conductive region (A3) of the lower transistor through a bonding wire (A-LQ1), and then connected to the external circuit through the gate connection terminal (A-P3). The power source of the lower transistor chip (A-LQ) of the first phase bridge is connected to the negative conductive region (E) through a bonding wire (A-LQ2), and then connected to the external circuit through the negative connection terminal (DCN).

[0096] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power semiconductor module packaging structure, characterized in that, include: A substrate on which a three-phase circuit is disposed; wherein the three-phase circuit includes a first phase bridge, a second phase bridge and a third phase bridge; and the included angle between each pair of the first phase bridge, the second phase bridge and the third phase bridge is 120°. A heat dissipation structure is disposed on at least one side of the substrate for dissipating heat from the three-phase circuit.

2. The power semiconductor module packaging structure according to claim 1, characterized in that, The heat dissipation structure includes multiple heat dissipation fins, which are located on the side of the substrate away from the three-phase circuit, and at least one end of each heat dissipation fin extends toward the edge of the substrate.

3. The power semiconductor module packaging structure according to claim 2, characterized in that, The plurality of heat dissipation fins are arranged in parallel and spaced apart, and both ends of each heat dissipation fin extend toward the edge of the substrate.

4. The power semiconductor module packaging structure according to claim 2, characterized in that, The first ends of the plurality of heat dissipation fins are connected and have an included angle, and the second ends of the plurality of heat dissipation fins extend toward the edge of the substrate.

5. The power semiconductor module packaging structure according to any one of claims 2-4, characterized in that, The heat dissipation structure further includes a base plate and an annular portion, the substrate and the plurality of heat dissipation fins are located on opposite sides of the base plate, and the annular portion extends from the edge of the base plate toward one side of the substrate.

6. The power semiconductor module packaging structure according to claim 5, characterized in that, The substrate has mounting holes; a portion of the base plate is exposed through the mounting holes.

7. The power semiconductor module packaging structure according to claim 1, characterized in that, The first phase bridge, the second phase bridge, and the third phase bridge all include an upper-side chip and a lower-side chip; Both the upper-side chip and the lower-side chip are formed by connecting multiple semiconductor chips in parallel.

8. The power semiconductor module packaging structure according to claim 7, characterized in that, The first phase bridge, the second phase bridge, and the third phase bridge each include multiple conductive regions that are electrically insulated; the multiple conductive regions include a positive conductive region, a negative conductive region, an intermediate conductive region, an upper gate drive conductive region, a lower gate drive conductive region, and an AC conductive region; The upper transistor chip is disposed in the positive conductive region so that the drain of the upper transistor chip is connected to the positive conductive region, and the gate of the upper transistor chip is connected to the upper transistor gate drive conductive region through a bonding wire. The power source of the upper transistor chip is also connected to the AC conductive region. The lower transistor chip is disposed in the intermediate electrode conductive region so that the drain of the lower transistor chip is connected to the intermediate electrode conductive region, and the drain of the lower transistor chip is also connected to the AC conductive region. The gate of the lower transistor chip is connected to the lower transistor gate drive conductive region through a bonding wire, and the power source of the lower transistor chip is connected to the negative electrode conductive region through a bonding wire.

9. The power semiconductor module packaging structure according to claim 8, characterized in that, The plurality of conductive regions further include an inlet current detection conductive region connected to the intermediate electrode conductive region and an outlet current detection conductive region connected to the AC conductive region. The first phase bridge, the second phase bridge, and the third phase bridge all include a current sampling resistor. One end of the current sampling resistor is connected to the intermediate electrode conductive region, and the other end of the current sampling resistor is connected to the AC conductive region. The power source of the upper transistor chip and the drain of the lower transistor chip are both connected to the AC conductive region through the current sampling resistor.

10. The power semiconductor module packaging structure according to claim 9, characterized in that, The insulating layer in the substrate includes a first side, a second side, and a third side; as well as a first transition edge connecting the first side and the second side, a second transition edge connecting the second side and the third side, and a third transition edge connecting the first side and the third side; The included angle between each pair of the first side, the second side, and the third side is 60°, and the extensions of the first side, the second side, and the third side intersect each other to form an equilateral triangle.

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