A test structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-07-08
- Publication Date
- 2026-08-07
AI Technical Summary
[0004]目前，为了缩减应用器件工艺尺寸所引起的栅漏电流，常利用HKMG技术；但是，由于HKMG工艺复杂，极易造成金属栅极层下方的高K栅介质层发生部分缺失，进而造成金属栅极层与基底短接而引起的栅极漏电问题
[0035]如上所述，本实用新型提供了一种测试结构版图，其具体可阱图案、有源区图案、多个第一栅极图案、多个第一插塞图案、以及第一金属线图案；其中所述有源区图案包括沿第一方向延伸的第一有源区图案、以及沿所述第一方向延伸并沿第二方向位于所述第一有源区图案外侧的第二有源区图案，所述多个第一栅极图案沿所述第二方向横跨在所述第二有源区图案和所述阱图案上，所述多个第一插塞图案位于所述第一栅极图案上，并对位于所述阱图案，所述第一金属线图案沿所述第一方向横跨在所述多个第一插塞图案上。
Smart Images
Figure CN224611275U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to a test structure. Background Technology
[0002] SRAM (Static Random Access Memory) is a type of memory that does not require a refresh circuit, is fast, and is commonly used in the memory of various integrated circuits.
[0003] SRAM memory comprises multiple SRAM cells, each configured to store a bit of data. A typical SRAM cell has four transistors for storing that bit, configured as two cross-coupled inverters. The SRAM cell has two stable states that determine the logic "0" and "1" state of the bit. In addition to the four transistors for storing the bit, a typical SRAM cell includes two additional transistors (called transfer gate (PG) transistors, or access transistors) that control access to these four transistors during bit read or bit write operations.
[0004] Currently, HKMG technology is often used to reduce gate leakage current caused by the size of application devices. However, due to the complexity of the HKMG process, it is easy to cause partial loss of the high-k gate dielectric layer under the metal gate layer, which in turn causes gate leakage problem due to short circuit between the metal gate layer and the substrate. Utility Model Content
[0005] The purpose of this invention is to provide a test structure for testing whether the high-k gate dielectric layer of the N-type transistor in an SRAM device has filling damage and gate leakage, thereby enabling rapid online testing of SRAM devices and improving device stability.
[0006] Firstly, to solve the aforementioned technical problems, this utility model provides a test structure layout, which may include at least:
[0007] Trap pattern;
[0008] The active area pattern includes a first active area pattern extending along a first direction, and a second active area pattern extending along the first direction and disposed outside the first active area pattern along a second direction.
[0009] Multiple first gate patterns are traversed along the second direction across the second active region pattern and the well pattern;
[0010] Multiple first plug patterns are disposed on the first gate pattern and are located on the well pattern;
[0011] A first metal wire pattern extends across the plurality of first plug patterns along the first direction.
[0012] In one optional example, the test architecture layout may further include:
[0013] Multiple second plug patterns are arranged on the second active area pattern, spaced apart from each other;
[0014] At least one third plug pattern is disposed on the trap pattern;
[0015] The second metal wire pattern extends across the plurality of second plug patterns and the third plug pattern along the first direction.
[0016] In one optional example, the test architecture layout may further include:
[0017] Multiple second gate patterns are extended along the second direction across the first active region pattern and the second active region pattern on one side of the first active region pattern.
[0018] In one alternative example, the first gate pattern and the second gate pattern may not overlap.
[0019] In one alternative example, the well pattern includes a P-well pattern extending along the first direction, the projection of the P-well pattern onto the substrate overlapping the projection of the second active region pattern onto the well pattern.
[0020] In one alternative example, the gate layer corresponding to the first gate pattern may include a metal gate layer, the material of which may include aluminum.
[0021] In one alternative example, the width of the first active region pattern in the second direction may be greater than the width of the second active region pattern in the second direction.
[0022] Secondly, based on the same concept, this utility model also provides a test structure, which may include at least:
[0023] Base;
[0024] A first active region extends within the substrate along a first direction;
[0025] The second active region extends along the first direction and is located within the substrate outside the first active region along the second direction;
[0026] A plurality of transistors, including a first gate layer that is spaced apart from each other across the second active region along the second direction and extends to cover the substrate exposed on one side of the second active region;
[0027] A plurality of first plugs are respectively disposed on the portion of the first gate layer located on the exposed substrate; and
[0028] A first metal wire crosses the plurality of first plugs along the first direction and is electrically connected to the plurality of first plugs.
[0029] In some optional examples, the test structure may also include:
[0030] Multiple second plugs are disposed on the second active area;
[0031] At least one third plug is disposed on the substrate;
[0032] A second metal wire crosses the plurality of second plugs and the third plug along the first direction and is electrically connected to the second plugs and the third plug.
[0033] In some alternative examples, the transistor may include a pull-down transistor or access transistor of a SARM cell, and the first gate layer may include a metal gate layer.
[0034] Compared with the prior art, the present invention has at least the following technical effects:
[0035] As described above, this utility model provides a test structure layout, which specifically includes a well pattern, an active region pattern, a plurality of first gate patterns, a plurality of first plug patterns, and a first metal line pattern; wherein the active region pattern includes a first active region pattern extending along a first direction and a second active region pattern extending along the first direction and located outside the first active region pattern along a second direction; the plurality of first gate patterns span across the second active region pattern and the well pattern along the second direction; the plurality of first plug patterns are located on the first gate pattern and opposite to the well pattern; and the first metal line pattern spans across the plurality of first plug patterns along the first direction.
[0036] In this invention, the test structure may include multiple test units, and each test structure may include multiple transistors corresponding to the SRAM cell. The first gate layer of the pull-down transistors or access transistors (NMOS transistors in the multiple test units) in the multiple test units is connected to a first metal line through a first plug. An unexpected effect is that by forming a test structure containing multiple transistors corresponding to the SRAM cell structure on the dicing channel where the SRAM device chip is formed, it is possible to quickly detect whether the SRAM device has filling damage in the high-k gate dielectric layer and gate leakage problems on the line. Furthermore, by connecting the first gate layers of the pull-down transistors or access transistors in the multiple test units, connecting the source and drain of the pull-down transistors or access transistors in the multiple test units, and then applying a high voltage and a ground voltage to them respectively, the magnitude of the current between the first gate layer, the source and drain, and the substrate can be used to quickly detect whether the high-k gate dielectric layer of the SRAM device has filling damage and gate leakage problems, thereby improving the test efficiency and device stability of the SRAM device. Attached Figure Description
[0037] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the following detailed description to explain the present invention, but do not constitute a limitation thereof. In the drawings:
[0038] Figure 1 This is a current curve showing the gate leakage current of an SRAM device in the prior art.
[0039] Figure 2 This is a schematic diagram of a partial structure of the test structure layout provided in some embodiments of the present invention.
[0040] Figure 3 This is another schematic diagram of a partial structure of the test structure layout provided in some embodiments of the present invention.
[0041] Figure 4 The utilization provided in some embodiments of this utility model Figure 2 A partial cross-sectional view of the test structure formed by the test structure layout shown.
[0042] The attached figures are labeled as follows:
[0043] 100 - Substrate; 110 - Well pattern; PW-P well pattern, NW-N well pattern; 120 - Active region pattern; 121 - First active region pattern; 122 - Second active region pattern; 130 - Gate pattern; 131 - First gate pattern; 132 - Second gate pattern; 140 - Plug pattern; 141 - First Plug pattern; 142 - Second Plug pattern; 143 - Third Plug pattern; 150 - Metal line pattern; 151 - First metal line pattern; 152 - Second metal line pattern; D1 - First direction; D2 - Second direction; CT1 - First Plug; CT2 - Second Plug; CT3 - Third Plug; M1 - First metal line; M2 - Second metal line; MG - First gate layer.
[0044] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0045] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0046] It should be noted that the illustrations provided in this embodiment are merely schematic representations of the basic structure of this utility model. That is, the illustrations only show components relevant to this utility model and are not drawn according to the actual number, state, and size of components in implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. Therefore, the following description should be understood as being common knowledge to those skilled in the art and is not intended to limit this utility model.
[0047] In the description of this utility model, it should be noted that the terms "center", "middle", "outer periphery", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device, graphic, material layer or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0048] For ease of understanding, the following text defines horizontal and vertical directions, where the horizontal direction is parallel to the surface of the substrate 100; and the vertical direction is perpendicular to the surface of the substrate 100. Figures 2-4The first direction and the second direction are defined, wherein the first direction and the second direction are located in the same plane and correspond to the horizontal direction, and the second direction corresponds to the vertical direction.
[0049] Typically, a Static Random Access Memory (SRAM) cell (hereinafter referred to as an SRAM cell in an SRAM device) includes multiple transistors, such as 6T, 8T, or 10T, where T represents a transistor, such as a pull-up (PU) transistor, a pull-down (PD) transistor, and a transmission gate (PG) transistor (also called an access transistor). Specifically, in an SRAM cell, the pull-up transistor is a P-type transistor, and the pull-down transistor and access transistor are N-type transistors. It should be understood that the type of transistor of the same type may differ in different regions of the SRAM device; for example, the access transistor may be an N-type transistor within the SRAM cell, but a P-type transistor in a peripheral area, such as a read circuit port.
[0050] As is known from the background art, the gate in SRAM devices is often a metal gate, and the high-k gate dielectric layer located below the metal gate is very prone to filling damage and gate leakage. Currently, existing technologies cannot fully monitor whether the high-k gate dielectric layer below the metal gate has been damaged by simply detecting gate leakage in SRAM devices online. Figure 1 This is a current curve showing the gate leakage current of an SRAM device in the prior art, based on... Figure 1 As shown, when the transistor type in the SRAM cell of the SRAM device is an N-type transistor, such as a pull-down transistor or an access transistor, gate leakage occurs ( Figure 1 GLeakage is used in the middle, and its corresponding metal gate layer ( Figure 1 The current (indicated by G) can reach the microampere level, while under proper conditions it is only in the picoampere level.
[0051] To address this issue, this invention proposes a novel test structure. By forming a test structure containing multiple transistors corresponding to the SRAM cell structure on the dicing path where the SRAM device chip is formed, it enables rapid online detection of whether the SRAM device has filling damage in the high-k gate dielectric layer or gate leakage. Furthermore, by connecting the first gate layers of the pull-down transistors or access transistors in the multiple test cells, and connecting the source and drain terminals of the pull-down transistors or access transistors in the multiple test cells, and then applying a high voltage and a ground voltage to them respectively, the present invention can quickly detect whether the high-k gate dielectric layer of the SRAM device has filling damage or gate leakage by receiving the current between the first gate layer, the source and drain terminals, and the substrate. This improves the testing efficiency and device stability of the SRAM device.
[0052] The following section will use a 6T SRAM cell as an example to illustrate the test structure. For ease of observation, different pattern layers within the test structure layout provided by this invention will be used as examples in different accompanying drawings. It should be understood that, for the sake of simplicity, the embodiments of this invention... Figure 2 and Figure 3 Only a portion of the test layout is shown.
[0053] Please see Figure 2 and Figure 3 ,in, Figure 2 This is a schematic diagram of a partial structure of a test structure layout with a first metal wire pattern and a second metal wire pattern provided in some embodiments of the present invention. Figure 3 This is a schematic diagram of a partial structure of a test structure layout without the first metal wire pattern and the second metal wire pattern provided in some embodiments of the present invention.
[0054] like Figure 2 and Figure 3 As shown, the test structure layout provided by this utility model may specifically include:
[0055] Trap pattern 110;
[0056] The active area pattern 120 includes a first active area pattern 121 extending along a first direction D1, and a second active area pattern 122 extending along the first direction D1 and disposed outside the first active area pattern 121 along a second direction D2.
[0057] Multiple first gate patterns 131 are transversely spanning the second active region pattern 122 and the well pattern 110 along the second direction D2;
[0058] Multiple first plug patterns 141 are disposed on the first gate pattern 131 and are located on the well pattern 110;
[0059] The first metal wire pattern 151 extends across the plurality of first plug patterns 141 along the first direction D1.
[0060] Specifically, the well pattern 110 can be formed within a substrate 100. The well pattern 110 can be a P-well pattern PW and / or an N-well pattern NW, and multiple well patterns 110 can be formed within the substrate 100. For example, a P-well pattern PW can be formed within the substrate 100 first, and then an N-well pattern NW can be formed within the P-well pattern PW. The area of the substrate 100 corresponding to the P-well pattern PW can be used to form N-type transistors for SRAM cells, such as pull-down transistors and / or access transistors. The area of the substrate 100 corresponding to the N-well pattern NW can be used to form P-type transistors for SRAM cells, such as pull-up transistors. In one embodiment, the substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto.
[0061] The active region pattern 120 can be specifically formed within the well pattern 110. More specifically, the active region pattern can include a first active region pattern 121 and a second active region pattern 122. Since a 6T SRAM cell specifically includes four N-type transistors and two P-type transistors, and two of the N-type transistors, such as access transistors, are located on either side of the remaining transistors, the active region pattern in this embodiment can include a first active region pattern 121 and two second active region patterns 122. The first active region pattern 121 extends along the first direction D1, and the second active region pattern 122 extends along the first direction D1 and is disposed outside the first active region pattern 121 along the second direction D2, but is not limited thereto. The first active region pattern 121 is aligned with the N-well pattern NW region within the substrate 100 to form the P-type transistor in the SRAM cell, and the second active region pattern 122 is aligned with the P-well pattern PW region within the substrate 100 to form the N-type transistor in the SRAM cell. In one embodiment, the width of the first active region pattern 121 in the second direction D2 is greater than the width of the second active region pattern 122 in the second direction D2, but is not limited thereto.
[0062] Furthermore, the test structure layout may include multiple gate patterns 130, such as multiple first gate patterns 131 and multiple second gate patterns 13, wherein the gate patterns 130 are located on the active region pattern 120; wherein, the first gate pattern 131 may span across the second active region pattern 122 and the P-well pattern PW along the second direction D2, and the second gate pattern 132 may span across the first active region pattern 121 and the second active region pattern 122 on one side of the first active region pattern 121 along the second direction D2. In one embodiment, a first gate pattern 131 and a second gate pattern 132 may be collinear but not overlap along the second direction D2, and the width of the first gate pattern 131 in the first direction D1 may be the same as the width of the second gate pattern 132 in the first direction D1, but its length in the second direction D2 is less than the length of the second gate pattern 132 in the second direction D2, but is not limited thereto.
[0063] It should be understood that in the test structure formed by the first gate pattern 131 and the second gate pattern 132 in the embodiments of the present invention, the gate layer of the corresponding transistor is specifically a metal gate layer. The material of the metal gate layer may be, for example, aluminum, while the gate dielectric layer below the gate layer is a high-K gate dielectric layer, such as hafnium oxide (HfO2) and titanium oxide (TiO2), but is not limited thereto.
[0064] Furthermore, the test structure layout may also include multiple plug patterns 140, such as multiple first plug patterns 141, multiple second plug patterns 142, and at least one third plug pattern 143, wherein the plug patterns 140 are located on the gate pattern 130; wherein the multiple first plug patterns 141 may be respectively disposed on the first gate pattern 131, and are located on the P-well pattern PW, that is, the first plug pattern 141 may be located on the P-well where the first gate pattern 131 extends outside the second active region pattern 122. On a portion of the pattern PW, the metal gate layers of the N-type transistors in a plurality of test structures arranged along the first direction D1 are electrically led out respectively; a plurality of second plug patterns 142 may be disposed on the second active region pattern 122 in a mutually spaced manner to electrically lead out the source and drain electrodes in the P-well patterns PW formed on both sides of the first gate pattern 131; at least one of the third plug patterns 143 may be disposed on the P-well pattern PW exposed on one side of the second active region pattern 122 to electrically lead out the substrate 100 corresponding to the P-well pattern PW.
[0065] Furthermore, such as Figure 3As shown, the test structure layout may further include at least a plurality of first metal wire patterns 151 and a plurality of second metal wire patterns 152; wherein the first metal wire pattern 151 may span across the plurality of first plug patterns 141 along the first direction D1, so as to short-circuit all the first plugs corresponding to the first plug pattern 141 that electrically leads out of the metal gate layer of the N-type transistor in the plurality of test units, for use as an external voltage source such as VDD; the second metal wire pattern 152 spans across the plurality of second plug patterns 142 and the third plug pattern 143 along the first direction D1, so as to short-circuit all the second plugs corresponding to the second plug pattern 142 and the third plug pattern 143 that electrically leads out of the source and drain of the N-type transistor in the plurality of test units and the second plug pattern 142 of the substrate 100, and all the third plugs corresponding to the third plug pattern 143, for use as an external voltage source such as GND (ground voltage source), but is not limited thereto.
[0066] Please refer to Figure 4 , Figure 4 The utilization provided in some embodiments of this utility model Figure 2 A partial cross-sectional view of the test structure formed by the test structure layout shown. (See attached image.) Figure 4 As shown, the test structure that can be formed using the test structure layout provided in this embodiment of the present invention may include at least: a substrate 100, a first active region, a second active region, a plurality of transistors, a plurality of first plugs CT1, a first metal line M1, a plurality of second plugs CT2, at least one third plug CT3, and a second metal line M2.
[0067] In one embodiment, the first active region may extend within the substrate 100 along a first direction D1; the second active region may extend along the first direction D1 and be located within the substrate 100 outside the first active region along a second direction D2; each of the plurality of transistors (pull-down transistors or access transistors of the SARM unit) may include a first gate layer MG, the first gate layer MG being mutually spaced across the second active region along the second direction D2, and extending to cover the substrate exposed on one side of the second active region; the plurality of first plugs may be respectively provided The first gate layer is located on the exposed portion of the substrate 100; the first metal line M1 may cross the plurality of first plugs CT1 along the first direction D1 and is electrically connected to the plurality of first plugs CT1; the plurality of second plugs CT2 may be disposed on the second active region; the third plug CT3 may be disposed on the substrate 100; the second metal line M2 may cross the plurality of second plugs CT2 and the third plug CT3 along the first direction D1 and is electrically connected to the second plugs CT2 and the third plug CT3.
[0068] Under this setting, such as Figure 4 As shown, by applying a voltage to the first metal line M1 and the second metal line M2 of the test structure, the current between the metal gate layer (first gate layer MG) of multiple N-type transistors located in the second active region and their source / drain and the substrate 100 can be measured. If the current reaches the microampere level, it indicates that there must be filling damage in the high-k gate dielectric layer of the N-type transistor in the SRAM cell of the SRAM device tested by the test structure. If the current reaches the picoampere level, it indicates that the SRAM cells in the SRAM device tested by the test structure are all normal.
[0069] It should be understood that the test structure formed by the test structure layout provided in the embodiments of this utility model can be used for online testing of SRAM devices. Therefore, the test structure can be set on the dicing channel where SRAM device chips are formed, but is not limited thereto.
[0070] It should be noted that the methods, processes, and material descriptions involved in this utility model are all existing technologies used to explain the functionality of the structure or layout proposed in this embodiment.
[0071] In summary, this utility model provides a test structure layout, which specifically includes a substrate, an active region pattern, a plurality of first gate patterns, a plurality of first plug patterns, and a first metal line pattern; wherein the active region pattern includes a first active region pattern extending along a first direction and a second active region pattern extending along the first direction and located outside the first active region pattern along a second direction; the plurality of first gate patterns span across the second active region pattern and the substrate along the second direction; the plurality of first plug patterns are located on the first gate pattern and opposite to the substrate; and the first metal line pattern spans across the plurality of first plug patterns along the first direction.
[0072] In this invention, the test structure may include multiple test units, and each test structure may include multiple transistors corresponding to the SRAM cell. The first gate layer of the pull-down transistors or access transistors (NMOS transistors in the multiple test units) in the multiple test units is connected to a first metal line through a first plug. An unexpected effect is that by forming a test structure containing multiple transistors corresponding to the SRAM cell structure on the dicing channel where the SRAM device chip is formed, it is possible to quickly detect whether the SRAM device has filling damage in the high-k gate dielectric layer and gate leakage problems on the line. Furthermore, by connecting the first gate layers of the pull-down transistors or access transistors in the multiple test units, connecting the source and drain of the pull-down transistors or access transistors in the multiple test units, and then applying a high voltage and a ground voltage to them respectively, the magnitude of the current between the first gate layer, the source and drain, and the substrate can be used to quickly detect whether the high-k gate dielectric layer of the SRAM device has filling damage and gate leakage problems, thereby improving the test efficiency and device stability of the SRAM device.
[0073] It should be noted that the above description is only a preferred embodiment of the present utility model and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the utility model involved in the present utility model is not limited to the technical solutions formed by a specific combination of the above technical features. It should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the concept of the utility model. For example, technical solutions formed by replacing the above features with (but not limited to) similar technologies disclosed in this application.
[0074] Apart from the technical features described in the specification, the other technical features are known to those skilled in the art. To highlight the innovative features of this utility model, the other technical features will not be repeated here.
Claims
1. A test structure, characterized in that, include: Base; A first active region extends within the substrate along a first direction; The second active region extends along the first direction and is located within the substrate outside the first active region along the second direction; A plurality of transistors, including a first gate layer that is spaced apart from each other across the second active region along the second direction and extends to cover the substrate exposed on one side of the second active region; Multiple first plugs are respectively disposed on the portion of the first gate layer located on the exposed substrate; as well as A first metal wire crosses the plurality of first plugs along the first direction and is electrically connected to the plurality of first plugs.
2. The test structure as described in claim 1, characterized in that, Also includes: Multiple second plugs are disposed on the second active area; At least one third plug is disposed on the substrate; A second metal wire crosses the plurality of second plugs and the third plug along the first direction and is electrically connected to the second plugs and the third plug.
3. The test structure as described in claim 2, characterized in that, The transistor includes a pull-down transistor or access transistor of a SARM cell, and the first gate layer includes a metal gate layer.