A low inductance current sharing power device package structure

Abstract

The utility model provides a kind of low inductance current-sharing power device packaging structure;Including ceramic copper-clad plate, the upper layer of ceramic copper-clad plate is equipped with copper layer, copper layer is formed by etching two left and right opposite islands A and island B;Island A and island B are respectively fixed with upper bridge power device group and lower bridge power device group, the lower end surface of ceramic substrate is fixed on bottom plate through bottom copper-clad, by the structure design of innovation, effectively reduce the parasitic inductance generated in packaging process, improve the heat dissipation performance and electrical performance of device, enhance the stability and reliability of device working in high temperature, high frequency environment, to meet the demand of modern electronic equipment to high performance semiconductor device.

Description

Technical Field

[0001] This utility model relates to a packaging structure for a low-inductance current-sharing power device. Background Technology

[0002] Third-generation wide-bandgap semiconductor materials, including SiC and GaN, possess significant advantages such as high temperature, high frequency, high voltage, low loss, and low thermal resistance. These advantages make SiC devices have enormous application potential in power conversion, but to fully realize these properties, matching packaging technologies are required. The high switching speed of third-generation semiconductor devices can lead to wideband electromagnetic oscillations, while traditional packaging technologies introduce large parasitic inductances. This can cause voltage overshoot during switching, increase device losses, induce electromagnetic interference, reduce the device's safe operating area, and consequently affect the reliability and stability of the power module. Therefore, low-inductance packaging technologies are needed to reduce parasitic inductance to accommodate the high di / dt applications of SiC power devices. Summary of the Invention

[0003] To address the aforementioned technical problems, this utility model provides a low-inductance current-sharing power device packaging structure.

[0004] This utility model is achieved through the following technical solution.

[0005] This utility model provides a low-inductance current-sharing power device packaging structure, including a ceramic copper-clad laminate, with a copper layer on the upper layer of the ceramic copper-clad laminate. The copper layer is etched to form two islands A and B that are opposite to each other. An upper bridge power device group and a lower bridge power device group are respectively fixed on islands A and B. The lower end face of the ceramic substrate is fixed to the base plate by bottom copper cladding. The island A is also connected to one end of the output terminal, and a wiring board is installed on the output terminal. The wiring board is connected to the top of the upper cover through the lower bridge gate terminal. The wiring board is connected to the lower bridge power device group through aluminum wire. The other end of the output terminal is fixed to the top of the upper cover. The island B is equipped with a positive input terminal, and a negative input terminal and an upper bridge gate terminal are installed through a ceramic pad. The other ends of the positive input terminal, negative input terminal and upper bridge gate terminal are all fixed to the top of the upper cover. The upper bridge gate terminal is fixed to the ceramic pad through a wiring board, and the wiring board is connected to the upper bridge power device group through aluminum wire. The island A is connected to the upper bridge power device group via aluminum busbar B, and the lower bridge power device group is connected to the negative input terminal via aluminum busbar B.

[0006] Both the upper and lower bridge power device groups consist of multiple SiC or GaN power devices connected in parallel, and the parasitic parameters of each parallel branch are consistent. Multiple surface mount resistors are soldered onto the wiring board, and each power device is connected to a surface mount resistor.

[0007] The ceramic copper-clad laminate is encapsulated in a cavity formed by an upper cover and a bottom plate. The outer surface of the bottom plate is provided with a fin array. The cavity is filled with a thermally conductive silicone layer. The upper cover and the bottom plate are made of insulating high thermal conductivity material.

[0008] The output terminal is fixed to island A by ultrasonic welding.

[0009] The layout of the upper bridge power device group and the lower bridge power device group is a centrally symmetrical structure, and the connection path length between each device and the gate resistor is consistent.

[0010] The inner surface of the top cover is provided with a groove structure that matches the shape of the ceramic copper-clad plate, for fixing the ceramic copper-clad plate.

[0011] The beneficial effects of this utility model are: By employing island etching isolation, symmetrical parallel layout, thermally conductive-insulating packaging design, and ultrasonic welding process, the electrical performance, heat dissipation capacity, and reliability of the power module are comprehensively optimized, making it particularly suitable for high-frequency, high-power-density applications (such as new energy vehicle inverters and server power supplies). Attached Figure Description

[0012] Figure 1 This is a cross-sectional schematic diagram of the present invention; Figure 2 This is a schematic diagram of the power device arrangement of this utility model; Figure 3 This is a schematic diagram of the circuit principle of this utility model; In the diagram: 1-lower bridge gate terminal, 2-output terminal, 3-wiring board, 4-ceramic copper-clad board, 41-island A, 42-island B, 43-bottom copper plating, 5-upper bridge gate terminal, 6-negative input terminal, 7-positive input terminal, 8-top cover, 9-bottom plate, 10-lower bridge power device group, 11-lower bridge gate resistor, 12-aluminum busbar A, 13-aluminum busbar B, 14-upper bridge power device group, 15-upper bridge gate resistor, 16-aluminum wire. Detailed Implementation

[0013] Example 1: like Figure 1As shown, a low-inductance current-sharing power device packaging structure includes a ceramic copper-clad laminate 4. A copper layer is provided on the upper layer of the ceramic copper-clad laminate 4, and two opposing islands A41 and B42 are formed by etching. An upper bridge power device group 14 and a lower bridge power device group 10 are respectively fixed on islands A41 and B42. The lower end face of the ceramic substrate 4 is fixed to a base plate 9 via a bottom copper cladding 43. The etched islands A and B divide the circuit into upper and lower bridge arms, achieving electrical isolation between the high-voltage side and the low-voltage side, avoiding short-circuit risks. The ceramic copper-clad laminate has high thermal conductivity, and the combination of the bottom copper cladding 43 and the base plate 9 can quickly conduct the heat of the power devices to the base plate fin array, improving heat dissipation efficiency. Figure 1 The islanded layout shown reduces displacement caused by vibration or thermal expansion by mechanically fixing the power device group, ensuring long-term reliability.

[0014] The island A41 is also connected to one end of the output terminal 2, and a wiring board 3 is installed on the output terminal 2. The wiring board 3 is connected to the top of the upper cover 8 through the lower bridge gate terminal 1. The wiring board 3 is connected to the lower bridge power device group 10 through aluminum wire. The other end of the output terminal 2 is fixed to the top of the upper cover 8. like Figure 2 As shown, the wiring board 3 forms a low-impedance connection path with the aluminum wire, which reduces the transmission delay and parasitic inductance of the gate drive signal and improves the switching speed.

[0015] like Figure 1 As shown, the output terminal 2 is directly fixed to the top of the cover 8, which shortens the output circuit length, reduces loop inductance, and reduces switching losses and electromagnetic interference (EMI).

[0016] like Figure 1 As shown, a positive input terminal 7 is installed on island B42, and a negative input terminal 6 and an upper bridge gate terminal 5 are installed through a ceramic pad 6. The other ends of the positive input terminal 7, the negative input terminal 6, and the upper bridge gate terminal 5 are all fixed to the top of the upper cover 8. The upper bridge gate terminal 5 is fixed to the ceramic pad through a wiring board 3, and the wiring board 3 is connected to the upper bridge power device group 14 through aluminum wires. The positive and negative input terminals and the gate terminal are separated to avoid the intersection of the high current path and the signal path and reduce coupling interference.

[0017] The pad 6 provides insulation support to prevent breakdown between the high-voltage input terminal and the low-level gate signal.

[0018] like Figure 2As shown, island A41 is connected to the upper bridge power device group 14 via aluminum busbar B13, and the lower bridge power device group 10 is connected to the negative input terminal 6 via aluminum busbar A12. The wide cross-sectional area of ​​aluminum busbars B13 and A12 reduces the on-resistance, ensuring the current sharing characteristics of multiple parallel power devices (such as SiC MOSFETs) and avoiding single-transistor overload. The aluminum busbar layout, in conjunction with the symmetrical island structure, ensures that the parasitic inductance of each parallel branch is consistent, suppressing current oscillation.

[0019] like Figure 2 As shown, both the upper bridge power device group 14 and the lower bridge power device group 10 consist of multiple SiC or GaN power devices connected in parallel, and the parasitic parameters of each parallel branch are consistent. Multiple surface-mount resistors are soldered onto the wiring board 3, and each power device is connected to one of these surface-mount resistors. Figure 2 As shown, the high-frequency characteristics of SiC / GaN devices, combined with parallel design, increase the module switching frequency, making them suitable for high-frequency power supply applications. Figure 3 As shown, the surface mount resistors are connected to the power devices one by one to precisely control the gate drive waveform and suppress ringing.

[0020] like Figure 1 As shown, the ceramic copper-clad laminate 4 is encapsulated within a cavity formed by the upper cover 8 and the bottom plate 9. The outer surface of the bottom plate 9 is provided with a fin array. The cavity is filled with a thermally conductive silicone layer. The upper cover 8 and the bottom plate 9 are made of an insulating, highly thermally conductive material. The thermally conductive silicone fills the cavity gaps, eliminating air thermal resistance and ensuring efficient heat dissipation from the ceramic copper-clad laminate 4 → the bottom plate 9 → the fin array. The upper cover and bottom plate, made of insulating, highly thermally conductive materials (such as PPS or ceramic composite materials), are both insulating and thermally conductive, meeting the requirements for high-voltage isolation.

[0021] The output terminal 2 is fixed to island A41 by ultrasonic welding. Ultrasonic welding achieves a metallurgical bond between the copper layer and the terminal, resulting in low contact resistance and high temperature resistance, avoiding the problems of poor soldering or oxidation associated with traditional welding.

[0022] The upper bridge power device group 14 and the lower bridge power device group 10 are arranged in a centrally symmetrical structure, and the connection path length between each device and the gate resistor is consistent. The parasitic parameters of each branch between the parallel power devices are consistent. In addition, each power device is equipped with a gate resistor connected to the gate terminal, thereby ensuring the current sharing effect among the power devices.

[0023] The inner surface of the upper cover 8 is provided with a groove structure that matches the shape of the ceramic copper-clad laminate 4, for fixing the ceramic copper-clad laminate. Symmetrical layout and equal-length paths ( Figure 2 To ensure that the drive signals of the upper and lower bridge arm devices arrive synchronously, avoid switching timing deviations caused by path differences, and reduce dead time loss.

[0024] like Figure 3As shown, from the perspective of the current path, the positive input terminal DC+ and the upper bridge power devices T1-T4 are all placed on the ceramic copper-clad plate and electrically connected to the copper layer on their right side; the output terminal AC and the lower bridge power devices T5-T8 are both placed on the ceramic copper-clad plate and electrically connected to the copper layer on their left side; the upper bridge power devices T1-T4 are connected to the copper layer on the left side of the ceramic copper-clad plate through connecting aluminum busbar B; the lower bridge power devices T5-T8 are connected to the negative input terminal DC- through connecting aluminum busbar A. This structure realizes the connection of the entire power loop in the circuit, including DC+, T1-T4, AC, T5-T8, and DC-. Furthermore, since the current path from DC+ to AC is left-handed and from AC to DC- is right-handed, the current paths of the upper and lower bridges are short, opposite in direction, and close in position, resulting in a lower stray inductance for the entire loop. The positive input terminal DC+, output terminal AC, and negative input terminal DC- are all vertically elongated strips. Similarly, power devices T1-T4 and T5-T8 are also vertically and evenly distributed. This ensures that the parasitic parameters of each branch in the power circuit are identical, resulting in excellent current sharing among the different power devices. The lower-bridge gate terminal G2 is placed on the gate trace PCB. The control gates of the lower-bridge power devices T5-T8 are connected to the gate trace PCB via connecting aluminum wires. A lower-bridge gate resistor is placed on the gate trace PCB for each power device, further enhancing current sharing among the power devices. This stacked design also results in a compact structure with minimal internal space, thereby increasing power density.

Claims

1. A low-inductance current-sharing power device package structure, characterized in that: The ceramic copper-clad laminate (4) has a copper layer on its upper layer. The copper layer is etched to form two islands A (41) and B (42) that are opposite each other. An upper bridge power device group (14) and a lower bridge power device group (10) are fixed on island A (41) and island B (42) respectively. The lower end face of the ceramic substrate (4) is fixed to the base plate (9) by bottom copper cladding (43). The island A (41) is also connected to one end of the output terminal (2), and a wiring board (3) is installed on the output terminal (2). The wiring board (3) is connected to the top of the upper cover (8) through the lower bridge gate terminal (1). The wiring board (3) is connected to the lower bridge power device group (10) through aluminum wire. The other end of the output terminal (2) is fixed to the top of the upper cover (8). The island B (42) is equipped with a positive input terminal (7), and a negative input terminal (6) and an upper bridge gate terminal (5) are installed through a ceramic pad (6). The other ends of the positive input terminal (7), the negative input terminal (6), and the upper bridge gate terminal (5) are all fixed to the top of the cover (8). The upper bridge gate terminal (5) is fixed to the ceramic pad through a wiring board (3). The wiring board (3) is connected to the upper bridge power device group (14) through aluminum wire. The island A (41) is connected to the upper bridge power device group (14) via aluminum busbar B (13), and the lower bridge power device group (10) is connected to the negative input terminal (6) via aluminum busbar (12).

2. The low-inductance current-sharing power device packaging structure according to claim 1, characterized in that: The upper bridge power device group (14) and the lower bridge power device group (10) are both multiple SiC or GaN power devices connected in parallel, and the parasitic parameters of each parallel branch are consistent. Multiple surface mount resistors are soldered on the wiring board (3), and the power devices are connected to the surface mount resistors one by one.

3. The low-inductance current-sharing power device packaging structure according to claim 1, characterized in that: The ceramic copper-clad plate (4) is encapsulated in a cavity formed by the upper cover (8) and the bottom plate (9). The outer surface of the bottom plate (9) is provided with a fin array. The cavity is filled with a thermally conductive silicone layer. The upper cover (8) and the bottom plate (9) are made of insulating high thermal conductivity material.

4. The low-inductance current-sharing power device packaging structure according to claim 1, characterized in that: The output terminal (2) is fixed to island A (41) by ultrasonic welding.

5. The low-inductance current-sharing power device packaging structure according to claim 1, characterized in that: The upper bridge power device group (14) and the lower bridge power device group (10) are arranged in a centrally symmetrical structure, and the connection path length between each device and the gate resistor is consistent.

6. The low-inductance current-sharing power device packaging structure according to claim 1, characterized in that: The inner surface of the top cover (8) is provided with a groove structure that matches the shape of the ceramic copper-clad plate (4) for fixing the ceramic copper-clad plate (4) and preventing displacement.

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