Pin side immersion tin packaging structure

Abstract

The utility model relates to the structure that utilizes lead wire frame to carry out the packaging of chip, disclose a kind of packaging structure of pin side tin immersion, including mutually electrically connected lead wire frame and chip, the back cutting way area of the lead wire frame is preinstalled bare copper, the back of the lead wire frame has the nickel palladium gold layer that avoids the area where bare copper is located, part surface of the pin side has the tin layer that extends to the back.This structure, change the plating layer of the back of lead wire frame to nickel palladium gold layer, retain the plating layer of pin side to tin layer, can be obtained by chip first-level packaging before and after collaborative processing, solve the problem of high reliability requirement chip after secondary packaging high-low temperature cycle test failure.

Description

Technical Field

[0001] This utility model relates to a structure for packaging chips using a lead frame. Background Technology

[0002] The process of fixing the chip onto a packaging substrate or leadframe, interconnecting the chip's pads with the inner pins of the packaging substrate or leadframe to further connect with the outer pins, and then protectively encapsulating the chip and the interconnects is called primary packaging. Primary packaging results in a packaged electronic device. Mounting the primary package and other electronic components onto the surface of a printed circuit board is called secondary packaging.

[0003] US Patent 2016276251A1 discloses a method for manufacturing electronic packages. This method involves forming a mask on the back side of the leadframe (the side connected to the chip is typically called the front side, and the opposite side is typically called the back side) using methods such as ink printing. The exposed portions are then etched and electroplated to form a solderable metal layer on the sides of the leadframe pins, thereby establishing a more reliable connection between the package and the connected device (e.g., a printed circuit board). This durability is particularly important in certain applications, such as chips used in automobiles.

[0004] However, it has been found that if automotive chips use only a single layer of tin plating in the primary packaging, they are prone to failure during high and low temperature cycling tests after secondary packaging. This problem needs to be solved.

[0005] Analysis revealed that the problem stemmed from the fact that the leadframe protective layer used in the primary package is a tin layer, which has lower stability compared to another common type of protective layer in packages, such as a nickel-palladium-gold layer. A simple solution is to complete the primary package using the process described in US2016276251A1, where the metal protective layer plated on the sides and back of the leads is a nickel-palladium-gold layer. However, primary package manufacturers often use tin as their plating material and are unable to perform the plating of this special nickel-palladium-gold protective layer. Therefore, the aforementioned simple solution cannot be implemented.

[0006] Furthermore, the chemicals used in current gold plating processes are highly hazardous, and the location of nickel-palladium-gold plating workshops is restricted by safety and legal factors; that is, the construction of workshops with gold plating capabilities is prohibited in certain regions. Therefore, the protective layer gold plating process often has to be carried out at the lead frame manufacturing plant, where they complete the production of the protective layer before the product leaves the factory. Currently, forming an electroplated layer at a predetermined location on the back side during the lead frame fabrication process is a feasible existing technology. Utility Model Content

[0007] To improve the reliability of chips after secondary packaging, this invention proposes a packaging structure with pin-side tinning obtained by coordinating processing before and after primary packaging of the chip, which has better reliability.

[0008] The technical solution adopted by this utility model to solve its technical problem is: a package structure with pin side tinning, including a lead frame and a chip that are electrically connected to each other, bare copper is pre-placed in the back cut area of ​​the lead frame, the back of the lead frame has a nickel-palladium-gold layer that avoids the area where the bare copper is located, and a part of the surface of the pin side has a tin layer extending to the back.

[0009] The packaging structure of this utility model is implemented as follows: bare copper is pre-placed at the cutting channel position before the lead frame leaves the factory, and a nickel-palladium-gold layer that avoids the area where the bare copper is located is pre-plated on its back. After the typical packaging process of primary packaging (the typical process of plastic packaging is: chip mounting, wire bonding, injection molding, etc.), the above-mentioned side tin-dipped packaging structure is formed by masking, etching, and electroplating.

[0010] The area of ​​the pin side surface covered with the tin layer accounts for less than 90% of the total area of ​​the pin side surface.

[0011] The beneficial effects of this invention are: by changing the tin layer on the back of the lead frame to a nickel-palladium-gold layer, while retaining the tin layer on the side of the pins, the problem of high reliability chip failure during high and low temperature cycle testing after secondary packaging is solved. Attached Figure Description

[0012] Figure 1 It is a schematic diagram of multiple lead frames arranged regularly on a lead frame carrier.

[0013] Figure 2 This is a schematic diagram of a typical pin arrangement for a leadframe.

[0014] Figure 3 This is a schematic flowchart illustrating the implementation process of Embodiment 1 of the side-dip tin packaging structure of this utility model.

[0015] Figure 4 This is a cross-sectional schematic diagram of the packaging structure of Embodiment 1 of the side-immersion tin packaging structure of this utility model.

[0016] Figure 5 This is a plan view of the packaging structure of Embodiment 1 of the side-immersion tin packaging structure of this utility model.

[0017] Figure 6 This is a flowchart illustrating the implementation process of Embodiment 2 of the side-dip tin packaging structure of this utility model.

[0018] Figure 7 This is a cross-sectional view of the packaging structure of Embodiment 2 of the side-immersion tin packaging structure of this utility model.

[0019] Figure 8 This is a plan view of the packaging structure of Embodiment 2 of the side-immersion tin packaging structure of this utility model.

[0020] The diagram is labeled as follows: 100-lead frame carrier, 1-lead frame, 2-chip, 3-molded body, 10-pin area, 20-cut track area, 30-pad area, 101-nickel-palladium-gold layer, 102-tin layer, 103-bare copper surface, 104-protective film. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] like Figure 1 As shown, during production, multiple lead frames 1 are regularly arranged on a lead frame carrier 100. Cutting groove areas 20 are designed between the lead frames 1. After processing, the units are separated along the cutting grooves to form individual packaged chips. Figure 2 As shown, in a typical QFN package, the pins are distributed around the chip base island, which is used to mount the chip. The metal of some of the pins of adjacent chips is integrated before the first-level packaging. The middle of the metal is the dicing area, and a large area of ​​pads is designed on the back of the lead frame.

[0023] Example 1: like Figure 3 , Figure 4 and Figure 5 As shown, the side-dip tin-plated packaging structure of this utility model uses wire bonding to complete the primary packaging. Its complete process is as follows: Figure 3 As shown, the process includes "preparation-mounting-wire bonding-molding-film application-exposure and development-etching-electroplating-film removal-dicing". The back of the incoming lead frame 1 is pre-plated with a nickel-palladium-gold layer 101. The nickel-palladium-gold layer 101 avoids the bare copper in the dicing area. After molding, a film is applied to the back of the lead frame to protect the nickel-palladium-gold layer 101. Then, exposure and development are performed to expose the bare copper area to be processed. A pit is formed in the bare copper by etching. Then, a tin layer 102 is formed on the pit wall by electroplating. After that, the protective film is removed and the packaged chip units are diced and separated.

[0024] Depend on Figure 3 It can be seen that the width of the bare copper area depends on the size of the recess on the side of a single cell formed by the packaging cut. Without considering the cutting loss, the width of the bare copper area is roughly equivalent to twice the width of the recess on the side of a single cell.

[0025] The etching depth should not exceed the thickness of the bare copper in the pre-defined etch area, and generally should not exceed 90% of the lead copper layer thickness. The small amount of oxidation on the exposed copper surface after etching has virtually no impact on the package quality.

[0026] After the above processing, the following can be obtained: Figure 5 and Figure 6 The package structure shown is a side-tin-dip package. (Example) Figure 5 As shown, the package unit includes a lead frame 1 and a chip 2 that are electrically connected to each other. The back surface of the lead frame 1 has a cut-out area 20 with bare copper pre-formed on it. The back surface of the lead frame 1 has a nickel-palladium-gold layer 101 that avoids the area where the bare copper is located. A portion of the surface of the side of the pin 10 has a tin layer 102 that extends to the back surface.

[0027] Example 2: like Figure 6 , Figure 7 and Figure 8 As shown, the side-dip tin-plated packaging structure of this utility model uses a flip-chip method to complete the primary packaging. Its complete process is as follows: Figure 6 As shown, the process includes "preparation-flip chip-molding-film application-exposure and development-etching-electroplating-film removal-dicing". The back of the incoming lead frame 1 is pre-plated with a nickel-palladium-gold layer 101. The nickel-palladium-gold layer 101 avoids the bare copper in the dicing area. After molding, a film is applied to the back of the lead frame to protect the nickel-palladium-gold layer 101. Then, exposure and development are performed to expose the bare copper area to be processed. A pit is formed in the bare copper by etching. Then, a tin layer 102 is formed on the pit wall by electroplating. After that, the protective film is removed and the packaged chip units are diced and separated.

[0028] The etching depth should be carefully controlled and must not exceed the thickness of the bare copper pre-set in the etch zone area.

[0029] After the above processing, the following can be obtained: Figure 7 and Figure 8 The package structure shown is a side-tin-dip package.

[0030] The side-dip tin packaging structure of this utility model has a tin layer 102 in the pin side area, which retains the advantages of solderability and easy observation. The pad area on the back of the lead frame is protected by a nickel-palladium-gold layer 101, which has good stability and performs well in high and low temperature cycle testing after secondary packaging: no feedback on failure during high and low temperature cycle testing was received for samples produced using this process after secondary packaging.

Claims

1. A package structure with pins side-plated tin, comprising a lead frame (1) and a chip (2) electrically connected to each other, characterized in that: The back cut area (20) of the lead frame (1) is pre-filled with bare copper, and the back of the lead frame (1) has a nickel-palladium-gold layer (101) that avoids the area where the bare copper is located. A portion of the surface of the side of the pin (10) has a tin layer (102) that extends to the back.

2. The package structure with pin-side tin plating as described in claim 1, characterized in that: The area of ​​the pin side surface covered with a tin layer accounts for less than 90% of the total area of ​​the pin side surface.

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