Semiconductor module, electronic device, and vehicle

Abstract

The utility model discloses a kind of semiconductor module, electronic equipment and vehicle, semiconductor module includes: chip layer and first insulating layer, first conductive layer.Chip layer includes multiple semiconductor chips;First insulating layer is laminated with chip layer, first conductive layer is set to the side of first insulating layer opposite chip layer, and conductive layer includes multiple first conductive regions, and one first conductive region is electrically connected with one semiconductor chip.The chip conductive connection end in the semiconductor module is more concentrated, structure is more compact, and the volume of module can be effectively reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor module, as well as electronic devices and vehicles. Background Technology

[0002] In related technologies, for modules that include multiple semiconductor chips, the chips are individually packaged, and the connections between individual chips or between chips and external components are made by directly connecting the corresponding pins of the chips through wire harnesses. The chip electrical connections are scattered, the process is complicated, the structure is not compact enough, and the module size is large.

[0003] This utility model content

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one objective of the present invention is to provide a semiconductor module in which the conductive connection terminals of the chips are located on the same layer, thus being more concentrated and the stacked structure is more compact, effectively reducing the size of the module.

[0005] The second objective of this invention is to provide an electronic device.

[0006] The third objective of this utility model is to propose a vehicle.

[0007] To address the aforementioned problems, a first aspect of this utility model provides a semiconductor module, comprising: a chip layer including a plurality of semiconductor chips; a first insulating layer stacked on top of the chip layer; and a first conductive layer disposed on the side of the first insulating layer facing away from the chip layer, the first conductive layer including a plurality of first conductive regions, one of the first conductive regions being electrically connected to one of the semiconductor chips.

[0008] According to the semiconductor module of this utility model embodiment, multiple semiconductor chips are designed as chip layers, and the chip layers are stacked with the first insulating layer, resulting in a more compact structure that can effectively reduce the size of the module. Furthermore, multiple first conductive regions electrically connected to the semiconductor chips are formed on the first conductive layer, which is equivalent to concentrating the conductive connection ends of the semiconductor chips on the same layer. The more concentrated the conductive connection ends of the chips are, the more conducive it is to the conductive connection of the semiconductor chips, the simpler the manufacturing process, and the lower the manufacturing cost.

[0009] In some embodiments, each of the semiconductor chips has a drive signal terminal, and each of the first conductive regions includes a first signal conductive portion, which is electrically connected to the drive signal terminal of the corresponding semiconductor chip.

[0010] In some embodiments, the first power conductive portion is electrically connected to the drive signal terminal corresponding to the semiconductor chip through a via in the first insulating layer.

[0011] In some embodiments, each of the semiconductor chips has a power signal output terminal, and each of the first conductive regions includes a first power conductive portion, which is electrically connected to the power signal output terminal of the corresponding semiconductor chip.

[0012] In some embodiments, the first power conductive portion is electrically connected to the power signal output terminal of the corresponding semiconductor chip through a via in the first insulating layer.

[0013] In some embodiments, a plurality of the first signal conductive regions are insulated.

[0014] In some embodiments, the semiconductor module further includes: a conductive substrate, wherein the conductive substrate, the chip layer, the first insulating layer stack, and the first conductive layer are disposed, and the chip layer is located between the conductive substrate and the first insulating layer.

[0015] In some embodiments, the conductive substrate includes: a second conductive layer, on which a plurality of insulatingly disposed second conductive regions are formed, and one second conductive region is electrically connected to one semiconductor chip and one first conductive region, respectively.

[0016] In some embodiments, each of the second conductive regions includes a chip conductive portion, which is electrically connected to the power signal input terminal of the corresponding semiconductor chip.

[0017] In some embodiments, the semiconductor chip is disposed on a corresponding conductive portion of the chip.

[0018] In some embodiments, each of the second conductive regions includes a second signal conductive portion, which is electrically connected to a first signal conductive portion of the corresponding semiconductor chip.

[0019] In some embodiments, each of the second conductive regions includes a second power conductive portion, which is electrically connected to a first power conductive portion of the corresponding semiconductor chip.

[0020] In some embodiments, the second signal conductive part is connected to the corresponding first signal conductive part through a via in the first insulating layer, and the second power conductive part is connected to the corresponding first power conductive part through a via in the first insulating layer.

[0021] In some embodiments, the conductive substrate further includes an insulating substrate and a third conductive layer, wherein the insulating substrate is located between the second conductive layer and the third conductive layer along the thickness direction of the first insulating layer.

[0022] In some embodiments, the semiconductor module further includes: a second insulating layer, wherein the second insulating layer is stacked with the conductive substrate, the chip layer, the first insulating layer, and the first conductive layer, and the second insulating layer is located on the side of the first conductive layer away from the first insulating layer.

[0023] In some embodiments, the semiconductor module further includes: a fourth conductive layer located along the thickness direction of the conductive substrate on the side of the second insulating layer away from the first conductive layer; the fourth conductive layer includes a plurality of pin conductive regions, one of the pin conductive regions being electrically connected to a second conductive region on the conductive substrate.

[0024] In some embodiments, each of the pin conductive regions is electrically connected to the corresponding second signal conductive region via a via.

[0025] In some embodiments, each of the pin conductive regions includes a signal pin conductive portion, the signal pin conductive portion being electrically connected to a second signal conductive portion of the corresponding semiconductor chip on the conductive substrate.

[0026] In some embodiments, each of the pin conductive regions includes a power pin conductive portion, the power pin conductive portion being connected to the second power conductive portion and the chip conductive portion of the corresponding semiconductor chip on the conductive substrate.

[0027] In some embodiments, the conductive substrate, the chip layer, the first insulating layer, the first conductive layer, the second insulating layer, and the fourth conductive layer are formed into a stacked structure through a lamination process.

[0028] In some embodiments, the plurality of semiconductor chips include at least one of a power factor correction chip, a primary-side power chip of an inductor-inductor-capacitor resonant circuit, a secondary-side power chip of an inductor-inductor-capacitor resonant circuit, a primary-side power chip of a DC-DC converter, and a secondary-side power chip of a DC-DC converter.

[0029] In some embodiments, a plurality of conductive partitions are formed on the second conductive layer, and each conductive partition has a plurality of second conductive regions distributed thereon.

[0030] In some embodiments, the plurality of conductive partitions include a first partition, a second partition, and a third partition; wherein the second partition and the third partition are located on the same side of the first partition, and both the second partition and the third partition are arranged adjacent to the first partition.

[0031] In some embodiments, the second partition and the third partition are arranged along the width direction of the conductive substrate, and the first partition and the second partition are arranged along the length direction of the conductive substrate.

[0032] In some embodiments, the plurality of semiconductor chips include a power factor correction chip, a primary-side power chip of an inductor-inductor-capacitor resonant circuit, a secondary-side power chip of an inductor-inductor-capacitor resonant circuit, a primary-side power chip of a DC-DC converter, and a secondary-side power chip of a DC-DC converter; wherein the power factor correction chip is electrically connected to the primary-side power chip of the inductor-inductor-capacitor resonant circuit, the primary-side power chip of the inductor-inductor-capacitor resonant circuit is electrically connected to the secondary-side power chip of the inductor-inductor-capacitor resonant circuit via a transformer, the secondary-side power chip of the inductor-inductor-capacitor resonant circuit is electrically connected to the primary-side power chip of the DC-DC converter, and the primary-side power chip of the DC-DC converter is electrically connected to the secondary-side power chip of the DC-DC converter.

[0033] In some embodiments, the power factor correction chip and the primary power chip of the inductor-inductor-capacitor resonant circuit are located in the first partition; the secondary power chip of the inductor-inductor-capacitor resonant circuit and the primary power chip of the DC-DC converter are located in the second partition, with the secondary power chip of the inductor-inductor-capacitor resonant circuit being close to the primary power chip of the inductor-inductor-capacitor resonant circuit; and the secondary power chip of the DC-DC converter is located in the third partition.

[0034] In some embodiments, at least one temperature sensing conductive portion is further provided on the second conductive layer, and a temperature sensing unit is provided on the temperature sensing conductive portion; at least one temperature sensing pin conductive portion is further formed on the second insulating layer, the temperature sensing pin conductive portion is insulated from the plurality of pin conductive regions, and the temperature sensing pin conductive portion is electrically connected to the corresponding temperature sensing conductive portion on the conductive substrate.

[0035] In some embodiments, a plurality of temperature sensing conductive parts are provided on the second conductive layer, and one temperature sensing conductive part is located in a conductive partition of the second conductive layer; a plurality of temperature sensing pin conductive parts are formed on the second insulating layer, and one temperature sensing pin conductive part is electrically connected to one of the temperature sensing conductive parts.

[0036] In some embodiments, the power module further includes a solder resist layer located in the fourth conductive layer along the thickness direction of the chip layer.

[0037] A second aspect of this utility model provides an electronic device including at least one power module as described in the above embodiments.

[0038] The electronic device according to the present invention realizes the conversion and control of electrical energy through modules. The modules have no terminals, no binding wires, and no pins, making the structure more compact. This can effectively reduce the size of the modules and increase the power density of the modules. Other driving components can be soldered to the surface of the modules through the module pins. The devices are arranged in the shortest distance on the chip, and a larger overcurrent cross-sectional area and lower stray inductance are designed to achieve the optimal design of power and drive.

[0039] A third aspect of this utility model provides a vehicle that includes the semiconductor module described in the above embodiments, or the vehicle includes the electronic device described in the above embodiments.

[0040] According to the vehicle of this utility model embodiment, the conversion and control of electrical energy are realized through modules. The modules have no terminals, no binding wires, and no pins, making the structure more compact. This can effectively reduce the size of the modules and increase the power density of the modules. Other driving components can be soldered to the surface of the modules through the module pins. The devices are arranged at the shortest distance on the chip, and a larger overcurrent cross-sectional area and lower stray inductance are designed to achieve the optimal design of power and drive.

[0041] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0042] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is a schematic diagram of a semiconductor module according to an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of the back side of a semiconductor module packaging structure according to an embodiment of the present invention;

[0045] Figure 3 This is a top view of the chip layer of a semiconductor module according to an embodiment of the present invention;

[0046] Figure 4 This is a top view of the first wiring layer of a semiconductor module according to an embodiment of the present invention;

[0047] Figure 5 This is a top view of the second wiring layer of a semiconductor module according to an embodiment of the present invention;

[0048] Figure 6 This is a schematic diagram of the appearance of a semiconductor module according to an embodiment of the present invention;

[0049] Figure 7 This is a structural block diagram of an electronic device according to an embodiment of the present invention;

[0050] Figure 8 This is a structural block diagram of a vehicle according to an embodiment of the present utility model;

[0051] Figure 9 This is a structural block diagram of a vehicle according to an embodiment of the present invention.

[0052] Figure label:

[0053] 30 vehicles;

[0054] 20 electronic devices;

[0055] Semiconductor Module 1000;

[0056] Conductive substrate 100; chip layer 200; first conductive substrate region 113; second conductive substrate region 123; third conductive substrate region 133; power factor correction high-frequency chip 210; power factor correction low-frequency / power frequency chip 220; inductor-inductor-capacitor resonant circuit primary-side chip 230; inductor-inductor-capacitor resonant circuit secondary-side chip 240; DC-DC converter primary-side chip 250 and DC-DC converter secondary-side chip 260; first partition 111; second partition 121; third partition 131; first temperature detection conductive part 271; second temperature detection conductive part 272; third temperature detection conductive part 273; first conductive layer 500; first via layer 400; first signal via 430 Second signal via 410; First signal conductive part 420; Second signal conductive part 110; First power via 440; Second power via 460; First power conductive part 450, Second power conductive part 120; First insulating layer 300; Fourth conductive layer 800; Second via layer 700; Second insulating layer 600; First signal pin conductive part 810; Second signal pin conductive part 850; Third signal pin conductive part 870; First power pin conductive part 820; Second power pin conductive part 860; Third power pin conductive part 880; Temperature sensing detection positive electrode conductive part 830, Temperature sensing detection negative electrode conductive part 840; Ceramic plate layer 112; Solder resist layer 900. Detailed Implementation

[0057] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0058] In existing technologies, for semiconductor modules such as power modules that contain multiple semiconductor chips, the semiconductor chips, such as power devices, have a large number of pins, resulting in high cost and high failure rate due to the pins being easily damaged components. Furthermore, while integrating the chips into a single package achieves power module integration, directly connecting them to the semiconductor chip pins using wire harnesses is prone to damage, and the dispersed electrical connections and chip distribution lead to a large module size, complex manufacturing processes, and are detrimental to module design and fabrication.

[0059] To address the above problems, the first aspect of this utility model provides a semiconductor module that can effectively reduce module size and simplify module manufacturing process.

[0060] The semiconductor module according to a first aspect embodiment of the present invention will now be described with reference to the accompanying drawings.

[0061] like Figure 1 As shown, the semiconductor module 1000 of this embodiment includes a chip layer 200, a first insulating layer 300, and a first conductive layer 400.

[0062] The chip layer 200 includes multiple semiconductor chips. In some embodiments, the semiconductor chips may include power chips such as MOS (Metal-Oxide-Semiconductor) chips, IGBT (Insulated Gate Bipolar Transistor) chips, light-emitting diode chips, or other types of semiconductor chips, etc., without specific limitations. That is, in the embodiments of this application, multiple semiconductor chips are arranged on the same layer.

[0063] The first insulating layer 300 and the chip layer 200 are stacked together. In this embodiment, the stacking of the two layers can be achieved through semiconductor processes such as lamination. Using a stacked configuration allows for a more compact structure, which helps to reduce the size of the semiconductor module 1000.

[0064] A first conductive layer 400 is formed on the side of the first insulating layer 300 away from the chip layer 200. Specifically, the first conductive layer 400 is disposed on the side of the first insulating layer 300 facing away from the chip layer 200. The first conductive layer 400 includes a plurality of first conductive regions, each of which is electrically connected to a semiconductor chip. In an embodiment, the first conductive region may include one or more conductive portions connected to the semiconductor chip.

[0065] In other words, it is equivalent to distributing the electrical connection terminals of multiple semiconductor chips in the same layer, which is more conducive to the conductive connection of semiconductor chips, simplifies the manufacturing process, and reduces the manufacturing cost.

[0066] Furthermore, in some embodiments, for a semiconductor chip having a drive signal terminal, such as a power chip including a gate, each first conductive region includes a first signal conductive portion, and the first signal conductive portion is electrically connected to the drive signal terminal of the corresponding semiconductor chip.

[0067] For example, in a power chip, the first signal conductive portion may include a gate signal conductive portion, wherein the gate signal conductive portion is connected to the gate of the power chip to transmit a gate drive signal. The first signal conductive portion may also include a signal Kelvin source conductive portion, etc., which is used to isolate the power circuit and signal circuit of the power chip and improve the stability of the gate drive signal.

[0068] In some embodiments, the first power conductive portion can be electrically connected to the drive signal terminal of the corresponding semiconductor chip through a via in the first insulating layer 300.

[0069] In an embodiment, for a semiconductor chip with a power signal output terminal, such as the source of a power chip, each first conductive region further includes a first power conductive portion, which is electrically connected to the power signal output terminal of the corresponding semiconductor chip.

[0070] For example, in the case of a power chip, the first power conductive part may include a source conductive part, which is connected to the source of the power chip, and the source is used to output the power signal of the power chip.

[0071] In the embodiments of this utility model, the signal conductive parts and power conductive parts of multiple semiconductor chips are concentrated on the same layer, which reduces the number of PCB layers and simplifies the manufacturing process.

[0072] In one embodiment, multiple first signal conductive regions are insulated from each other. For example, adjacent first signal conductive regions can be isolated by insulating adhesive or other insulating materials to prevent short circuits.

[0073] In an embodiment, such as Figure 1 As shown, the power signal conductive portions in the plurality of first signal conductive regions 500 can also be electrically connected to the corresponding semiconductor chips through vias 400 in the first insulating layer 300. This eliminates the need for wire bonding, resulting in a more compact structure.

[0074] Furthermore, compared to wire bonding, which requires horizontal crossing of the chip, vias can vertically interconnect, thus shortening the current transmission path. In addition, vias can be cylindrical, while wire bonding is usually circular with a smaller diameter. Therefore, vias usually have a larger cross-sectional area and a more uniform current distribution, which helps to reduce stray inductance.

[0075] like Figure 1 As shown, the semiconductor module 1000 of this embodiment of the present invention also includes a conductive substrate 100.

[0076] The conductive substrate 100, chip layer 200, first insulating layer 300, and first conductive layer 400 are stacked along the thickness direction of the conductive substrate 100. The chip layer 200 is located between the conductive substrate 100 and the first insulating layer 300. In this embodiment, the stacking can be achieved by lamination process, that is, multiple semiconductor chips are embedded in the PCB of the entire semiconductor module 1000, resulting in a compact structure and small size.

[0077] In an embodiment, the conductive substrate 100 includes a second conductive layer, on which a plurality of insulating second conductive regions are formed. Each second conductive region is electrically connected to a semiconductor chip and a first conductive region to realize the transmission of signals related to the semiconductor chip.

[0078] Furthermore, in the embodiments, the second conductive region can be connected to the first conductive region or the semiconductor chip by a wire harness. The second conductive region can also be electrically connected to the corresponding first conductive region through a via in the first insulating layer 300, thereby shortening the signal loop path and reducing stray inductance.

[0079] In some embodiments, the conductive substrate 100 may be a single copper layer, such as a second conductive layer, or a single-sided or double-sided copper-clad ceramic plate. In some embodiments, the conductive substrate 100 further includes an insulating substrate and a third conductive layer, with the insulating substrate located between the second and third conductive layers along the thickness direction of the first insulating layer. For example, the insulating substrate may be a ceramic plate or other insulating plate, and the conductive layer may be a copper layer, an aluminum layer, or other conductive layers.

[0080] For example, in some embodiments, the conductive substrate 100 includes a second conductive layer, a ceramic plate layer 112, and a third conductive layer. Specifically, the ceramic plate layer 112 is located between the second and third conductive layers. The second conductive layer has a chip drain conductive portion, a chip signal conductive portion, and a chip power conductive portion formed therein. The ceramic plate layer 112 has excellent insulation properties. Therefore, the ceramic plate layer 112 is located between the second and third conductive layers to provide insulation, thereby improving the reliability and stability of the power module 1000.

[0081] In an embodiment, each second conductive region may include a chip conductive portion, which is electrically connected to the power signal input terminal of the semiconductor chip.

[0082] For example, in a power module, the conductive part of the chip can be connected to the drain or collector of the power chip to input the power signal of the power chip.

[0083] In this embodiment, the semiconductor chip can be disposed on the substrate, for example, next to the conductive area of ​​the connected chip, or the semiconductor chip can be disposed on the corresponding conductive area of ​​the chip by means of a patch, for example, the power chip is patched on the corresponding conductive area of ​​the chip on the substrate, and the drain of the power chip is in close contact with the conductive area of ​​the chip.

[0084] In some embodiments, each second conductive region may further include a second signal conductive portion, which is electrically connected to a corresponding first signal conductive portion, and the first signal conductive portion is connected to a driving signal terminal of a corresponding semiconductor chip, thereby enabling the transmission of driving signals from the semiconductor chip.

[0085] In some embodiments, each second conductive region further includes a second power conductive portion, which is electrically connected to a first power conductive portion of the corresponding semiconductor chip.

[0086] For example, for a power chip, the second power conductive part can correspond to the source conductive part of the power chip. The source conductive part is connected to the power signal output terminal of the power chip, such as the source, through the first power conductive part on the first insulating layer 300, thereby realizing the transmission of the power signal of the power chip.

[0087] In this embodiment, the second signal conductive part is connected to the corresponding first signal conductive part through a via in the first insulating layer, and the second power conductive part is connected to the corresponding first power conductive part through a via in the first insulating layer. This results in a shorter current path and reduced stray inductance.

[0088] In an embodiment, such as Figure 1 As shown, the semiconductor module 1000 further includes a second insulating layer 600, which is stacked with the conductive substrate 100, the chip layer 200, the first insulating layer 300, and the first conductive layer. The second insulating layer is located on the side of the first conductive layer 400 away from the first insulating layer 300. That is, the semiconductor module 1000 of this application is equivalent to a PCB board, and multiple semiconductor chips are embedded in the PCB board, resulting in a compact structure and small size.

[0089] Furthermore, the semiconductor module also includes a fourth conductive layer 800, which is located along the thickness direction of the conductive substrate on the side of the second insulating layer away from the first conductive layer. The fourth conductive layer includes a plurality of pin conductive regions, one of which is electrically connected to a second conductive region on the conductive substrate to achieve electrical connection between each semiconductor chip and the outside.

[0090] By centrally placing the connection terminals of multiple semiconductor chips to the outside on the second insulating layer, it is beneficial to simplify the manufacturing process and reduce the module size.

[0091] In the embodiment, each pin conductive area is connected to the corresponding second signal conductive area through a via, for example, the chip conductive part, the second signal conductive part and the second power conductive part are electrically connected to each other, thereby realizing the transmission of semiconductor chip drive signals and power signals, and the stray inductance of the module can be greatly reduced by the via connection.

[0092] Each pin conductive region may include a signal pin conductive portion, which is connected to a second signal conductive portion of the corresponding semiconductor chip on the conductive substrate 100 to realize the transmission of semiconductor chip drive signals.

[0093] In some embodiments, each pin conductive region includes a power pin conductive portion, which is connected to a second power conductive portion and a chip conductive portion of a corresponding semiconductor chip on the conductive substrate 100, thereby enabling a semiconductor chip power signal transmission loop.

[0094] In some embodiments, the conductive substrate 100, chip layer 200, first insulating layer 300, first conductive layer 400, second insulating layer 600, and fourth conductive layer 800 are laminated to form a stacked structure, i.e., the semiconductor module 1000 is equivalent to a PCB board. The module has no terminals, no bonding wires, and no pins inside, making the structure more compact. This can effectively reduce the size of the module, increase the power density of the module, simplify the manufacturing process, reduce the cost, and enable process automation. Signal pins and power pins are provided on the second insulating layer 600, so that other driving components of the module can be soldered to the surface of the semiconductor module through pins on the PCB board surface, arranging devices at the shortest distance on the chip and achieving optimal power and drive design.

[0095] In some embodiments, the plurality of semiconductor chips may include at least one of a power factor correction chip, a primary-side power chip of an inductor-inductor-capacitor resonant circuit, a secondary-side power chip of an inductor-inductor-capacitor resonant circuit, a primary-side power chip of a DC-DC converter, and a secondary-side power chip of a DC-DC converter. The primary-side power chip of the inductor-inductor-capacitor resonant circuit is the power chip connected to the primary coil side of the transformer in the inductor-inductor-capacitor resonant circuit; the secondary-side power chip of the inductor-inductor-capacitor resonant circuit is the power chip connected to the secondary coil side of the transformer in the inductor-inductor-capacitor resonant circuit; the primary-side power chip of the DC-DC converter is the power chip connected to the primary coil side of the transformer in the DC-DC converter; and the secondary-side power chip of the DC-DC converter is the power chip connected to the secondary coil side of the transformer in the DC-DC converter. Alternatively, the semiconductor chips may be other types of chips, without specific limitations.

[0096] Furthermore, to optimize chip layout, the conductive substrate 100 can employ a multi-conductive region distribution. For example, in some embodiments, multiple conductive partitions are formed on the first conductive layer, each conductive partition has multiple second conductive regions, and multiple semiconductor chips are distributed on the corresponding chip conductive regions within the multiple conductive partitions. In this way, the distribution position of the semiconductor chips can be set based on the circuit topology of each semiconductor chip within the module, reducing the chip circuit path and making the module structure more compact.

[0097] For example, in some embodiments, the conductive substrate 100 is formed with three conductive zones, namely as follows: Figure 3 The diagram shows a first partition 111, a second partition 121, and a third partition 131, wherein the second partition 121 and the third partition 131 are located on the same side of the first partition 111, and are distributed adjacent to the first partition 111. This compact distribution helps reduce the module size.

[0098] Specifically, Figure 2 For the copper clad substrate with three corresponding zones, the copper clad area distribution on the other side is as follows: Figure 2 The middle and lower copper cladding areas are the same. The second partition 121 and the third partition 131 are arranged along the width direction of the conductive substrate 100. The first partition 111 and the second partition 121 are arranged along the length direction of the conductive substrate 100. The first partition 111 and the third partition 131 are arranged along the length direction of the conductive substrate 100.

[0099] Furthermore, based on the distribution of conductive partitions on the conductive substrate 100, taking a power chip as an example, multiple semiconductor chips may include at least one of a power factor correction chip, a primary-side power chip of an inductor-inductor-capacitor resonant circuit, a secondary-side power chip of an inductor-inductor-capacitor resonant circuit, a primary-side power chip of a DC-DC converter, and a secondary-side power chip of a DC-DC converter. Specifically, the primary-side power chip of the inductor-inductor-capacitor resonant circuit is the power chip connected to the primary coil side of the transformer in the inductor-inductor-capacitor resonant circuit; the secondary-side power chip of the inductor-inductor-capacitor resonant circuit is the power chip connected to the secondary coil side of the transformer in the inductor-inductor-capacitor resonant circuit; the primary-side power chip of the DC-DC converter is the power chip connected to the primary coil side of the transformer in the DC-DC converter; and the secondary-side power chip of the DC-DC converter is the power chip connected to the secondary coil side of the transformer in the DC-DC converter.

[0100] In this circuit, the power factor correction chip is electrically connected to the primary power chip 230 of the inductor-inductor-capacitor resonant circuit. The primary power chip 230 is electrically connected to the secondary power chip of the inductor-inductor-capacitor resonant circuit via a transformer. The secondary power chip 240 is electrically connected to the primary power chip 250 of the DC-DC converter circuit. The primary power chip 250 is electrically connected to the secondary power chip 260 of the DC-DC converter circuit. This circuit topology can be applied to on-board chargers, inverter modules, etc., to achieve voltage conversion after inversion and rectification.

[0101] In some embodiments, the power factor correction chip (210+220) and the primary-side power chip 230 of the inductor-inductor-capacitor resonant circuit are located in the first partition 111; the secondary-side power chip 240 of the inductor-inductor-capacitor resonant circuit and the primary-side power chip 250 of the DC-DC converter are located in the second partition 121, with the secondary-side power chip 240 of the inductor-inductor-capacitor resonant circuit close to the primary-side power chip 230; and the secondary-side power chip 260 of the DC-DC converter is located in the third partition 131. This arrangement allows for shorter paths for chip connection and signal transmission, resulting in low stray inductance.

[0102] The operation of the semiconductor module 100, especially the semiconductor chip, is greatly affected by temperature. In order to ensure the normal operation of the chip, in some embodiments, at least one temperature detection conductive area is provided on the conductive substrate 100. A temperature detection unit, such as a thermistor, is provided on the temperature detection conductive area to detect the temperature of the conductive substrate, thereby reflecting the temperature of the semiconductor chip.

[0103] At least one temperature sensing pin conductive portion is also formed on the second conductive layer. The temperature sensing pin conductive portion is insulated from the multiple pin conductive portions and is electrically connected to the corresponding temperature detection conductive area on the conductive substrate 100, thereby enabling the transmission of the detected temperature signal.

[0104] Specifically, the second conductive layer may be provided with multiple temperature detection conductive parts, which are located in multiple conductive portions of the conductive substrate to detect the temperature of the semiconductor chip on each conductive portion.

[0105] Similarly, multiple temperature sensing pin conductive parts are formed on the second conductive layer, and the multiple temperature sensing pin conductive parts are electrically connected to the multiple temperature detection conductive parts, thereby enabling the monitoring of the temperature of the semiconductor chip on each conductive zone.

[0106] Based on the above embodiments, the first conductive layer includes multiple first conductive regions, such as first signal conductive regions and first power conductive regions, which correspond to the connection wiring between the signal terminals and power terminals of each semiconductor chip. Therefore, in some embodiments, the first conductive layer, i.e., the entirety of the multiple first signal conductive regions and the multiple first power conductive regions, can be referred to as the first wiring layer. Similarly, the fourth conductive layer 800 includes multiple pin conductive regions, such as signal pin conductive regions and power pin conductive regions, which correspond to the electrical connection lines between the semiconductor chip and the outside. In some embodiments, the entirety of the multiple pin conductive regions can be referred to as the second wiring layer. In the embodiments, the entirety of the vias in the first insulating layer 300 can be referred to as the first via layer, and the entirety of the vias in the second insulating layer 600 can be referred to as the second via layer.

[0107] Specifically, the conductive substrate 100, also known as a circuit board or PCB (Printed Circuit Board), is a flat plate made of conductive material (such as copper). For example, the conductive substrate 100 can be a double-sided copper-clad ceramic plate, the surface of which is treated to form circuit patterns to realize circuit connection and control signal transmission. The conductive substrate 100 is not only a fixed support for electronic components, but also provides protection for the circuit to prevent mechanical damage and external environmental interference.

[0108] Chip layer 200 may contain multiple semiconductor chips, such as power device chips, each with a specific function. Chip layer 200 is located on conductive substrate 100, which provides fixed support for the multiple semiconductor chips in chip layer 200. For example, semiconductor chips can be attached to corresponding conductive areas of conductive substrate 100 using a surface mount technology.

[0109] The first conductive layer 400 and the fourth conductive layer 800, namely the first wiring layer and the second wiring layer mentioned above, are mainly used to connect various semiconductor chips in the module, such as to realize the connection of the signal circuit and power circuit of the chip. The design and optimization of the wiring layer directly affects the performance, reliability and manufacturing cost of the circuit. The wiring layer is usually made of metal (such as copper) and is used to transmit electrical signals or power.

[0110] by Figure 1 As shown in the example, the first conductive layer is located on the side of the chip layer 200 away from the conductive substrate 100 in the thickness direction of the conductive substrate 100. The first conductive layer is electrically connected to the chip layer 200 and the conductive substrate 1000 and is used to transmit small current signals and / or power signals of the chip in the chip layer 200.

[0111] Specifically, one of the main functions of the first conductive layer is to transmit small current signals and power signals from the chip in the chip layer 200. Small current signals typically refer to electrical signals with relatively small current values. Because of the small current values, high precision is often required for the measurement of small currents to avoid the impact of measurement errors on circuit performance. Power signals refer to larger current signals used to drive loads or perform energy conversion. The first conductive layer plays a crucial role in signal transmission between the conductive substrate 100 and the chip layer 200, ensuring the stability and reliability of the entire circuit system.

[0112] Via layers, such as first and second via layers, relate to electrical connections between multilayer boards. In some embodiments, a via layer does not refer to a specific physical layer, but rather to an electrical connection layer established between different physical layers through vias. To connect printed conductors between layers, a common hole is drilled at the intersection of the conductors that need to be connected, and copper is plated to form a pathway structure, thereby achieving electrical connections between multilayer boards. Via layers also play an important role in signal transmission, power delivery, and ground connections. Figure 1 As can be seen, the first via layer is located between the chip layer 200 and the first wiring layer, so that the chip layer 200 is electrically connected to multiple first conductive areas on the first insulating layer 300 through the first via layer, thereby realizing the transmission of semiconductor chip drive signals and power signals. At the same time, the pins of the semiconductor module 1000 can also be brought out through the second via layer, which facilitates subsequent testing of the semiconductor module 1000 through the pins.

[0113] Specifically, on the conductive substrate 100, a dedicated second signal conductive region is formed for each power device chip. These second signal conductive regions are used to electrically connect with the signal terminals of the power device chip. The first wiring layer is used to transmit drive signals. In the first wiring layer, one or more signal conductive regions are designed for each power device chip. These signal conductive regions correspond to the signal terminals of the power device chip and are used to transmit small current signals. The signal conductive regions are connected to the signal terminals of the chip and the corresponding second signal conductive regions on the conductive substrate 100 through via layers to ensure accurate signal transmission. For example, the signals may include signal Kelvin source and gate (gate drive of power device switch) signals, and the power terminals may include drain and source signals.

[0114] Furthermore, the signal transmission of the driving circuit and power circuit of the semiconductor chip is realized through the first via layer and the second via layer, thereby constructing a complete signal power transmission path.

[0115] According to the embodiment of the present invention, the semiconductor module 1000 realizes the electrical connection between the internal semiconductor chips and the pins for connecting the semiconductor module 1000 to the outside based on the wiring layer and the via layer. It eliminates the need for terminals, wire bonding, and pins, making the structure more compact. It can effectively reduce the size of the module, increase the power density of the module, and save materials and processes such as outer frame, wire bonding, and potting. The cost is lower, the manufacturing process is simpler, and the process can be automated. Other driving components can be soldered to the surface of the module through the power module pins, and the devices can be arranged in the shortest distance between the chips to achieve the optimal design of power and drive.

[0116] For example, Figure 1 This can be represented as an exploded view of an embedded OBC (On-Board Charger) - DC-DC converter semiconductor module. In order from bottom to top, the power module 1000 mainly consists of a conductive substrate 100, a chip layer 200, a first insulating layer 300, a first via layer 400, a first wiring layer 500, a second insulating layer 600, a second via layer 700, and a second wiring layer 800.

[0117] In some embodiments, taking a power device as an example, a plurality of chip drain conductive portions are formed on the conductive substrate 100; the chip layer 200 includes a plurality of power device chips, and the drain of the power device chip is connected to the corresponding chip drain conductive portion.

[0118] Specifically, the conductive substrate 100 can be formed with copper plating and etching to form the required conductive areas or electronic circuits. For example, multiple conductive areas, drains, power conductive areas, and signal conductive areas are formed for the corresponding power device chip. The drain of the chip is attached to the substrate, that is, the drain is connected to the copper layer on the substrate. The chip drain conductive area formed on the conductive substrate 100 is a specific area for connecting with the drain of the power device chip. The chip layer 200 contains multiple power device chips, which are used to realize functions such as power conversion, control, and regulation. Each power device chip has one or more drains, which need to be connected to the chip drain conductive area on the conductive substrate 100 to realize power transmission and device operation.

[0119] In some embodiments, the semiconductor module 1000 may adopt a semi-enclosed structure, that is, the first insulating layer 300 partially encloses the conductive substrate 100, and the side of the conductive substrate 100 away from the chip layer 200 is exposed. Alternatively, it may adopt an unenclosed or fully enclosed structure. Furthermore, a heat dissipation component, such as a heat sink, may be provided on the side of the conductive substrate 100 away from the chip layer 200.

[0120] In some embodiments, such as Figure 2As shown, for a double-sided copper-clad conductive substrate, corresponding to the three conductive zones of the conductive substrate 100, the other side of the conductive substrate away from the chip layer 200 can be provided with a first conductive substrate region 113, a second conductive substrate region 123 and a third conductive substrate region 133.

[0121] The second conductive substrate region 123 and the third conductive substrate region 133 are arranged along the width direction of the conductive substrate 100, and the first conductive substrate region 113, the second conductive substrate region 123, and the third conductive substrate region 133 are arranged along the length direction of the conductive substrate 100.

[0122] For example, Figure 2 The diagram shows the back view of the semiconductor module 1000 of the embedded OBC-DC converter circuit of this invention. The conductive substrate 100 can be a double-sided copper-clad ceramic plate. The conductive substrate 100 includes three conductive regions, wherein the surfaces of the first conductive substrate region 113, the second conductive substrate region 123, and the third conductive substrate region 133 are flush with the lower surface of the first insulating layer 300. This facilitates direct soldering to the heat sink and is beneficial for heat dissipation of the module. The insulating layer material includes prepreg materials with bonding properties such as FR4 (Flame Retardant) or BT (Bismaleimide and Triazine), which can be selected according to temperature resistance requirements. The ceramic material can be alumina, aluminum nitride, or silicon nitride. Compared with the low thermal conductivity of FR4 or BT, ceramic has a higher thermal conductivity, which can quickly transfer the heat generated by the chip to the downward, reduce the thermal resistance of the module, improve heat dissipation capacity, and reduce the junction temperature of the chip. The thickness of the double-sided copper-clad ceramic board can be adjusted according to the actual application and manufacturing process requirements. The thickness of the ceramic can be 0.2~1.0mm, and the thickness of the upper and lower copper layers can be 50~800um. Increasing the thickness of the ceramic layer and the upper and lower copper layers can prevent them from breaking during the lamination process.

[0123] In some embodiments, such as Figure 3 As shown, chip layer 200 contains multiple power device chips, such as power factor correction high-frequency chip 210, power factor correction low-frequency / power frequency chip 220, inductor-inductor-capacitor resonant circuit primary chip 230, inductor-inductor-capacitor resonant circuit secondary chip 240, DC-DC converter primary chip 250, and DC-DC converter secondary chip 260.

[0124] Among them, the high-frequency power factor correction chip 210, the low-frequency / power frequency power factor correction chip 220 and the primary-side chip 230 of the inductor-inductor-capacitor resonant circuit are located on the first partition 111; the secondary-side chip 240 of the inductor-inductor-capacitor resonant circuit and the primary-side chip 250 of the DC-DC converter are located on the second partition 121; and the secondary-side chip 260 of the DC-DC converter is located on the third partition 131.

[0125] Specifically, the high-frequency power factor correction chip 210 is typically used in power factor correction circuits. As a fast-response switching device, the high-frequency power factor correction chip 210 achieves precise control of the input current waveform through high-speed switching action, keeping it synchronized with the input voltage waveform, thereby improving the power factor. The low-frequency / power frequency power factor correction chip 220 is also used in power factor correction circuits, but compared with fast-response chips, its switching speed is slower. The low-frequency / power frequency power factor correction chip 220 achieves smooth control of the input current waveform through relatively slow switching action, which helps to improve the stability and efficiency of the system. The primary-side chip 230 of the inductor-inductor-capacitor resonant circuit is responsible for controlling the switching frequency and waveform of the circuit. The primary-side chip 230 of the inductor-inductor-capacitor resonant circuit achieves high efficiency by precisely controlling the switching frequency and duty cycle. Stable power conversion; the secondary chip 240 of the inductor-inductor-capacitor resonant circuit achieves stable power supply to the load by precisely controlling the output current and voltage. The secondary chip 240 of the inductor-inductor-capacitor resonant circuit usually works in conjunction with the primary chip 230 of the inductor-inductor-capacitor resonant circuit to achieve efficient and stable power conversion; the primary chip 250 of the DC-DC converter circuit is responsible for controlling the power conversion and control at the input end. The primary chip 250 of the DC-DC converter circuit achieves efficient conversion from input voltage to output voltage by precisely controlling the switching frequency and duty cycle; the secondary chip 260 of the DC-DC converter circuit ensures that the load receives stable power supply by precisely controlling the output current and voltage. The secondary chip 260 of the DC-DC converter circuit usually works in conjunction with the primary chip 250 of the DC-DC converter circuit to achieve efficient power conversion and stable output voltage.

[0126] For example, Figure 3 This diagram illustrates the layout of the chip layer 200 of the embedded OBC-DC integrated semiconductor module 1000 of this invention. Chip layer 200 includes a power factor correction high-frequency chip 210, a power factor correction low-frequency / power frequency chip 220, an inductor-inductor-capacitor resonant circuit primary-side chip 230, an inductor-inductor-capacitor resonant circuit secondary-side chip 240, a DC-DC converter primary-side chip 250, and a DC-DC converter secondary-side chip 260. The power factor correction high-frequency chip 210, the power factor correction low-frequency / power frequency chip 220, and the inductor-inductor-capacitor resonant circuit primary-side chip 230 are located on the first partition 111. The inductor-inductor-capacitor resonant circuit secondary-side chip 240 and the DC-DC converter primary-side chip 250 are located on the second partition 121; the DC-DC converter secondary-side chip 260 is located on the third partition 131.

[0127] The semiconductor module 1000 has a power output of 11 kW. The power factor correction high-frequency chip 210 contains three half-bridge modules, which can significantly improve the charging efficiency of the battery pack. The DC-DC converter circuit secondary chip 260 contains four parallel chips, which can also improve the charging power of the battery pack for vehicle electrical appliances and external electrical appliances. All chips can be connected to the upper copper layer of the double-sided copper-clad ceramic plate by soldering or sintering. Temperature chips are provided in all three substrate areas to detect the operating temperature of the chips.

[0128] In some embodiments, such as Figure 3 As shown, a first temperature detection conductive part 271, a second temperature detection conductive part 272 and a third temperature detection conductive part 273 can be formed on the conductive substrate 100.

[0129] The first temperature detection conductive part 271 is located on the first partition 113, the second temperature detection conductive part 272 is located on the second partition 121, and the third temperature detection conductive part 273 is located on the third partition 131. A temperature detection unit can be provided on each temperature detection conductive part to detect the temperature of each partition respectively.

[0130] Specifically, the first partition 111, the second partition 121 and the third partition 131 are integrated together. Through reasonable layout and heat dissipation design, the semiconductor module 1000 can be ensured to remain stable and efficient under long-term and high-load working conditions. During the operation of the semiconductor module 1000, the temperature of the chip on the substrate should be detected in real time, and the temperature of each partition should be detected separately to ensure that the chip operates at a stable operating temperature, thereby improving the overall performance and reliability of the power module 1000.

[0131] In some embodiments, such as Figure 4 As shown, the first via layer 400 may include: a first signal via 430 and a second signal via 410.

[0132] The first signal via 430 is connected to the signal terminal and the signal conductive part of the power device chip, and the second signal via 410 is connected to the signal conductive area and the second signal conductive part corresponding to the power device chip on the conductive substrate 100, so as to transmit the small current signal of the power device chip.

[0133] Specifically, the first signal via 430 is connected between the signal terminal of the power device chip and the first signal conductive part. The main function of the first signal via 430 is to transmit the small current signal generated by the power device chip. These signals are usually used for control, monitoring or communication purposes. The current is small but the accuracy and stability requirements are high. The small current signal generated by the signal terminal of the power device chip is transmitted to the signal conductive area through the first signal via 430. The second signal via 410 is connected between the signal conductive area and the second signal conductive part corresponding to the power device chip on the conductive substrate 100. The main function of the second signal via 410 is to further transmit the small current signal in the signal conductive area to the chip signal conductive area on the conductive substrate 100.

[0134] In some embodiments, such as Figure 4 As shown, the first via layer 400 includes a first power via 440 and a second power via 460.

[0135] The first power via 440 is connected to the power terminal of the power device chip and the first power conductive part, and the second power via 460 is connected to the power conductive area and the second power conductive part corresponding to the power device chip on the conductive substrate 100, so as to transmit the power signal of the power device chip.

[0136] Specifically, the first power via 440 is connected between the power terminal of the power device chip and the first power conductive portion. The main function of the first power via 440 is to transmit the power signal generated by the power device chip. These signals typically have large current and voltage and are used to provide the required power for the electronic device. The power signal generated by the power terminal of the power device chip is transmitted to the power conductive area through the first power via 440. The second power via 460 is connected between the power conductive area and the second power conductive portion corresponding to the power device chip on the conductive substrate 100. The main function of the second power via 460 is to further transmit the power signal in the power conductive area to the chip power conductive area on the conductive substrate 100 to transmit the power signal of the power device chip.

[0137] For example, taking power chips as an example, Figure 4This diagram shows a top view of the first wiring layer 500 of the embedded OBC-DC converter integrated semiconductor module 1000 of this invention. The signal Kelvin source of the chip is led out through the first signal via 430 above, then reaches the corresponding first signal conductive part 420, and then through the second signal via 410 to reach the corresponding second signal conductive part 110 on the conductive substrate. The chip gate connection method is similar and will not be described in detail here. The source in the chip power circuit is led out through the first power via 440 above, then reaches the first power conductive part 450, and then through the second power via 460 to reach the corresponding second power conductive part 120, and then is led out to the PCB surface of the semiconductor module through connecting copper pillars. The drain of the chip is connected to the upper copper layer of the double-sided copper-clad ceramic board. Electrical connection is achieved by using vias to deposit copper instead of traditional wire bonding. The number of vias is sufficient and the cross-sectional area of ​​the overcurrent copper layer is large, which can improve the overcurrent capability of the module and greatly reduce stray inductance. The signal copper layer and the power copper layer are located in the first wiring layer 500, which can reduce the number of PCB layers and make the manufacturing process simpler.

[0138] The first insulating layer 300 is located between the chip layer 200 and the first wiring layer 500, effectively isolating the connection between different power device chips and the first wiring layer 500, preventing direct electrical connection between the power device chips and the first wiring layer 500, thereby avoiding short circuits and ensuring the normal operation and stable functioning of the power module 1000.

[0139] In some embodiments, such as Figure 1 As shown, the second wiring layer 800 is located on the side of the first wiring layer 500 away from the power device chip layer 200 in the thickness direction of the conductive substrate 100. The second wiring layer 800 is connected to the conductive area corresponding to the power device chip on the conductive substrate 100 through a via layer.

[0140] In some embodiments, the second via layer 700 is connected to the second wiring layer 800 and the conductive area corresponding to the power device chip on the conductive substrate 100.

[0141] Specifically, the conductive areas of the signal pins in the second wiring layer 800 are used to receive external signals to ensure that signals can smoothly enter and exit the circuit board, such as... Figure 5 As shown, the third signal via can be located in Figure 5 At positions 710, 750, and 770, the main function of the third signal via is to achieve electrical connection between different layers. The chip signal conductive area of ​​a power device chip is usually located on a specific layer, while the conductive area of ​​the signal pin that needs to be connected may be located on another layer. The third signal via connects the conductive areas between these two layers, thereby realizing signal transmission and control.

[0142] In some embodiments, the second wiring layer includes a power pin conductive region; the second via layer includes a third power via, the third power via connecting the second power conductive portion of the power device chip on the conductive substrate, the chip conductive portion, and the corresponding power pin conductive region on the second wiring layer.

[0143] Specifically, the fourth conductive layer 800, also known as the second wiring layer mentioned above, is an internal layer in the multilayer structure of a PCB. It includes a power pin conductive area, which is a conductive region on the second wiring layer specifically designed for connecting power device pins. Figure 5 As shown, the third power via can be located in Figure 5 At positions 720, 760, and 780, the third power via is a specific via in the second via layer 700. It connects the chip power conductive area, the chip drain conductive area of ​​the power device chip on the conductive substrate 100, and the corresponding power pin conductive area on the second wiring layer 800. This connection method allows the pins of the power device to be directly connected to the internal wiring layer, thereby achieving efficient electrical connection and signal transmission.

[0144] Specifically, at least one temperature sensing conductive part is provided on the conductive substrate 100 for acquiring the temperature of the power device chip. The fourth conductive layer 800 includes a series of conductive lines and conductive areas for realizing electrical connections between circuit elements. In the fourth conductive layer 800, at least one temperature sensing pin conductive area is specifically provided. The temperature sensing pin conductive area is connected to the sensing pin of the temperature chip through a temperature via for receiving temperature signals from the temperature chip. Figure 5 As shown, the temperature via can be located in Figure 5 Positions at 730 and 740.

[0145] Specifically, the second insulating layer 600 is located between the first conductive layer 500 and the fourth conductive layer 800 in the thickness direction of the conductive substrate 100, and the second via layer 700 is embedded in the second insulating layer 600.

[0146] Specifically, in the power device chip layer 200, in addition to including multiple power device chips, it may also include at least one temperature detection conductive part, and the temperature detection conductive part is located on the conductive substrate 100. The temperature detection unit is usually an integrated circuit chip that can monitor and control temperature. In the power device chip layer 200, the main function of the temperature detection unit is to monitor the operating temperature of the power device in real time to ensure that it operates within a safe range.

[0147] The semiconductor module 1000 can be a key component in a power electronic system, mainly used for the conversion, control, and regulation of electrical energy. The conductive substrate 100 is the foundation of the semiconductor module 1000, providing electrical connections and heat dissipation paths. The presence of multiple conductive substrates 100 can support the distribution of multiple power device chips and temperature detection chips, thereby optimizing the module's performance and reliability. Distributing multiple power device chips on the conductive substrate 100 can improve the module's power density and efficiency, while also aiding in heat dissipation. In the power module 1000, the conductive substrate 100, power device chips, and temperature detection unit are integrated together through a precise design and manufacturing process. Through reasonable layout and heat dissipation design, the power module 1000 can be ensured to remain stable and efficient under long-term, high-load operating conditions.

[0148] Furthermore, in some embodiments, the semiconductor module 1000 also includes various pins connected to the above PCB board structure, such as signal pins. For example, signal pins are electrically connected to the conductive areas of signal pins to transmit small current signals from the power device chip.

[0149] Specifically, such as Figure 6 As shown, the signal pin conductive area includes a first signal pin conductive part 810, a second signal pin conductive part 850, and a third signal pin conductive part 870. The signal pin is connected to the signal pin conductive area. This connection method ensures that small current signals can be stably and efficiently transmitted to other devices. The main function of the signal pin conductive area is to receive small current signals from the signal pins of power device chips or other circuit elements and transmit these signals to other circuit elements for processing.

[0150] In some embodiments, the semiconductor module 1000 may further include power pins. These power pins are electrically connected to the power pin conductive region and are used to transmit power signals from the power device chip.

[0151] Specifically, such as Figure 6 As shown, the power pin conductive area includes: a first power pin conductive part 820, a second power pin conductive part 860, and a third power pin conductive part 880. The power pin is connected to the power pin conductive area. The main function of the power pin conductive area is to receive power signals from the power pins of the power device chip and transmit these signals to other circuit elements or external loads.

[0152] In some embodiments, the reporting module 1000 may further include a temperature sensing pin. The temperature sensing pin is connected to a temperature sensing pin conductive area and is used to connect a temperature sensor to acquire the temperature of the conductive substrate 100.

[0153] Specifically, such as Figure 6As shown, the conductive part of the temperature sensing pin includes: a positive temperature sensing pin conductive part 830 and a negative temperature sensing pin conductive part 840. The temperature sensing pin is connected to the conductive part of the temperature sensing pin. This connection method ensures that the temperature signal can be stably and accurately transmitted to other circuit components for processing. The main function of the conductive part of the temperature sensing pin is to receive the temperature signal from the sensing pin of the temperature sensor and transmit these signals to the temperature monitoring circuit or control system.

[0154] For example, Figure 5 This diagram shows a top view of the second wiring layer 800 of the embedded OBC-DC converter integrated power module 1000 of this invention. The fourth conductive layer 800 contains signal pin conductive portions and power pin conductive portions for each module. Each pin is electrically connected to the upper copper layer of the double-sided copper-clad ceramic via a copper via below. The first signal pin 810 primarily refers to the signal pin of the power factor correction module, and the first power pin conductive portion 820 refers to the power pin conductive portion of the power factor correction module. The second signal pin conductive portion 850 primarily refers to the signal pin conductive portion of the inductor-inductor-capacitor resonant circuit module, and the second power pin conductive portion 860 refers to the power pin conductive portion of the inductor-inductor-capacitor resonant circuit module. The third signal pin conductive portion 870 primarily refers to the signal pin conductive portion of the DC converter circuit module, and the third power pin conductive portion 880 refers to the power pin conductive portion of the DC converter circuit module. The signal pins of the OBC-DC converter circuit module are placed as close as possible to facilitate subsequent connection to the driver board. The conductive portions on the PCB surface can be used as pads for surface mount mounting of driver components, resulting in a more compact structure and reduced module size.

[0155] In some embodiments, such as Figure 6 As shown, the semiconductor module 1000 may also include a solder mask layer 900.

[0156] The solder mask layer 900 is located on the fourth conductive layer along the thickness direction of the chip layer to cover multiple pin conductive parts.

[0157] Specifically, the solder mask layer 900 is located above the fourth conductive layer 800. The main function of the solder mask layer 900 is to protect the wiring layers from damage caused by the external environment, such as oxidation, corrosion, and mechanical damage. The solder mask layer 900 is also used to define the soldering areas of the circuit board, ensuring that only specific areas are soldered during the soldering process. For example, in some embodiments, the solder mask layer 900 may be implemented using, but is not limited to, solder resist ink.

[0158] For example, Figure 6This diagram shows the overall appearance of the embedded OBC-DC converter integrated semiconductor module 1000 of this utility model. Based on the above-described semiconductor module configuration, the OBC-DC converter integrated semiconductor module 1000 is a thin-layer board with no terminals or bonding wires on its surface, offering advantages such as small size and high power density. The chip is embedded in the PCB, and electrical connections between layers are achieved through vias. The upper surface is coated with a layer of solder resist ink, providing insulation and oxidation resistance. The main electrodes of the power module 1000 are led out to the upper surface of the PCB, including a first signal pin conductive portion 810, a first power pin conductive portion 820, a temperature sensing positive electrode conductive portion 830, a temperature sensing negative electrode conductive portion 840, a second signal pin conductive portion 850, a second power pin conductive portion 860, a third signal pin conductive portion 870, and a third power pin conductive portion 880.

[0159] This utility model's embedded OBC-DC converter integrated power module 1000's power and drive circuits are entirely composed of copper layers, copper blocks, and connecting copper pillars, eliminating traditional wire bonding, reducing stray inductance, and increasing module connection reliability. Furthermore, this integrated power module 1000 eliminates the need for outer frames, wire bonding, and potting materials and processes, resulting in lower costs and a simpler manufacturing process, enabling automation. Driver components can be surface-mounted on the PCB, allowing for the placement of filter and driver components within the shortest possible chip distance, achieving optimal power and drive design. The more compact structure saves space and improves power density. The power module 1000 can be designed with a larger overcurrent cross-sectional area and lower stray inductance. Other driver components can be surface-mounted to the module surface, allowing for the placement of filter and driver components within the shortest possible chip distance, achieving optimal power and drive design.

[0160] A second aspect of this utility model provides an electronic device, such as... Figure 7 As shown, the electronic device 20 includes at least one semiconductor module 1000.

[0161] The electronic device according to the present invention realizes the conversion and control of electrical energy through a power module. The power module has no terminals, no binding wires, and no pins, making the structure more compact. It can effectively reduce the size of the module and increase the power density of the module. Other driving components can be soldered to the surface of the module through the power module pins. The devices are arranged in the shortest distance on the chip, and a larger overcurrent cross-sectional area and lower stray inductance are designed to achieve the optimal design of power and drive.

[0162] The third aspect of this utility model provides a vehicle, such as Figure 8 As shown, vehicle 30 includes semiconductor module 1000, or, as... Figure 9 As shown, vehicle 30 includes electronic equipment 20.

[0163] According to the vehicle of this utility model embodiment, the power module realizes the conversion and control of electrical energy. The power module has no terminals, no binding wires, and no pins, making the structure more compact. It can effectively reduce the size of the module and increase the power density of the module. Other driving components can be soldered to the surface of the module through the power module pins. The devices are arranged in the shortest distance of the chip, and a larger overcurrent cross-sectional area and lower stray inductance are designed to achieve the optimal design of power and drive.

[0164] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, substrate, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0165] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor module (1000), characterized in that, include: A chip layer (200) comprising a plurality of semiconductor chips; A first insulating layer (300) is stacked with the chip layer; A first conductive layer (500) is disposed on the side of the first insulating layer (300) facing away from the chip layer (200). The first conductive layer (500) includes a plurality of first conductive regions, and one of the first conductive regions is electrically connected to one of the semiconductor chips.

2. The semiconductor module (1000) according to claim 1, characterized in that, Each of the semiconductor chips has a drive signal terminal, and each of the first conductive regions includes: The first signal conductive part (420) is electrically connected to the driving signal terminal of the corresponding semiconductor chip.

3. The semiconductor module (1000) according to claim 2, characterized in that, The first signal conductive part (420) is electrically connected to the driving signal terminal of the corresponding semiconductor chip through a via in the first insulating layer (300).

4. The semiconductor module (1000) according to any one of claims 1-3, characterized in that, Each of the semiconductor chips has a power signal output terminal, and each of the first conductive regions (420+450) includes: A first power conductive part (450) is electrically connected to the power signal output terminal of the corresponding semiconductor chip.

5. The semiconductor module (1000) according to claim 4, characterized in that, The first power conductive part (450) is electrically connected to the power signal output terminal of the corresponding semiconductor chip through a via in the first insulating layer (300).

6. The semiconductor module (1000) according to claim 1, characterized in that, Multiple first conductive regions are insulated.

7. The semiconductor module (1000) according to claim 1, characterized in that, The semiconductor module (1000) also includes: A conductive substrate (100) is stacked with the conductive substrate (100), the chip layer (200), the first insulating layer (300), and the first conductive layer (500), wherein the chip layer (200) is located between the conductive substrate (100) and the first insulating layer (300).

8. The semiconductor module (1000) according to claim 7, characterized in that, The conductive substrate (100) includes: A second conductive layer is formed on which a plurality of insulating second conductive regions are formed. Each second conductive region is electrically connected to a semiconductor chip and a first conductive region (420+450), respectively.

9. The semiconductor module (1000) according to claim 8, characterized in that, Each of the second conductive regions includes: The chip conductive part is electrically connected to the power signal input terminal of the corresponding semiconductor chip.

10. The semiconductor module (1000) according to claim 9, characterized in that, The semiconductor chip is disposed on the corresponding conductive part of the chip.

11. The semiconductor module (1000) according to claim 8, characterized in that, Each of the second conductive regions includes: The second signal conductive part (110) is electrically connected to the first signal conductive part (420) of the corresponding semiconductor chip.

12. The semiconductor module (1000) according to claim 9, characterized in that, Each of the second conductive regions includes: The second power conductive part (120) is electrically connected to the first power conductive part (450) of the corresponding semiconductor chip.

13. The semiconductor module (1000) according to claim 11 or 12, characterized in that, The second signal conductive part (110) is connected to the corresponding first signal conductive part (420) through the via in the first insulating layer (300), and the second power conductive part (120) is connected to the corresponding first power conductive part (450) through the via in the first insulating layer (300).

14. The semiconductor module (1000) according to any one of claims 8-12, characterized in that, The conductive substrate (100) further includes: An insulating substrate and a third conductive layer (113+123+133) are arranged along the thickness direction of the first insulating layer (300), with the insulating substrate located between the second conductive layer and the third conductive layer (113+123+133).

15. The semiconductor module (1000) according to any one of claims 7-12, characterized in that, The semiconductor module (1000) also includes: The second insulating layer (600) is stacked with the conductive substrate (100), the chip layer (200), the first insulating layer (300), and the first conductive layer (500), and the second insulating layer (600) is located on the side of the first conductive layer (500) away from the first insulating layer (300).

16. The semiconductor module (1000) according to claim 15, characterized in that, The semiconductor module (1000) also includes: A fourth conductive layer (800) is located on the side of the second insulating layer (600) away from the first conductive layer (500) along the thickness direction of the conductive substrate (100). The fourth conductive layer (800) includes a plurality of pin conductive regions (810-880), one of the pin conductive regions (810-880) being electrically connected to a second conductive region on the conductive substrate (100).

17. The semiconductor module (1000) according to claim 16, characterized in that, Each of the said pin conductive regions (810-880) is electrically connected to the corresponding second conductive region through a via.

18. The semiconductor module (1000) according to claim 16, characterized in that, Each of the said pin conductive regions (810-880) includes: The signal pin conductive portion (810+850+870) is electrically connected to the second signal conductive portion (110) of the corresponding semiconductor chip on the conductive substrate (100).

19. The semiconductor module (1000) according to claim 16, characterized in that, Each of the said pin conductive regions (810-880) includes: The power pin conductive portion (820+860+880) is connected to the second power conductive portion (120) and the chip conductive portion of the corresponding semiconductor chip on the conductive substrate (100).

20. The semiconductor module (1000) according to any one of claims 1-3 and 7-12, characterized in that, The conductive substrate (100), the chip layer (200), the first insulating layer (300), the first conductive layer (500), the second insulating layer (600) and the fourth conductive layer (800) are laminated to form a stacked structure.

21. The semiconductor module (1000) according to any one of claims 1-3 and 7-12, characterized in that, The plurality of semiconductor chips include at least one of a power factor correction chip (210+220), a primary power chip (230) of an inductor-inductor-capacitor resonant circuit, a secondary power chip (240) of an inductor-inductor-capacitor resonant circuit, a primary power chip (250) of a DC-DC converter circuit, and a secondary power chip (260) of a DC-DC converter circuit.

22. The semiconductor module (1000) according to any one of claims 8-12, characterized in that, Multiple conductive partitions are formed on the second conductive layer, and each conductive partition has multiple second conductive regions distributed thereon.

23. The semiconductor module (1000) according to claim 22, characterized in that, The plurality of conductive partitions include a first partition (111), a second partition (121), and a third partition (131); The second partition (121) and the third partition (131) are located on the same side of the first partition (111), and both the second partition (121) and the third partition (131) are arranged adjacent to the first partition (111).

24. The semiconductor module (1000) according to claim 23, characterized in that, The second partition (121) and the third partition (131) are arranged along the width direction of the conductive substrate (100), the first partition (111) and the second partition (121) are arranged along the length direction of the conductive substrate (100), and the first partition (111) and the third partition (131) are arranged along the length direction of the conductive substrate (100).

25. The semiconductor module (1000) according to claim 24, characterized in that, The plurality of semiconductor chips include a power factor correction chip (210+220), a primary power chip (230) of an inductor-inductor-capacitor resonant circuit, a secondary power chip (240) of an inductor-inductor-capacitor resonant circuit, a primary power chip (250) of a DC-DC converter circuit, and a secondary power chip (260) of a DC-DC converter circuit. The power factor correction chip (210+220) is electrically connected to the primary power chip (230) of the inductor-inductor-capacitor resonant circuit. The primary power chip (230) of the inductor-inductor-capacitor resonant circuit is electrically connected to the secondary power chip (240) of the inductor-inductor-capacitor resonant circuit through a transformer. The secondary power chip (240) of the inductor-inductor-capacitor resonant circuit is electrically connected to the primary power chip (250) of the DC-DC converter circuit. The primary power chip (250) of the DC-DC converter circuit is electrically connected to the secondary power chip (260) of the DC-DC converter circuit.

26. The semiconductor module (1000) according to claim 25, characterized in that, The power factor correction chip (210+220) and the primary power chip (230) of the inductor-inductor-capacitor resonant circuit are located in the first partition (111). The secondary power chip (240) of the inductor-inductor-capacitor resonant circuit and the primary power chip (250) of the DC-DC converter circuit are located in the second partition (121), and the secondary power chip (240) of the inductor-inductor-capacitor resonant circuit is close to the primary power chip (230) of the inductor-inductor-capacitor resonant circuit. The secondary power chip (260) of the DC-DC converter circuit is located in the third partition (131).

27. The semiconductor module (1000) according to any one of claims 8-12, characterized in that, The second conductive layer is further provided with at least one temperature detection conductive part (271+272+273), and the temperature detection conductive part is provided with a temperature detection unit; At least one temperature sensing pin conductive portion (830+840) is also formed on the second insulating layer (600). The temperature sensing pin conductive portion (830+840) is insulated from multiple pin conductive areas (810-880). The temperature sensing pin conductive portion (830+840) is electrically connected to the corresponding temperature detection conductive portion (271+272+273) on the conductive substrate (100).

28. The semiconductor module (1000) according to claim 27, characterized in that, The second conductive layer is provided with multiple temperature detection conductive parts (271+272+273), and one temperature detection conductive part (271+272+273) is located in a conductive partition of the second conductive layer; A plurality of temperature sensing pin conductive portions (830+840) are formed on the second insulating layer (600), and one temperature sensing pin conductive portion (830+840) is electrically connected to one of the temperature detection conductive portions (271+272+273).

29. The semiconductor module (1000) according to any one of claims 1-3 and 6-8, characterized in that, The semiconductor module (1000) further includes a solder resist layer (900), which is located in the fourth conductive layer (800) along the thickness direction of the chip layer.

30. An electronic device (20), characterized in that, The electronic device (20) includes at least one semiconductor module (1000) as described in any one of claims 1-29.

31. A vehicle (30), characterized in that, The vehicle (30) includes a semiconductor module (1000) according to any one of claims 1-29, or the vehicle (30) includes an electronic device (20) according to claim 30.

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