Semiconductor package device

Abstract

The application provides a semiconductor packaging device, which comprises a redistribution layer, an electronic element arranged on the redistribution layer, and a rigid reinforcing structure arranged on the redistribution layer and located at the side of the electronic element, wherein the rigid reinforcing structure has a laterally arranged hole, and the rigid reinforcing structure and the electronic element are not overlapped in the vertical direction. The semiconductor packaging device provided by the application does not need to limit the material selection range of the mold sealing material, improves the process flexibility, does not need to increase the thickness of the EMC, avoids material waste, and does not affect the placement operation of the electronic element, and improves the process efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically to a semiconductor packaging device. Background Technology

[0002] Fan-out Multi-Chip Module (FOMCM) in Panel-Level Packaging (PNL) is a packaging technology that uses a fan-out layer (FO) instead of a traditional substrate to connect chips and solder balls. This technology offers advantages such as the ability to package a large number of packaging units (PKGs) in a single packaging operation, and high utilization due to its square design. However, this technology also has certain drawbacks. Specifically, the diagonal length of a square wafer is longer than that of a circular wafer, which can easily lead to greater warpage during the packaging process.

[0003] To address warpage issues, during molding and preceding process steps, a carrier, such as a glass carrier, can be used to support the upper package structure, effectively controlling warpage deformation. However, after the debonding step, the package structure loses its carrier support. At this point, the fan-out layer, being more flexible than the substrate, is more prone to warpage deformation after stress release, and the degree of warpage may exceed the acceptable range for subsequent process steps.

[0004] Currently, two methods are commonly used to improve the aforementioned warpage problem: one is to use a high-rigidity molding compound to replace the traditional molding compound; the other is to increase the thickness of the molding compound during the molding process. However, both methods have some drawbacks. Using a high-rigidity molding compound narrows the range of material choices, limiting process flexibility; while increasing the thickness of the molding compound results in material waste, as more material needs to be removed during subsequent grinding steps. Utility Model Content

[0005] The purpose of this application is to provide a semiconductor packaging device that helps to improve the packaging warpage problem.

[0006] This application discloses a semiconductor packaging device comprising: a redistribution layer; an electronic component disposed on the redistribution layer; and a rigid reinforcement structure disposed on the redistribution layer and located on the side of the electronic component, the rigid reinforcement structure having a laterally disposed hole, and the rigid reinforcement structure and the electronic component not overlapping in the vertical direction.

[0007] In some alternative implementations, the rigid reinforcement structure is a one-piece structure.

[0008] In some alternative implementations, the holes extend to the lower surface of the rigid reinforcement structure.

[0009] In some optional embodiments, the hole is at a predetermined distance from both the upper and lower surfaces of the rigid reinforcement structure.

[0010] In some alternative implementations, the rigid reinforcement structure is square and surrounds the electronic component in a top view.

[0011] In some alternative embodiments, the rigid reinforcement structure has the holes on all four sides.

[0012] In some alternative implementations, the sides of the redistribution layer and the sides of the rigid reinforcement structure are substantially flush.

[0013] In some alternative embodiments, the semiconductor packaging device further includes a molding layer disposed on the redistribution layer and covering the electronic components.

[0014] In some alternative implementations, the sides of the rigid reinforcement structure are exposed outside the molding layer.

[0015] In some alternative implementations, the sealing layer fills the holes.

[0016] In some alternative implementations, the upper surface of the rigid reinforcement structure is substantially flush with the upper surface of the molding layer.

[0017] In some alternative embodiments, the sealing layer covers the upper surface of the rigid reinforcement structure.

[0018] In some alternative embodiments, the rigid reinforcement structure is a metal, ceramic, glass, or polymer material.

[0019] In some alternative implementations, the rigid reinforcement structure is metal and electrically connected to the ground wire in the redistribution layer.

[0020] In some alternative implementations, the rigid reinforcement structure does not contact the electronic component.

[0021] In some alternative embodiments, the semiconductor packaging device further includes an electrical connector disposed on the lower surface of the redistribution layer.

[0022] To address the limitations of material selection due to the use of high-rigidity molding materials and the material waste caused by increasing the thickness of the molding material, this application proposes a semiconductor packaging device. This device utilizes a rigid reinforcement structure above the redistribution layer, with holes designed into the sidewalls of the reinforcement structure. This allows the rigid reinforcement structure to suppress package warpage, and the holes facilitate the flow of molding material during the molding process. Therefore, it eliminates the need to limit the range of molding material selection, improving process flexibility; it also eliminates the need to increase the thickness of the EMC (electromagnetic composite material), avoiding material waste. Furthermore, the rigid reinforcement structure and electronic components do not overlap vertically, thus not affecting the placement of electronic components and improving process efficiency. Additionally, this solution can increase the process window, i.e., expand the acceptable range of process parameters, such as temperature, pressure, and material properties. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging device based on existing technology;

[0025] Figure 2 This is a schematic diagram of the manufacturing steps of a semiconductor packaging device based on existing technology;

[0026] Figure 3 This is a schematic diagram of a longitudinal cross-section of a panel-type encapsulation structure based on existing technology.

[0027] Figure 4 This is a top view of a semiconductor packaging apparatus according to an embodiment of this application;

[0028] Figure 5 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device according to an embodiment of this application;

[0029] Figure 6 This is a side view of a rigid reinforcement structure according to an embodiment of this application;

[0030] Figure 7 This is a three-dimensional structural schematic diagram of a rigid reinforcement structure according to an embodiment of this application;

[0031] Figure 8 This is a side view of a rigid reinforcement structure according to another embodiment of this application;

[0032] Figure 9 This is a side view of a rigid reinforcement structure according to yet another embodiment of this application;

[0033] Figure 10 This is a top view of a panel-type encapsulation structure according to this application;

[0034] Figure 11 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device according to another embodiment of this application;

[0035] Figure 12 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device according to yet another embodiment of this application;

[0036] Figures 13 to 14 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application.

[0037] Explanation of reference numerals / symbols in the attached diagram:

[0038] 11: Rewiring layer; 12: Electronic components; 13: Rigid reinforcement structure; 131: Hole; 14: Mold sealing layer; 15: Electrical connectors; 16: Carrier board; 17: Panel;

[0039] 21: Redundancy layer; 22: Electronic component; 23: Mold layer; 24: Solder ball; 25: Carrier;

[0040] 100, 200, 300, 400: Semiconductor packaging devices;

[0041] C1-C6: Steps; S1-S7: Steps. Detailed Implementation

[0042] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0043] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0044] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0046] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0047] As used herein, the terms “substantial,” “approximately,” and “about” are used to indicate and explain minor variations. For example, when used in conjunction with numerical values, these terms may refer to a range of variation less than or equal to ±10% of the corresponding value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. When used in conjunction with events or circumstances, the terms “substantial,” “approximately,” and “about” may refer to an event or circumstance occurring precisely or very approximately.

[0048] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0049] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0050] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging device 100 based on existing technology. (Example) Figure 1 As shown, the semiconductor packaging device 100 includes a redistribution layer (RDL) 21 as a fan-out layer, an electronic component 22 disposed above the redistribution layer 21, a molding layer 23 encapsulating the electronic component 22, and solder balls 24 disposed below the redistribution layer.

[0052] refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the manufacturing steps of a semiconductor packaging device 100 based on existing technology. (Example) Figure 2 As shown, the manufacturing steps of the semiconductor packaging device 100 include:

[0053] Step C1: Fabricate a redistribution layer 21 on a carrier 25, wherein the carrier 25 may be a glass carrier.

[0054] Step C2: Place the electronic component 22 above the redistribution layer 21.

[0055] Step C3: Perform molding to form a molding layer 23 covering the electronic component 22.

[0056] Step C4: Debond the vector 25.

[0057] Step C5: Perform solder ball placement, placing solder balls 24 below the redistribution layer 21.

[0058] Step C6: Monomerize the semiconductor into individual units by cutting them to obtain a single semiconductor packaging device 100.

[0059] In the above manufacturing process, starting from step C1, the redistribution layer 21 is supported by the carrier 25, which can prevent warping deformation. However, in step C4, since the carrier 25 is removed, the redistribution layer 21 is prone to warping deformation after the stress is released, and the degree of warping may exceed the acceptable range for subsequent steps, causing subsequent steps to fail to be executed smoothly.

[0060] Here, the semiconductor packaging device 100 can be manufactured using panel-level packaging (PNL) technology, and the semiconductor packaging device 100 can specifically be a fan-out multi-chip module (FOMCM).

[0061] refer to Figure 3 , Figure 3 This is a longitudinal cross-sectional diagram of a panel-type (PNL form) packaging structure from existing technology. (Example:) Figure 3 As shown, a panel can include multiple semiconductor packaging devices 100 arranged in an array to improve process efficiency. However, compared to a single semiconductor packaging device 100, the panel has a larger area and a correspondingly greater degree of warpage.

[0062] Currently, in order to control warpage, using a high-rigidity molding material for the molding layer 23 would narrow the range of material choices; increasing the thickness of the molding layer 23 would result in material waste. Therefore, a new technical solution is urgently needed to control warpage.

[0063] refer to Figure 4 and Figure 5 , Figure 4 This is a top view of a semiconductor packaging apparatus 200 according to an embodiment of this application. Figure 5 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 200 according to an embodiment of this application (i.e., Figure 4 (AA sectional view). For example... Figure 4 and Figure 5 As shown, the semiconductor packaging device 200 of this application includes: a redistribution layer 11, an electronic component 12 disposed on the redistribution layer 11, and a rigid reinforcement structure 13 disposed on the redistribution layer 11 and located on the side of the electronic component 12.

[0064] refer to Figure 6 and Figure 7 , Figure 6 This is a side view of a rigid reinforcement structure 13 according to an embodiment of this application. Figure 7This is a three-dimensional structural schematic diagram of a rigid reinforcement structure 13 according to an embodiment of this application. (In conjunction with...) Figures 4 to 7 As shown, the rigid reinforcing structure 13 is located on the side of the electronic component. The rigid reinforcing structure 13 and the electronic component 12 do not overlap in the vertical direction, and the rigid reinforcing structure 13 has a laterally arranged hole 131.

[0065] Here, the redistribution layer 11 can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies; this application does not specifically limit this. For example, it can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, prepreg (PrePreg, PP, or semi-cured resin, semi-cured sheet), Ajinomoto build-up film (ABF), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0066] Here, electronic component 12 can be various types of bare dies. For example, it can include logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, bare die or chip-scale packages, interposers, or combinations thereof. This application does not specifically limit it in this regard. For example, electronic component 12 can include application-specific integrated circuit (ASIC) and dynamic random access memory (DRMA) chips.

[0067] Here, the rigid reinforcement structure 13 can be made of metal, ceramic, glass, or polymer materials. The function of the rigid reinforcement structure is to enhance the rigidity of the structure and control the degree of warpage of the redistribution layer 11. Here, the rigid reinforcement structure 13 and the electronic component 12 do not overlap in the vertical direction; it can be understood that there is no rigid reinforcement structure 13 above the electronic component 12.

[0068] In some alternative embodiments, the rigid reinforcement structure 13 is a one-piece structure. A one-piece structure simplifies the manufacturing process, avoids the fragility issues at the joints of split structures, and provides better rigidity and warping suppression compared to split structures.

[0069] In some alternative implementations, such as Figure 6 and Figure 7 As shown, the hole 131 extends to the lower surface of the rigid reinforcing structure 13. That is, the hole 131 is an open opening, or a recessed notch extending upward from the lower surface of the rigid reinforcing structure 13. This type of hole 131 is more conducive to the passage of mold flow, which can ensure the smooth progress of the molding process.

[0070] In some alternative implementations, such as Figure 4 and Figure 7 As shown, in a top-down view, the rigid reinforcement structure 13 is square and hollow, surrounding the electronic component 12. This more comprehensively suppresses package warpage.

[0071] In some alternative implementations, such as Figure 6 and Figure 7 As shown, the rigid reinforcing structure 13 has holes 131 on all four sides; for example, each side has one hole 131. This ensures that mold flow can pass smoothly in any direction.

[0072] refer to Figure 8 , Figure 8 This is a side view schematic diagram of the rigid reinforcement structure 13 according to another embodiment of this application. Figure 8 As shown, in some optional embodiments, the hole 131 has a predetermined distance from both the upper and lower surfaces of the rigid reinforcing structure 13. That is, the hole 131 is a closed opening. This type of hole 131 is more conducive to maintaining the rigidity of the rigid reinforcing structure 13 and enhancing the effect of suppressing warping.

[0073] refer to Figure 9 , Figure 9 This is a side view schematic diagram of the rigid reinforcement structure 13 according to another embodiment of this application. Figure 9 As shown, in some alternative embodiments, the rigid reinforcing structure 13 may have more holes 131. For example, each side of the rigid reinforcing structure 13 has three holes 131.

[0074] In other alternative embodiments, the holes 131 may take other forms, shapes or numbers, which are not limited herein.

[0075] Continue to refer to Figure 5 In some alternative implementations, the sides of the redistribution layer 11 are substantially flush with the sides of the rigid reinforcement structure 13.

[0076] In some alternative embodiments, the semiconductor packaging device 200 further includes a molding layer 14 disposed on the redistribution layer 11 and covering the electronic component 12.

[0077] Here, the molding layer 14 can be formed from various molding compounds. Exemplary molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. Exemplary molding layer 14 may specifically be an epoxy molding compound (EMC).

[0078] In some alternative embodiments, the sides of the rigid reinforcement structure 13 are exposed outside the molding layer 14. In this way, the rigid reinforcement structure 13 is located as close as possible to the edge region of the entire packaging device, avoiding the central placement space as much as possible, leaving sufficient space for the placement of electronic components 12.

[0079] In some alternative embodiments, the sealing layer 14 fills the holes 131. This more firmly locks the rigid reinforcement structure 13 in place, improving the connection strength.

[0080] In some alternative embodiments, the upper surface of the electronic component 12 is substantially flush with the upper surface of the molding layer 14.

[0081] In some alternative embodiments, the upper surface of the rigid reinforcement structure 13 is substantially flush with the upper surface of the molding layer 14.

[0082] In some alternative embodiments, the rigid reinforcement structure 13 does not contact the electronic component 12. A gap exists between the rigid reinforcement structure 13 and the electronic component 12. This avoids interference between the components.

[0083] In some alternative implementations, when the rigid reinforcing structure 13 is metal, it can serve as an electromagnetic shield to prevent electromagnetic interference.

[0084] In some alternative implementations, when the rigid reinforcement structure 13 is metal, it can be electrically connected to the ground wire in the redistribution layer 11 to further enhance the electromagnetic shielding effect, improve electrical performance, and improve heat dissipation performance.

[0085] Next, refer to Figure 10 , Figure 10 This is a top view schematic diagram of a panel-type encapsulation structure according to this application. For example... Figure 10 As shown, in actual manufacturing processes, panel-level technology can be used to manufacture the semiconductor packaging device 200 of this application. In this case, multiple semiconductor packaging devices 200 are arrayed on a panel 17, thereby improving process efficiency. Optionally, the rigid reinforcing structure 13 of all semiconductor packaging devices 200 on the panel 17 can be a single-piece structure, thereby enhancing the effect of suppressing warpage. Optionally, in a subsequent unitization operation step, the panel 17 and its rigid reinforcing structure 13 can be cut apart to form a single semiconductor packaging device 200. For example, the size of the panel 17 can be 300mm*300mm or larger.

[0086] refer to Figure 11 , Figure 11 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 300 according to another embodiment of this application. Figure 11 The semiconductor packaging device 300 shown is similar to Figure 5 The semiconductor packaging device 200 shown differs in that:

[0087] The semiconductor packaging device 300 further includes an electrical connector 15 disposed on the lower surface of the redistribution layer 11 and electrically connected to the electronic component 12 through the redistribution layer 11.

[0088] Here, electrical connector 15 includes, but is not limited to, solder balls, such as solder balls made of tin (i.e., solder balls).

[0089] Here, the electrical connector 15 is configured to connect to an external device.

[0090] refer to Figure 12 , Figure 12 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 400 according to another embodiment of this application. Figure 12 The semiconductor packaging device 400 shown is similar to Figure 5 The semiconductor packaging device 200 shown differs in that:

[0091] In the semiconductor packaging device 400, the molding layer 14 covers the upper surface of the rigid reinforcing structure 13. This improves the connection strength and better secures the rigid reinforcing structure 13.

[0092] refer to Figures 13 to 14 , Figures 13 to 14 This is a schematic diagram illustrating the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application. Figures 13 to 14 As shown, the manufacturing process of the semiconductor packaging device of this application may include the following steps:

[0093] Step S1: Fabricate a redistribution layer 11 on a carrier plate 16, which can be a glass substrate.

[0094] Step S2: Place the electronic component 12 above the redistribution layer 11.

[0095] Step S3: Set a rigid reinforcement structure 13 on the redistribution layer 11.

[0096] Step S4: Perform molding to form a molding layer 14 covering the electronic component 12.

[0097] Step S5: Perform grinding to thin the molding layer 14. For example, after thinning, the electronic component 12 and the rigid reinforcement structure 13 are exposed in the molding layer 14.

[0098] Step S6: Debond the substrate and remove the carrier plate 16.

[0099] Step S7: Perform ball planting and install electrical connectors 15 below the redistribution layer 11.

[0100] Step S8: Monomerize the semiconductor by cutting the redistribution layer 11 and the rigid reinforcement structure 13 in the middle to obtain a single semiconductor package device.

[0101] Here, after removing the carrier plate 16 in step S6, the rigid reinforcement structure 13 enhances rigidity and can suppress warping of the redistribution layer 11. For example, the warping dimension after removing the carrier plate 16 can now be reduced by more than 60% compared to the prior art, for example, from 4.2 mm to 1.6 mm.

[0102] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A semiconductor packaging device, characterized in that, include: Rewire layer; Electronic components are disposed on the redistribution layer; A rigid reinforcement structure is disposed on the redistribution layer, located on the side of the electronic component. The rigid reinforcement structure has laterally disposed holes, and the rigid reinforcement structure and the electronic component do not overlap in the vertical direction.

2. The semiconductor packaging apparatus according to claim 1, characterized in that, The rigid reinforcement structure is an integral structure.

3. The semiconductor packaging apparatus according to claim 1, characterized in that, The hole extends to the lower surface of the rigid reinforcement structure.

4. The semiconductor packaging apparatus according to claim 1, characterized in that, The hole is at a predetermined distance from both the upper and lower surfaces of the rigid reinforcement structure.

5. The semiconductor packaging apparatus according to claim 1, characterized in that, Viewed from above, the rigid reinforcement structure is square and surrounds the electronic component.

6. The semiconductor packaging apparatus according to claim 5, characterized in that, The rigid reinforcement structure has holes on all four sides.

7. The semiconductor packaging apparatus according to claim 3, characterized in that, The side surface of the redistribution layer is substantially flush with the side surface of the rigid reinforcement structure.

8. The semiconductor packaging apparatus according to claim 1, characterized in that, The semiconductor packaging device further includes: a molding layer disposed on the redistribution layer, covering the electronic component.

9. The semiconductor packaging apparatus according to claim 8, characterized in that, The side of the rigid reinforcement structure is exposed in the molding layer.

10. The semiconductor packaging apparatus according to claim 8, characterized in that, The sealing layer fills the holes.

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