Electronic package and its carrier module and electronic component
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-07-23
- Publication Date
- 2026-08-07
AI Technical Summary
[0004]然而，请配合参阅图2，当第二半导体芯片17接置至布线层16时，因设于第二半导体芯片17下方的第三导电凸块13、位于第一半导体芯片10上方的第一导电凸块11以及位于第一半导体芯片10下方的第二导电块12三者产生叠影，导致多种导电凸块尺寸未有固定辨识位置，判别不易，影响定位精度，造成第二半导体芯片17接合偏移或错接等问题
[0020]前述的电子封装件及其承载模组与电子元件中，该第一定位凸块及该第二定位凸块的平面尺寸为该导电凸块、该导电体及该导电件的平面尺寸中的最小者。
Smart Images
Figure CN224611287U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor structure, and more particularly to an electronic package and its carrier module and electronic components. Background Technology
[0002] High-performance computing (HPC) technology is becoming increasingly important and widespread in modern life, for example in medical technology development such as cancer drug development, or in the automatic sensing and detection computing of autonomous vehicles. Devices used in these fields often employ fan-out package (FO PKG) structures. To address this, the industry has developed numerous advanced process packaging technologies, such as Fan-Out Multi-Chip Module (FOMCM) and Fan-Out Embedded Bridge Die (FOEB), to meet design requirements such as multi-chip functionality, high line count, large fan-out size, and high heat dissipation.
[0003] Figure 1 A conventional fan-out embedded bridging structure is fabricated by providing a first semiconductor chip 10 having opposing first and second sides. The first side has a plurality of first conductive bumps 11, and the second side has a plurality of second conductive bumps 12. A circuit layer 141 and a plurality of conductive pillars 142 are also provided, and the first semiconductor chip 10 is attached to the circuit layer 141 via the plurality of second conductive bumps 12. Next, a cover layer 15 is formed covering the first semiconductor chip 10 and the conductive pillars 142. Then, a wiring layer 16 is formed on the cover layer 15. Subsequently, a plurality of second semiconductor chips 17 are attached to the wiring layer 16 via a plurality of third conductive bumps 13. Finally, a package layer 18 is used to cover the second semiconductor chips 17.
[0004] However, please refer to the following: Figure 2 When the second semiconductor chip 17 is attached to the wiring layer 16, the third conductive bump 13 located below the second semiconductor chip 17, the first conductive bump 11 located above the first semiconductor chip 10, and the second conductive bump 12 located below the first semiconductor chip 10 overlap, resulting in multiple conductive bump sizes not having fixed identification positions, making identification difficult, affecting positioning accuracy, and causing problems such as the second semiconductor chip 17 being misaligned or incorrectly connected.
[0005] Therefore, how to overcome the various shortcomings of existing technologies is a technical problem that all sectors urgently need to solve. Utility Model Content
[0006] In view of the deficiencies in the prior art, this application provides an electronic package, including: a carrier module having a plurality of first positioning bumps, and comprising: a circuit structure; a semiconductor element disposed on the circuit structure and having opposing first and second surfaces, wherein the first surface has a plurality of conductors, the second surface has a plurality of conductive bumps, and the semiconductor element is attached to and electrically connected to the circuit structure via the plurality of conductive bumps; and a wiring structure disposed on the semiconductor element and electrically connected to the plurality of conductors of the semiconductor element; and an electronic element disposed on and electrically connected to the carrier module, wherein the electronic element has opposing active and non-active surfaces, the active surface having a plurality of conductive elements and a plurality of second positioning bumps, such that the electronic element is correspondingly attached to the plurality of first positioning bumps of the carrier module via the plurality of second positioning bumps, and the plurality of conductive elements are correspondingly attached to and electrically connected to the wiring structure of the carrier module, and the conductive bumps, the first and second positioning bumps do not have conductive bumps, conductors, or conductive elements at their vertical projections.
[0007] This application also provides a carrier module for which electronic components are mounted on a plurality of first positioning bumps with a plurality of second positioning bumps and electrically connected to the carrier module through a plurality of conductive elements, comprising: a circuit structure; a semiconductor element disposed on the circuit structure and having opposing first and second surfaces, wherein the first surface is provided with a plurality of conductors, the second surface is provided with a plurality of conductive bumps, and the semiconductor element is mounted on the circuit structure with the plurality of conductive bumps and electrically connected to the circuit structure; and a wiring structure disposed on the semiconductor element and electrically connected to the plurality of conductors of the semiconductor element, wherein the first positioning bumps do not have conductive bumps, conductors, or conductive elements at their vertical projection.
[0008] This application also provides an electronic component, which is mounted on a carrier module having a plurality of first positioning bumps, including: an active surface having a plurality of conductive elements and a plurality of second positioning bumps, such that the electronic component is mounted on the plurality of first positioning bumps of the carrier module with the plurality of second positioning bumps corresponding to each other, and the plurality of conductive elements are correspondingly mounted and electrically connected to the carrier module, and the conductive elements are not provided at the vertical projection of the first positioning bumps and the second positioning bumps.
[0009] In the aforementioned electronic package and its carrier module and electronic components, the circuit structure has a first side and a second side, the first side being used to carry the semiconductor element, and the second side being used to embed a plurality of conductive elements.
[0010] In the aforementioned electronic packaging components and their carrier modules and electronic components, the semiconductor component is a semiconductor chip or an interposer.
[0011] In the aforementioned electronic package and its carrier module and electronic components, the semiconductor element has a plurality of conductive vias connecting the first surface and the second surface, so that the plurality of conductors are electrically connected to the plurality of conductive bumps through the plurality of conductive vias.
[0012] In the aforementioned electronic package and its carrier module and electronic component, the carrier module further includes a covering layer formed on the circuit structure and covering the semiconductor component.
[0013] In the aforementioned electronic package and its carrier module and electronic components, the plurality of first positioning bumps are disposed on the covering layer.
[0014] In the aforementioned electronic package and its carrier module and electronic components, the wiring structure defines a conductive connection area and a peripheral area located around the conductive connection area, and the plurality of first positioning bumps are located in the peripheral area.
[0015] In the aforementioned electronic package and its carrier module and electronic components, the plurality of first positioning bumps are formed at the corners of the peripheral area.
[0016] In the aforementioned electronic package and its carrier module and electronic components, the plurality of first positioning bumps are metal bumps without electrical function and are manufactured together with the wiring structure.
[0017] In the aforementioned electronic package and its carrier module and electronic component, the active surface of the electronic component defines an electrical action area and a non-electrical action area located around the electrical action area. The electrical action area is provided with the plurality of conductive elements, and the non-electrical action area is provided with the plurality of second positioning bumps.
[0018] In the aforementioned electronic package and its carrier module and electronic component, the plurality of second positioning bumps are non-electrical metal bumps and are manufactured together with the plurality of conductive parts of the electronic component.
[0019] In the aforementioned electronic package and its carrier module and electronic components, the planar dimensions of the first positioning bump and the second positioning bump are different from the planar dimensions of the conductive bump, the conductor and the conductive element.
[0020] In the aforementioned electronic package and its carrier module and electronic components, the planar dimensions of the first positioning bump and the second positioning bump are the smallest among the planar dimensions of the conductive bump, the conductor and the conductive element.
[0021] The aforementioned electronic package and its carrier module and electronic component also include a packaging layer covering the electronic component.
[0022] As can be seen from the above, the electronic package and its carrier module and electronic components of this application mainly have multiple first positioning bumps (to avoid structural superposition) on the periphery of the carrier module (including circuit structure, semiconductor element, cladding layer and wiring structure), that is, at the location where there are no conductive bumps, conductors or conductive elements in the vertical projection position. Multiple second positioning bumps are also provided on the periphery (non-electrical action area) of the active surface of the electronic component. The planar dimensions of the first and second positioning bumps can be different from the planar dimensions of the conductive bumps, conductors or conductive elements (e.g., the smallest one), so that the electronic component can be positioned on the multiple first positioning bumps of the carrier module through the multiple second positioning bumps, improving positioning accuracy. Furthermore, the multiple second positioning bumps on the electronic component and the multiple first positioning bumps on the carrier module are both fabricated simultaneously during the circuit formation process in the electronic component and carrier module manufacturing process, without adding any process steps. Attached Figure Description
[0023] Figure 1 This is a cross-sectional schematic diagram of an existing fan-out packaging structure.
[0024] Figure 2 This is a partial planar schematic diagram of an existing fan-out package structure.
[0025] Figure 3 This is a cross-sectional schematic diagram of the electronic package and its carrier module and electronic components of this application.
[0026] Figure 4 This is a perspective plan view of the load-bearing module of this application.
[0027] Figure 5 This is a cross-sectional schematic diagram of the second embodiment of the electronic package of this application.
[0028] Explanation of reference numerals in the attached figures
[0029] 10 First Semiconductor Chip
[0030] 11 First conductive bump
[0031] 12 Second conductive bump
[0032] 13 Third conductive bump
[0033] 141 Line Layer
[0034] 142 conductive pillars
[0035] 15 Coating Layers
[0036] 16 Wiring Layer
[0037] 17 Second Semiconductor Chip
[0038] 18 Encapsulation Layer
[0039] 2. Bearing Module
[0040] 2a First positioning bump
[0041] 21. Circuit Structure
[0042] 211 First side
[0043] 212 Second side
[0044] 213 Conductive Components
[0045] 22 Semiconductor Components
[0046] 221 First Surface
[0047] 222 Second Surface
[0048] 223 Conductor
[0049] 224 Conductive bumps
[0050] 225 conductive via
[0051] 23 Wiring Structure
[0052] 231 Conductive connection region
[0053] 232 Outer Zone
[0054] 24 Coating Layers
[0055] 3 Electronic components
[0056] 3a Second positioning bump
[0057] 30 encapsulation layers
[0058] 31. Active side
[0059] 311 Electrical Action Zone
[0060] 312 Non-electrical action zone
[0061] 313 Conductive components
[0062] 32 Non-active surfaces
[0063] 4. Electronic packaging components. Detailed Implementation
[0064] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0065] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0066] Please see Figure 3 This is a cross-sectional schematic diagram of the electronic package and its carrier module and electronic components of this application. The electronic package 4 of this application includes a carrier module 2 and an electronic component 3 disposed on and electrically connected to the carrier module 2.
[0067] The carrier module 2 includes a circuit structure 21, a semiconductor element 22 disposed on the circuit structure 21, and a wiring structure 23 disposed on the semiconductor element 22.
[0068] The circuit structure 21 has a first side 211 and a second side 212. The first side 211 of the circuit structure 21 is used to carry the semiconductor element 22, and the second side 212 of the circuit structure 21 is used to embed a plurality of conductive elements 213 (such as solder balls) for subsequent connection to an external device (such as a circuit board) through the plurality of conductive elements 213.
[0069] The circuit structure 21 may be a substrate with or without a core layer, comprising multiple dielectric layers and multiple redistribution layers (RDLs) disposed on the dielectric layers. Alternatively, the circuit structure 21 may consist of only a single dielectric layer and a single redistribution layer. Furthermore, the material forming the redistribution layer is copper, and the material forming the dielectric layer is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0070] The semiconductor element 22 is, for example, a semiconductor chip or an interposer, having opposing first surfaces 221 and second surfaces 222. The first surface 221 has a plurality of conductors 223, and the second surface 222 has a plurality of conductive bumps 224. The semiconductor element 22 is attached to and electrically connected to the circuit structure 21 via the second surface 222 and the plurality of conductive bumps 224. The illustrations of this embodiment show a plurality of semiconductor elements 22 attached to the circuit structure 21. The plurality of conductors 223 and the plurality of conductive bumps 224 are spherical, such as solder balls, or columnar, such as copper pillars or solder bumps, or nail-shaped, made by a wire bonding machine.
[0071] The semiconductor element 22 may also have a plurality of conductive vias 225 connecting the first surface 221 and the second surface 222, so that the plurality of conductors 223 can be electrically connected to the plurality of conductive bumps 224 through the plurality of conductive vias 225.
[0072] The carrier module 2 may also include a covering layer 24 formed on the circuit structure 21 and covering the semiconductor element 22. The covering layer 24 may be, for example, an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin.
[0073] The wiring structure 23 is formed on the cladding layer 24 and electrically connects the plurality of conductors 223 of the semiconductor element 22. The wiring structure 23 includes a plurality of dielectric layers and a plurality of redistribution layers (RDLs) disposed on the dielectric layers. Alternatively, the wiring structure 23 may include only a single dielectric layer and a single redistribution layer. Furthermore, the material forming the redistribution layer is copper, and the material forming the dielectric layer is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0074] In this embodiment, the wiring structure 23 defines a conductive connection area 231 and a peripheral area 232 surrounding the conductive connection area 231. The peripheral area 232 is provided with a plurality of first positioning bumps 2a. The first positioning bumps 2a are non-electrical metal bumps and can be fabricated together with the wiring redistribution layer of the wiring structure 23.
[0075] Please refer to the following at the same time. Figure 4This is a perspective plan view of the carrier module 2 of this application. The first positioning bump 2a can be formed, for example, diagonally outside the conductive connection area 231, that is, at the corner of the peripheral area 232, to avoid overlapping with other components.
[0076] The electronic component 3 has an active surface 31 and a non-active surface 32. The active surface 31 of the electronic component 3 defines an electrically active region 311 and a non-electrically active region 312 located around the electrically active region 311. The electrically active region 311 is provided with a plurality of conductive elements 313, and the non-electrically active region 312 is provided with a plurality of second positioning bumps 3a. The plurality of conductive elements 313 are spherical, such as solder balls, or columnar, such as copper pillars, solder bumps, or nail-shaped, made by a wire bonding machine. The electrically active region 311 and the non-electrically active region 312 of the electronic component 3 correspond to the conductive connection region 231 and the peripheral region 232 of the wiring structure 23, respectively.
[0077] The electronic component 3 has multiple second positioning bumps 3a on the non-electrical functional area 312 correspondingly placed on the first positioning bump 2a of the carrier module 2. At this time, the multiple conductive elements 313 are correspondingly placed on the conductive connection area 231 and electrically connected to the wiring structure 23. The second positioning bumps 3a are non-electrical metal bumps and can be manufactured together with the conductive elements 313 of the electronic component 3.
[0078] The first positioning protrusion 2a and the second positioning protrusion 3a do not have the conductive protrusion 224, the conductor 223, or the conductive element 313 at their vertical projection locations to improve positioning accuracy. Furthermore, the planar dimensions of the first positioning protrusion 2a and the second positioning protrusion 3a differ from the planar dimensions of the conductive protrusion 224, the conductor 223, and the conductive element 313 for easier identification. Preferably, the planar dimensions of the first positioning protrusion 2a and the second positioning protrusion 3a are the smallest among the planar dimensions of the conductive protrusion 224, the conductor 223, and the conductive element 313.
[0079] In one embodiment, the electronic component 3 is, for example, a semiconductor chip such as a graphics processing unit (GPU) or a high-bandwidth memory (HBM).
[0080] A further encapsulation layer 30 can be formed, for example, by molding, to cover the plurality of electronic components 3. Furthermore, the encapsulation layer 30 is an insulating material, such as polyimide (PI), dry film, an encapsulating colloid or molding compound such as epoxy resin, which can be formed on the circuit structure 21 by lamination or molding. It should be understood that the material forming the encapsulation layer 30 may be the same as or different from the material of the covering layer 24.
[0081] Please refer to the following: Figure 5 This is a cross-sectional schematic diagram of the second embodiment of the electronic package 4 of this application, wherein a plurality of first positioning bumps 2a may be disposed on the covering layer 24, so that the electronic component 3 is correspondingly connected to the plurality of first positioning bumps 2a on the covering layer 24 by a plurality of second positioning bumps 3a, and at the same time, the plurality of conductive elements 313 are correspondingly connected to and electrically connected to the wiring structure 23.
[0082] Therefore, the electronic package, its carrier module, and electronic components of this application mainly feature multiple first positioning bumps (to avoid structural superposition) on the periphery of the carrier module's (including circuit structure, semiconductor element, cladding layer, and wiring structure) cladding layer and / or wiring structure, i.e., at locations where no conductive bumps, conductors, or conductive elements are provided in the vertical projection position. Furthermore, multiple second positioning bumps are provided on the periphery of the active surface of the electronic component (non-electrical action area). The planar dimensions of the first and second positioning bumps can be different from the planar dimensions of the conductive bumps, conductors, or conductive elements (e.g., the smallest of them), allowing the electronic component to be positioned on the multiple first positioning bumps of the carrier module via the multiple second positioning bumps, thus improving positioning accuracy. In addition, the multiple second positioning bumps on the electronic component and the multiple first positioning bumps on the carrier module are both fabricated simultaneously during the circuit formation process in the electronic component and carrier module manufacturing process, without adding any process steps. Furthermore, the aforementioned structure does not require the addition of new development processes and materials or the purchase of equipment. Existing materials, processes, and equipment can solve existing technical problems in the industry, so there will be no large additional cost expenditures.
[0083] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: The support module is provided with multiple first positioning protrusions and includes: Line structure; A semiconductor element is disposed on the circuit structure and has opposing first and second surfaces, wherein the first surface has a plurality of conductors, and the second surface has a plurality of conductive bumps, and the semiconductor element is disposed on the circuit structure and electrically connected to the circuit structure via the plurality of conductive bumps; and A wiring structure, comprising the plurality of conductors disposed on the semiconductor element and electrically connected to the semiconductor element; and An electronic component is disposed on and electrically connected to the carrier module. The electronic component has an active surface and a non-active surface. The active surface is provided with a plurality of conductive elements and a plurality of second positioning bumps, so that the electronic component is correspondingly placed on the plurality of first positioning bumps of the carrier module with the plurality of second positioning bumps, and the plurality of conductive elements are correspondingly placed and electrically connected to the wiring structure of the carrier module. The conductive bumps, conductors or conductive elements are not provided at the vertical projection of the first positioning bumps and the second positioning bumps.
2. The electronic package as described in claim 1, characterized in that, The circuit structure has a first side and a second side, the first side being used to carry the semiconductor element and the second side being used to mount a plurality of conductive elements.
3. The electronic package as described in claim 1, characterized in that, The semiconductor component is a semiconductor chip or an interposer.
4. The electronic package as described in claim 1, characterized in that, The semiconductor element has a plurality of conductive vias connecting the first surface and the second surface, so that the plurality of conductors are electrically connected to the plurality of conductive bumps through the plurality of conductive vias.
5. The electronic package as described in claim 1, characterized in that, The carrier module also includes a cladding layer formed on the circuit structure and covering the semiconductor element.
6. The electronic package as described in claim 5, characterized in that, The plurality of first positioning bumps are provided on the covering layer.
7. The electronic package as claimed in claim 1, characterized in that, The wiring structure defines a conductive connection area and a peripheral area located around the conductive connection area, and the plurality of first positioning bumps are located in the peripheral area.
8. The electronic package as described in claim 7, characterized in that, The multiple first positioning bumps are formed at the corners of the peripheral area.
9. The electronic package as claimed in claim 1, characterized in that, The plurality of first positioning bumps are non-electrical metal bumps and are fabricated together with the wiring structure.
10. The electronic package as claimed in claim 1, characterized in that, The active surface of the electronic component is defined with an electrical action area and a non-electrical action area located around the electrical action area. The electrical action area is provided with the plurality of conductive elements, and the non-electrical action area is provided with the plurality of second positioning bumps.
11. The electronic package as claimed in claim 1, characterized in that, The plurality of second positioning bumps are non-electrically functional metal bumps and are manufactured together with the plurality of conductive parts of the electronic component.
12. The electronic package as claimed in claim 1, characterized in that, The planar dimensions of the first positioning bump and the second positioning bump are different from the planar dimensions of the conductive bump, the conductor, and the conductive component.
13. The electronic package as claimed in claim 1, characterized in that, The planar dimensions of the first positioning bump and the second positioning bump are the smallest among the planar dimensions of the conductive bump, the conductor, and the conductive component.
14. The electronic package as claimed in claim 1, characterized in that, The electronic package also includes a packaging layer that covers the electronic component.
15. A carrier module, comprising a plurality of first positioning bumps, for electronic components to be mounted on the plurality of first positioning bumps by a plurality of second positioning bumps and electrically connected to the carrier module via a plurality of conductive elements, characterized in that, include: Line structure; A semiconductor element is disposed on the circuit structure and has opposing first and second surfaces, wherein the first surface is provided with a plurality of conductors, the second surface is provided with a plurality of conductive bumps, and the semiconductor element is disposed on the circuit structure and electrically connected to the circuit structure via the plurality of conductive bumps. as well as The wiring structure is provided on the semiconductor element and electrically connected to the plurality of conductors of the semiconductor element, and the conductive bump, the conductor or the conductive element is not provided at the vertical projection of the first positioning bump.
16. The load-bearing module as described in claim 15, characterized in that, The circuit structure has a first side and a second side, the first side being used to carry the semiconductor element and the second side being used to mount a plurality of conductive elements.
17. The load-bearing module as described in claim 15, characterized in that, The semiconductor component is a semiconductor chip or an interposer.
18. The load-bearing module as described in claim 15, characterized in that, The semiconductor element has a plurality of conductive vias connecting the first surface and the second surface, so that the plurality of conductors are electrically connected to the plurality of conductive bumps through the plurality of conductive vias.
19. The load-bearing module as described in claim 15, characterized in that, The carrier module also includes a cladding layer formed on the circuit structure and covering the semiconductor element.
20. The load-bearing module as described in claim 19, characterized in that, The plurality of first positioning bumps are provided on the covering layer.
21. The load-bearing module as described in claim 15, characterized in that, The wiring structure defines a conductive connection area and a peripheral area located around the conductive connection area, and the plurality of first positioning bumps are located in the peripheral area.
22. The load-bearing module as described in claim 21, characterized in that, The multiple first positioning bumps are formed at the corners of the peripheral area.
23. The load-bearing module as described in claim 15, characterized in that, The plurality of first positioning bumps are non-electrical metal bumps and are fabricated together with the wiring structure.
24. The load-bearing module as described in claim 15, characterized in that, The active surface of the electronic component is defined with an electrical action area and a non-electrical action area located around the electrical action area. The electrical action area is provided with a plurality of conductive elements, and the non-electrical action area is provided with a plurality of second positioning bumps.
25. The load-bearing module as described in claim 24, characterized in that, The plurality of second positioning bumps are non-electrically functional metal bumps and are manufactured together with the plurality of conductive parts of the electronic component.
26. The load-bearing module as described in claim 24, characterized in that, The planar dimensions of the first positioning bump and the second positioning bump are different from the planar dimensions of the conductive bump, the conductor, and the conductive component.
27. The load-bearing module as described in claim 24, characterized in that, The planar dimensions of the first positioning bump and the second positioning bump are the smallest among the planar dimensions of the conductive bump, the conductor, and the conductive component.
28. An electronic component, mounted on a support module having a plurality of first positioning protrusions, characterized in that, include: The active surface is provided with multiple conductive elements and multiple second positioning bumps, so that the electronic component is correspondingly placed on the multiple first positioning bumps of the carrier module with the multiple second positioning bumps, and the multiple conductive elements are correspondingly placed and electrically connected to the carrier module, and the conductive elements are not provided at the vertical projection of the first positioning bumps and the second positioning bumps.
29. The electronic component as claimed in claim 28, characterized in that, The active surface is defined with an electrical action area and a non-electrical action area located around the electrical action area. The electrical action area is provided with the plurality of conductive elements, and the non-electrical action area is provided with the plurality of second positioning protrusions.
30. The electronic component as claimed in claim 28, characterized in that, The plurality of second positioning bumps are non-electrically functional metal bumps and are manufactured together with the plurality of conductive parts of the electronic component.
31. The electronic component as claimed in claim 28, characterized in that, The planar dimensions of the first positioning bump and the second positioning bump are different from the planar dimensions of the conductive component.