A dynamic testing system for a semiconductor power device

Abstract

This utility model discloses a dynamic testing system for semiconductor power devices, relating to the field of power device testing technology. The dynamic testing system includes a power supply module, an overcurrent detection module, and a current switch connected in series, as well as a main control module, a first gate driver, a second gate driver, and a gate voltage adjustment module. The first gate driver receives a first control signal from the main control module and outputs a first gate drive signal based on the first control signal. The gate voltage adjustment module receives the first gate drive signal and drives the current switch based on the first gate drive signal; it also receives a voltage setting signal from the main control module and controls the gate voltage of the current switch based on the voltage setting signal. Using the above technical solution, the output current of the short-circuit current testing system can be clamped for protection, effectively reducing the peak current when the power device under test is damaged, and avoiding damage to the short-circuit current testing system and application-side test fixtures and other equipment.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor power device testing technology, and in particular to a dynamic testing system for semiconductor power devices. Background Technology

[0002] Insulated-Gate Bipolar Transistors (IGBTs) and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are core components in power processing, primarily used for power conversion and circuit control in power equipment. They serve as a bridge between low-voltage control and high-voltage operation, mainly performing frequency conversion, voltage transformation, current conversion, power amplification, and power management, playing a crucial role in the normal operation of equipment. As the application scenarios of power devices expand, the operating conditions they face become increasingly complex, potentially encountering challenges such as overcurrent and even more extreme short circuits. The short-circuit withstand capability of these devices directly determines the design for fault protection and failure prevention; therefore, performance testing is essential and crucial.

[0003] Existing dynamic testing systems for IGBTs and MOSFETs have certain drawbacks. When the power device under test (DUT) fails, it cannot effectively limit the actual output current. The energy accumulated on the DUT and the test fixture is large, which can lead to burnout of the test fixture or even damage to the testing system. When the DUT fails, it is usually necessary to reduce the gate voltage of the main current switch in the dynamic testing system to limit the output current. However, existing gate drivers have undervoltage protection, which prevents the gate voltage of the main current switch from falling below the undervoltage protection value of the gate driver. This limits the ability of the main current switch to limit the output current, resulting in a significant risk of damage to the testing system and test fixture.

[0004] Therefore, how to limit the output current of the test system and protect the test system and application-side test fixtures and other equipment has become an urgent technical problem to be solved. Utility Model Content

[0005] This invention provides a dynamic testing system for semiconductor power devices. Its main purpose is to limit the output current of the short-circuit current testing system, effectively reduce the peak current when the power device under test is damaged, and avoid damage to the short-circuit current testing system and application-side test fixtures and other equipment.

[0006] According to this utility model, a dynamic testing system for semiconductor power devices is provided, comprising: a main control module, a power supply module, an overcurrent detection module, a current switch, a first gate driver, a second gate driver, and a gate voltage adjustment module;

[0007] The power module, the overcurrent detection module, and the current switch are connected in series to form a test circuit with the power device under test.

[0008] The first gate driver is electrically connected to the gate of the current switch through the gate voltage adjustment module;

[0009] The second gate driver is used to connect to the gate of the power device under test;

[0010] The main control module is electrically connected to the overcurrent detection module, the first gate driver, the second gate driver, and the gate voltage adjustment module, respectively.

[0011] The first gate driver is used to receive a first control signal from the main control module and output a first gate drive signal according to the first control signal; the gate voltage adjustment module is used to receive the first gate drive signal and drive the current switch according to the first gate drive signal; the gate voltage adjustment module is also used to receive a voltage setting signal from the main control module and control the gate voltage of the current switch according to the voltage setting signal.

[0012] Optionally, the gate voltage adjustment module includes a voltage control unit and a drive control unit;

[0013] The input terminal of the voltage control unit is electrically connected to the main control module, and the output terminal of the voltage control unit is electrically connected to the first power supply terminal of the drive control unit.

[0014] The input terminal of the drive control unit is electrically connected to the first gate driver, and the output terminal of the drive control unit is electrically connected to the gate of the current switch.

[0015] Optionally, the voltage control unit includes a digital-to-analog converter circuit;

[0016] The digital input terminal of the digital-to-analog converter is electrically connected to the main control module, and the analog output terminal of the digital-to-analog converter is electrically connected to the first power supply terminal of the drive control unit.

[0017] Optionally, the voltage control unit further includes a voltage regulation circuit;

[0018] The analog output terminal of the digital-to-analog converter circuit is electrically connected to the first power supply terminal of the drive control unit through the voltage regulation circuit.

[0019] Optionally, the voltage regulation circuit includes an operational amplifier, a fifth transistor, and a first energy storage capacitor;

[0020] The first power supply terminal of the operational amplifier and the first terminal of the fifth transistor are both electrically connected to the first power supply terminal of the voltage regulation circuit, and the second power supply terminal of the operational amplifier is grounded.

[0021] The non-inverting input of the operational amplifier is electrically connected to the analog output of the digital-to-analog converter circuit; the inverting input of the operational amplifier is electrically connected to the second terminal of the fifth transistor, the first plate of the first energy storage capacitor, and the first power supply terminal of the drive control unit; the output of the operational amplifier is electrically connected to the third terminal of the fifth transistor; and the second plate of the first energy storage capacitor is grounded.

[0022] Optionally, the drive control unit includes a dead-time generation circuit and a power drive circuit;

[0023] The input terminal of the dead-time generation circuit is electrically connected to the drive output terminal of the first gate driver, the first output terminal of the dead-time generation circuit is electrically connected to the first input terminal of the power drive circuit, the second output terminal of the dead-time generation circuit is electrically connected to the second input terminal of the power drive circuit, and the output terminal of the power drive circuit is electrically connected to the gate of the current switch.

[0024] The dead-time generation circuit is used to generate a first drive signal and a second drive signal with dead time according to the first gate drive signal; the power drive circuit is used to drive the current switch according to the first drive signal and the second drive signal.

[0025] Optionally, the dead-time generation circuit includes a first transistor, a third transistor, a first pull-up resistor, a second pull-up resistor, a first pull-down resistor, and a second pull-down resistor; wherein the first transistor is an N-channel MOSFET, and the third transistor is a P-channel MOSFET.

[0026] The first terminal of the first transistor is electrically connected to the first power supply terminal of the drive control unit through a first pull-up resistor; the second terminal of the first transistor is electrically connected to the first terminal of the third transistor through a first pull-down resistor and the second pull-up resistor; the second terminal of the third transistor is electrically connected to the second power supply terminal of the drive control unit through a second pull-down resistor; the gates of the first transistor and the third transistor are both electrically connected to the drive output terminal of the first gate driver.

[0027] The connection node between the first pull-down resistor and the second pull-up resistor is also electrically connected to the emitter or source of the current switch;

[0028] The power drive circuit includes a second transistor and a fourth transistor; wherein the second transistor is a P-channel MOSFET and the fourth transistor is an N-channel MOSFET.

[0029] The first terminal of the second transistor is electrically connected to the first power supply terminal of the drive control unit. The second terminal of the second transistor and the first terminal of the fourth transistor are both electrically connected to the gate of the current switch. The second terminal of the fourth transistor is electrically connected to the second power supply terminal of the drive control unit. The gate of the second transistor is electrically connected to the first terminal of the first transistor. The gate of the fourth transistor is electrically connected to the second terminal of the third transistor.

[0030] Optionally, the maximum operating current of the second transistor is greater than the maximum operating current of the first transistor and greater than the maximum operating current of the third transistor; the maximum operating current of the fourth transistor is greater than the maximum operating current of the first transistor and greater than the maximum operating current of the third transistor.

[0031] Optionally, the drive control unit further includes a first guiding diode and a second guiding diode;

[0032] The anode of the first guiding diode is electrically connected to the second electrode of the second transistor, and the cathode of the first guiding diode is electrically connected to the gate of the current switch;

[0033] The anode of the second guiding diode is electrically connected to the gate of the current switch, and the cathode of the second guiding diode is electrically connected to the first electrode of the fourth transistor.

[0034] Optionally, the drive control unit further includes a second energy storage capacitor;

[0035] The first plate of the second energy storage capacitor is electrically connected to the second power supply terminal of the drive control unit, and the second plate of the second energy storage capacitor is grounded.

[0036] The technical solution of this utility model includes a main control module, a power supply module, an overcurrent detection module, a current switch, a first gate driver, a second gate driver, and a gate voltage adjustment module. It can test the short-circuit withstand capability of the power device under test under short-circuit and overcurrent conditions. By setting the gate voltage adjustment module between the first gate driver and the gate of the current switch, the gate voltage adjustment module can flexibly adjust the gate voltage of the current switch according to the voltage setting signal output by the main control module. This overcomes the limitation of the undervoltage protection value of existing gate drivers. While ensuring that the first gate driver can drive the current switch normally, it ensures that the gate voltage of the current switch is lower than the undervoltage protection value of the gate driver. This helps to reduce the maximum voltage when the gate-emitter voltage spike occurs, limits the rapid increase of current, and achieves the purpose of clamping protection of the output current of the short-circuit current test system. This effectively reduces the peak current increase when the power device under test is damaged, avoiding damage to the short-circuit current test system and application-side test fixtures and other equipment.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices in related technologies;

[0040] Figure 2 This is a schematic diagram of the current and voltage waveforms of a dynamic testing system for a semiconductor power device in related technologies;

[0041] Figure 3 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 1 ;

[0042] Figure 4 This is a schematic diagram of the transfer characteristic curve of an IGBT provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the current and voltage waveforms of an improved dynamic testing system before and after an embodiment of this application.

[0044] Figure 6 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 2 ;

[0045] Figure 7 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 3 ;

[0046] Figure 8 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 4 ;

[0047] Figure 9 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 5 ;

[0048] Figure 10 This is a timing diagram of a gate voltage adjustment module provided in an embodiment of this application.

[0049] In this embodiment of the application, the reference numerals and their corresponding feature names are as follows:

[0050] 10-Main control module; 20-Power supply module; 30-Overcurrent detection module; 40-Gate voltage adjustment module; 410-Voltage control unit; 411-Digital / analog converter circuit; 412-Voltage regulation circuit; 420-Drive control unit; 421-Dead-time generation circuit; 422-Power drive circuit; 041-First output terminal of dead-time generation circuit; 042-First input terminal of power drive circuit; 043-Second output terminal of dead-time generation circuit; 044-Second input terminal of power drive circuit; GDU1-First gate driver; GDU2-Second gate driver; DUT-Power device under test. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] Figure 1 This is a circuit diagram of a dynamic testing system for semiconductor power devices in related technologies. As mentioned in the background section, the dynamic testing systems in related technologies have certain drawbacks, such as... Figure 1 As shown, the dynamic test system in the related technology includes a current switch T1'. The current switch T1' can be used as a main current switch. Since the gate driver (including the first gate driver GDU1' and the second gate driver GDU2') generally has an undervoltage protection function, when the supply voltage of the gate driver, i.e. the output voltage, is lower than the undervoltage protection value, the gate driver will not work (stop output voltage signal). Due to the limitation of this function, the gate positive voltage of the current switch T1' cannot be adjusted to a lower value. This restricts the current switch T1's ability to limit the output current. The current switch T1' does not have the function of dynamically adjusting the current limit. When the power device under test (DUT) is damaged, it cannot effectively limit the actual output current. An abnormally large current will be formed in the test circuit, which may lead to damage to the test fixture in severe cases.

[0054] Figure 2 This is a schematic diagram of the current and voltage waveforms of a dynamic testing system for semiconductor power devices in related technologies, such as... Figure 2In the diagram, the dashed lines represent the normal ICE (collector-emitter current) and VCE (collector-emitter voltage) waveforms of the power device under test (DUT) during dynamic testing; the solid lines represent the ICE (collector-emitter current) and VCE (collector-emitter voltage) waveforms of the current switch T1' when the DUT is damaged during dynamic testing. When the DUT is damaged during dynamic testing, dv / dt will be generated between the collector and emitter terminals of the current switch T1', and a voltage spike ΔVGE will be generated at the gate of the current switch T1'. This will increase the gate-emitter voltage of the current switch T1' to VGE + ΔVGE. The increased gate-emitter voltage of the current switch T1' will cause the output current ICE of the test system to increase to the maximum current value ICE_MAX. Figure 2 The waveforms of T1'_VGE and ICE (solid lines) are shown in the diagram. At this point, a large amount of energy accumulates on the power device under test (DUT) and the test fixture, which can severely burn out the test fixture and damage the test system. In this situation, it is necessary to adjust the gate voltage of the current switch T1' to a lower value to limit the output current. However, in related technologies, the gate driver has an undervoltage protection function. Due to this limitation, the forward gate voltage of the current switch T1' cannot be adjusted to a lower value, thus restricting the current switch's ability to limit the output current. To solve this problem, this application proposes a short-circuit current testing system for power devices. This system overcomes the limitation of the existing gate driver undervoltage protection voltage value, adjusts the forward gate voltage of the current switch to a lower value, weakens the gate-emitter voltage spike caused by dv / dt between C and E, thereby limiting the rapid increase in the output current and achieving the function of clamping protection for the output current.

[0055] Figure 3 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 1 ,refer to Figure 3The dynamic testing system includes a main control module 10, a power supply module 20, an overcurrent detection module 30, a current switch T1, a first gate driver GDU1, a second gate driver GDU2, and a gate voltage adjustment module 40. The power supply module 20, overcurrent detection module 30, and current switch T1 are connected in series to form a test circuit with the power device under test (DUT). The first gate driver GDU1 is electrically connected to the gate G of the current switch T1 through the gate voltage adjustment module 40. The second gate driver GDU2 is used to connect to the gate of the power device under test (DUT). The main control module 10 is electrically connected to the overcurrent detection module 30, the first gate driver GDU1, the second gate driver GDU2, and the gate voltage adjustment module 40. The first gate driver GDU1 is used to receive the first control signal from the main control module 10 and output the first gate drive signal according to the first control signal; the gate voltage adjustment module 40 is used to receive the first gate drive signal output by the first gate driver GDU1 and drive the current switch T1 according to the first gate drive signal; the gate voltage adjustment module 40 is also used to receive the voltage setting signal from the main control module 10 and control the gate voltage of the current switch T1 according to the voltage setting signal.

[0056] Among them, the power device under test (DUT) includes, but is not limited to, self-extinguishing arc-type semiconductor devices such as insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs); the current switch (T1) includes, but is not limited to, semiconductor switching devices such as IGBTs and MOSFETs.

[0057] The main control module 10 includes, but is not limited to, control devices such as Field Programmable Gate Array (FPGA) circuits, Advanced Reduced Instruction Set Machines (ARM), Microcontroller Units (MCUs), and Microprocessor Units (MPUs). The main control module 10 can control the first gate driver GDU1 to drive the current switch T1, control the voltage signal output by the gate voltage adjustment module 40, and control the second gate driver GDU2 to drive the power device under test (DUT). The main control module 10 can also receive overcurrent detection signals output by the overcurrent detection module 30. The power supply module 20 provides electrical signals to the test circuit of the dynamic test system, enabling current to exist in the test circuit. The overcurrent detection module 30 detects whether the current in the test circuit exceeds a preset current threshold and outputs the detection result to the main control module 10.

[0058] It is understood that the dynamic testing system for semiconductor power devices provided in this application includes, but is not limited to, the above-described structure. In other optional embodiments, the dynamic testing system for semiconductor power devices provided in this application may also include structures such as inductors and oscilloscopes. The dynamic testing system for semiconductor power devices provided in this application can be used to perform various tests such as short-circuit tests and double-pulse tests on semiconductor power devices. Technical solutions that include the above-described structure and conform to the above-described connection relationship should all fall within the scope of protection of this utility model.

[0059] Specifically, the power device under test (DUT) is connected to the test circuit using a test fixture (not shown in the figure). During testing, the main control module 10 outputs a first control signal that controls the current switch T1 to turn on, causing the first gate driver GDU1 to output a first gate drive signal according to the first control signal. The first gate drive signal is a signal that controls the current switch T1 to turn on or off. That is, according to the high or low level of the first gate drive signal, the gate voltage adjustment module 40 can control the current switch T1 to turn on or off. The first gate drive signal can be used as a logic level signal. For example, when the first gate drive signal is greater than zero, it can represent a logic level of 1, and the gate voltage adjustment module 40 can control the current switch T1 to turn on accordingly; when the first gate drive signal is less than zero, it can represent a logic level of 0, and the gate voltage adjustment module 40 can control the current switch T1 to turn off accordingly.

[0060] The gate voltage adjustment module 40 can output a gate voltage pulse to the gate G of the current switch T1 according to the first gate drive signal. The voltage value of the gate voltage pulse output by the gate voltage adjustment module 40 is related to the voltage setting signal received by the gate voltage adjustment module 40. When the voltage setting signal changes, the voltage value of the gate voltage pulse output by the gate voltage adjustment module 40 also changes accordingly. At the same time, the gate voltage adjustment module 40 can also provide a reference signal to the emitter E of the current switch T1, which is beneficial to accurately control the gate-emitter voltage VGE of the current switch T1, thereby effectively limiting the current.

[0061] In an optional implementation, the positive value of the gate voltage pulse output by the gate voltage adjustment module 40 is less than the positive value of the first gate drive signal voltage output by the first gate driver GDU1. This can overcome the undervoltage protection limit of the first gate driver GDU1, making the positive value of the gate voltage of the current switch T1 smaller (but still greater than the threshold voltage T1_Vth of the test switch T1). This limits the current value in the test circuit to a smaller range (smaller than the current in the test circuit in the prior art or related technologies, but sufficient for dynamic testing of the power device under test (DUT)). Thus, when the power device under test (DUT) is damaged, causing a voltage spike at the gate-emitter junction of the current switch T1, the smaller positive value of the gate voltage of the current switch T1 can reduce the voltage spike at the gate-emitter junction of the current switch T1 compared to the prior art or related technologies, limiting the sharp increase in the output current value. This can effectively reduce the maximum current value in the test loop and achieve the function of clamping and protecting the output current of the dynamic test system.

[0062] It is understood that the high / low logic level is related to the specific structure of the current switch T1 it controls. For example, when the current switch T1 includes a transistor and the transistor is a P-channel transistor, the logic level is low, meaning it is turned on when the gate voltage is low; while when the current switch T1 includes a transistor and the transistor is an N-channel transistor, the logic level is high, meaning it is turned on when the gate voltage is high. In the embodiments of this application, the current switch T1 can be set according to actual needs, and the logic level of the signal is not limited to high or low.

[0063] It is also understandable that high level and low level refer to the voltage used to control the transistor in the circuit to turn on or off, but are not limited to a certain fixed voltage. For example, electrical signals from +10V to +30V that can control the current switch T1 to be in the same state can all be high level, and electrical signals from -5V to -15V that can control the circuit to be in the same state can all be low level.

[0064] For example, taking the current switch T1 as an IGBT, the current switch T1 includes a gate G, an emitter E, and a collector C. Figure 4 This is a schematic diagram of the transfer characteristic curve of an IGBT provided in an embodiment of this application, showing the relationship between the collector-emitter current ICE and the gate-emitter voltage VGE of the IGBT. (Reference) Figure 4In the IGBT transfer characteristic curve, ΔVGE1 = ΔVGE2, and ΔICE1 is much smaller than ΔICE2. Based on the IGBT transfer characteristics, this embodiment of the invention adjusts the first gate drive signal, which has a large positive voltage value output by the first gate driver GDU1, to a high-level signal with a smaller voltage value below the undervoltage protection voltage value of the first gate driver GDU1 by setting the gate voltage adjustment module 40. Thus, when the DUT is damaged, even if a gate-emitter voltage spike occurs, increasing the gate-emitter voltage and collector-emitter current, the gate-emitter voltage before the voltage spike is lower than before the improvement. Superimposed with the same magnitude of voltage spike increment, the peak value of the gate-emitter voltage spike is also lower than before the improvement, which helps limit the sharp increase in collector-emitter current and reduce the maximum current value ICE_MAX. Furthermore, after the gate-emitter voltage is lowered before the voltage spike, the same magnitude of voltage spike increment reduces the current increment compared to before the improvement, further limiting the increase in collector-emitter current, thereby achieving the purpose of clamping protection for the output current.

[0065] Continuing with the example of current switch T1 being an IGBT, Figure 5 This is a schematic diagram of the current and voltage waveforms of a dynamic testing system before and after improvement, provided in an embodiment of this application. The red waveform represents the current and voltage waveforms of the improved dynamic testing system. Figure 5 As shown, the positive gate voltage pulse value T1_VGE_H1 of the improved current switch T1 is less than the positive gate voltage pulse value T1_VGE_H of the original current switch T1. The gate-emitter voltage spike VGE1+ΔVGE1 of the improved current switch T1 is also less than the gate-emitter voltage spike VGE+ΔVGE of the original current switch T1. This results in the improved maximum current value ICE_MAX1 being less than the original maximum current value ICE_MAX. The negative gate voltage pulse value T1_VGE_L1 of the improved current switch T1 can still be equal to the original negative gate voltage pulse value T1_VGE_L. The voltage adjustment range of the gate voltage adjustment module 40 can be from 0V to the voltage value of the first gate drive signal.

[0066] It should be noted that the figure only shows an example of the current switch T1 being an IGBT. In other optional embodiments, the current switch T1 can also be a MOSFET. When the current switch T1 is a P-channel MOSFET, the absolute value of the gate voltage can be reduced by increasing the negative value of the gate voltage pulse T1_VGE_L1, thereby reducing the current. The specific structure of the current switch T1 is not limited in this application embodiment, nor is the trend of the gate voltage pulse of the improved current switch T1 limited.

[0067] The dynamic testing system for semiconductor power devices provided in this application includes a main control module, a power supply module, an overcurrent detection module, a current switch, a first gate driver, a second gate driver, and a gate voltage adjustment module. It can test the short-circuit withstand capability of the power device under test under short-circuit and overcurrent conditions. By setting the gate voltage adjustment module between the gate of the first gate driver and the gate of the current switch, the gate voltage adjustment module can flexibly adjust the gate voltage of the current switch according to the voltage setting signal output by the main control module. This overcomes the limitation of the existing gate driver undervoltage protection value. While ensuring the normal operation of the first gate driver, it ensures that the gate voltage of the current switch is lower than the undervoltage protection value of the gate driver. This helps reduce the maximum voltage value when the gate-emitter voltage spike occurs, limits the rapid increase of current, and achieves the purpose of clamping protection for the output current of the dynamic testing system. This effectively reduces the peak current when the power device under test is damaged, avoiding damage to the dynamic testing system and application-side test fixtures and other equipment.

[0068] For ease of description, unless otherwise specified, the embodiments of this application all take the current switch T1 as an IGBT, and the gate voltage pulse positive value T1_VGE_H1 of the improved current switch T1 is less than the gate voltage pulse positive value T1_VGE_H of the unimproved current switch T1 as an example to illustrate the technical solution of the embodiments of this application.

[0069] Based on the above implementation, taking both the current switch T1 and the power device under test (DUT) as IGBTs as an example, the gate voltage adjustment module 40 can also be electrically connected to the emitter E of the current switch T1, thereby controlling the gate-emitter voltage VGE and the collector-emitter current ICE of the current switch T1; the second gate driver GDU2 can also be used to connect to the emitter of the power device under test (DUT), thereby driving the power device under test (DUT).

[0070] In other alternative implementations, the emitter of the current switch can be electrically connected via other circuitry or structures, for example, via a first gate driver (not shown in the figure).

[0071] Optional, Figure 6 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 2 ,refer to Figure 6The gate voltage adjustment module 40 includes a voltage control unit 410 and a drive control unit 420. The input terminal 410_IN of the voltage control unit 410 is electrically connected to the main control module 10, and the output terminal 410_OUT of the voltage control unit 410 is electrically connected to the first power supply terminal 420_VCC of the drive control unit 420. The input terminal 420_IN of the drive control unit 420 is electrically connected to the first gate driver GDU1, and the output terminal 420_OUT of the drive control unit 420 is electrically connected to the gate G of the current switch T1.

[0072] For example, continuing with the case where both the current switch T1 and the power device under test (DUT) are IGBTs, refer to... Figure 6 The first gate driver GDU1 includes a drive input terminal GDU_IN, a drive output terminal GDU_OUT, a first power supply terminal GDU_VCC, and a second power supply terminal GDU_VEE. The input terminal 420_IN of the drive control unit 420 is electrically connected to the drive output terminal GDU_OUT of the first gate driver GDU1. When the drive output terminal GDU_OUT of the first gate driver GDU1 is high, the voltage of the drive output terminal GDU_OUT is equal to the voltage of the first power supply terminal GDU_VCC. At this time, the output terminal 420_OUT of the drive control unit 420 is also high, and the voltage of the output terminal 420_OUT is equal to the voltage of the output terminal 410_OUT. Furthermore, the first gate driver GDU1 also includes a ground terminal, which can be connected to a floating ground FGND.

[0073] The voltage control unit 410 can receive the voltage setting signal from the main control module 10. The voltage setting signal includes the voltage setting value VGE_Set. The voltage control unit 410 can output a power signal with the corresponding voltage at the output terminal 410_OUT to power the drive control unit 420 according to the voltage setting value VGE_Set. The voltage at the output terminal 410_OUT is less than the voltage at the first power terminal GDU_VCC, that is, the voltage at the first power terminal 420_VCC of the drive control unit 420 is less than the voltage at the first power terminal GDU_VCC.

[0074] For example, the voltages of the first power supply terminal 420_VCC and the first power supply terminal GDU_VCC are both greater than zero, enabling the output terminal 420_OUT of the drive control unit 420 to output a signal with a voltage value less than or equal to the voltage of the first power supply terminal 420_VCC, i.e., the voltage of the output terminal 420_OUT is less than the voltage of the first power supply terminal GDU_VCC. Furthermore, since the voltage of the drive output terminal GDU_OUT of the first gate driver GDU1 is usually the voltage of the first power supply terminal GDU_VCC or the voltage of the second power supply terminal GDU_VEE (the voltage of the second power supply terminal GDU_VEE is less than zero), the voltage of the output terminal 420_OUT of the drive control unit 420 is less than the voltage of the drive output terminal GDU_OUT. In this way, the undervoltage protection value of the first gate driver GDU1 can be overcome, making the positive value of the gate voltage of the current switch T1 smaller (but still greater than the threshold voltage T1_Vth of the test switch T1), thereby limiting the current value in the test circuit to a small range and realizing the clamping protection function of the output current of the dynamic test system.

[0075] In one embodiment, the drive control unit 420 further includes a reference output terminal 420_Ref, which is electrically connected to the emitter E of the current switch T1, forming a gate current return path for the test switch T1. The reference output terminal 420_Ref of the drive control unit 420 can be connected to a floating ground FGND.

[0076] In an alternative embodiment, Figure 7 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 3 ,refer to Figure 7 The voltage control unit 410 includes a digital-to-analog converter circuit 411; the digital input terminal of the digital-to-analog converter circuit 411 is electrically connected to the main control module 10, and the analog output terminal of the digital-to-analog converter circuit 411 is electrically connected to the first power supply terminal 420_VCC of the drive control unit 420.

[0077] The digital input terminal of the digital-to-analog converter circuit 411 is a digital signal input interface that can receive digital signals; the analog output terminal of the digital-to-analog converter circuit 411 is an analog signal output interface that can output analog signals.

[0078] For example, the voltage setting signal output by the main control module 10 is a digital signal, which includes a voltage setting value VGE_Set. The digital-to-analog converter circuit 411 can convert the digital signal output by the main control module 10 into an analog signal. The voltage setting value VGE_Set is adjustable.

[0079] It is understood that the analog output terminal of the digital-to-analog converter circuit 411 can be directly electrically connected to the first power supply terminal 420_VCC of the drive control unit 420, or the analog output terminal of the digital-to-analog converter circuit 411 can also be indirectly electrically connected to the first power supply terminal 420_VCC of the drive control unit 420. This application embodiment does not limit this.

[0080] In yet another alternative embodiment, reference continues to... Figure 7 The voltage control unit also includes a voltage regulation circuit 412; the analog output terminal of the digital-to-analog converter 411 is electrically connected to the first power supply terminal 420_VCC of the drive control unit 420 through the voltage regulation circuit 412. The digital-to-analog converter 411 and the voltage regulation circuit 412 can make the first power supply terminal 420_VCC of the drive control unit 420 equal to the voltage setting value VGE_Set of the main control module 10.

[0081] For example, the digital-to-analog converter circuit 411 and the voltage regulation circuit 412 convert the voltage setting value VGE_Set (positive, adjustable) output by the main control module 10 into an analog quantity to drive the first power supply terminal 420_VCC of the control unit 420, so that the positive value of the gate voltage pulse output by the control unit 420 to the current switch T1 is equal to the voltage of the first power supply terminal 420_VCC, and is adjustable (set by the voltage setting value VGE_Set output by the main control module 10).

[0082] Based on the above embodiments, continue to refer to Figure 7 The voltage regulation circuit 412 includes an operational amplifier EA, a fifth transistor M0, and a first energy storage capacitor C1. The first power supply terminal of the operational amplifier EA and the first terminal of the fifth transistor M0 are both electrically connected to the first power supply terminal 412_VCC of the voltage regulation circuit 412. The second power supply terminal of the operational amplifier EA is connected to the floating ground FGND. The non-inverting input terminal of the operational amplifier EA is electrically connected to the analog output terminal of the digital-to-analog converter circuit 411. The inverting input terminal of the operational amplifier EA is electrically connected to the second terminal of the fifth transistor M0, the first plate of the first energy storage capacitor C1, and the first power supply terminal 420_VCC of the drive control unit 420. The output terminal of the operational amplifier EA is electrically connected to the third terminal of the fifth transistor M0. The second plate of the first energy storage capacitor C1 is connected to the floating ground FGND.

[0083] Specifically, precise voltage regulation can be achieved through a negative feedback closed-loop system composed of operational amplifier EA, and the fifth transistor M0 can charge the first energy storage capacitor C1, providing continuous and stable energy to the drive control unit 420.

[0084] In an optional embodiment, the voltages at the first power supply terminal 412_VCC of the voltage regulating circuit 412 and the first power supply terminal 420_VCC of the drive control unit 420 are greater than 0V. The fifth transistor M0 can be an N-channel MOSFET, including a source S (first terminal), a drain D (second terminal), and a gate G (third terminal). The voltage at the first power supply terminal 412_VCC of the voltage regulating circuit 412 can be equal to the voltage at the first power supply terminal GDU_VCC of the first gate driver GDU1.

[0085] In another optional embodiment, the voltages at the first power supply terminal 412_VCC of the voltage regulating circuit 412 and the first power supply terminal 420_VCC of the drive control unit 420 are greater than 0V. The fifth transistor M0 can be an NPN bipolar junction transistor (BJT), including a collector (first terminal), an emitter (second terminal), and a base (third terminal) (not shown in the figure). In this case, the voltage at the first power supply terminal 412_VCC of the voltage regulating circuit 412 can also be equal to the voltage at the first power supply terminal GDU_VCC of the first gate driver GDU1.

[0086] In another alternative embodiment, the voltage regulation circuit 412 further includes a current-limiting resistor R11, and the output of the operational amplifier EA is electrically connected to the third terminal of the fifth transistor M0 through the current-limiting resistor R11.

[0087] In other alternative embodiments, the voltages of the first power supply terminal 412_VCC of the voltage regulating circuit 412 and the first power supply terminal 420_VCC of the drive control unit 420 can also be less than 0V. In this case, the fifth transistor M0 can be a P-channel MOSFET or a PNP BJT, and the voltage of the first power supply terminal GDU_VCC of the first gate driver GDU1 can also be less than 0V.

[0088] Optional, Figure 8 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 4 ,refer to Figure 8The drive control unit 420 includes a dead-time generation circuit 421 and a power drive circuit 422. The input terminal of the dead-time generation circuit 421 is electrically connected to the drive output terminal GDU_OUT of the first gate driver GDU1. The first output terminal 041 of the dead-time generation circuit 421 is electrically connected to the first input terminal 042 of the power drive circuit 422. The second output terminal 043 of the dead-time generation circuit 421 is electrically connected to the second input terminal 044 of the power drive circuit 422. The output terminal of the power drive circuit 422 is electrically connected to the gate G of the current switch T1. The dead-time generation circuit 421 generates a first drive signal and a second drive signal with a dead time based on the first gate drive signal. The power drive circuit 422 generates a gate voltage pulse with strong drive capability based on the first drive signal and the second drive signal to drive the current switch T1.

[0089] For example, the first output terminal 041 of the dead-time generation circuit 421 can output the logic level of the first drive signal, so that the power drive circuit 422 outputs a positive value of the gate voltage of the current switch T1 according to the logic level of the first drive signal, and drives the current switch T1 to conduct; the second output terminal 043 of the dead-time generation circuit 421 can output the logic level of the second drive signal, so that the power drive circuit 422 outputs a negative value of the gate power supply of the current switch T1 according to the logic level of the second drive signal, and drives the current switch T1 to turn off; there is a dead time between the logic level period of the first drive signal and the logic level period of the second drive signal, so as to avoid the power drive circuit 422 outputting both positive and negative values ​​of the gate voltage at the same time, which would damage the circuit.

[0090] In an alternative embodiment, Figure 9 This is a schematic diagram of the circuit structure of a dynamic testing system for semiconductor power devices provided in an embodiment of this application. Figure 5 ,refer to Figure 9The dead-time generation circuit 421 includes a first transistor M1, a third transistor M3, a first pull-up resistor R3, a second pull-up resistor R8, a first pull-down resistor R7, and a second pull-down resistor R9; wherein, the first transistor M1 is an N-channel MOSFET, and the third transistor M3 is a P-channel MOSFET; the first terminal of the first transistor M1 is electrically connected to the first power supply terminal 420_VCC of the drive control unit 420 through the first pull-up resistor R3, and the second terminal of the first transistor M1 is electrically connected to the first terminal of the third transistor M3 through the first pull-down resistor R7 and the second pull-up resistor R8. The second terminal of the third transistor M3 is electrically connected to the second power supply terminal 420_VEE of the drive control unit 420 via the second pull-down resistor R9; the gates of the first transistor M1 and the third transistor M3 are both electrically connected to the drive output terminal GDU_OUT of the first gate driver GDU1; the connection node between the first pull-down resistor R7 and the second pull-up resistor R8 is also electrically connected to the emitter or source of the current switch T1 (the emitter E when the power device under test DUT is an IGBT; the source when the power device under test DUT is a MOSFET). In an optional embodiment, the gate of the first transistor M1 is further provided with a first gate resistor R1, and the gate of the third transistor M3 is further provided with a third gate resistor R2. In yet another optional embodiment, the connection node between the first pull-down resistor R7 and the second pull-up resistor R8 is also connected to the emitter E of the current switch T1 to the floating ground FGND. The first gate resistor R1 can adjust the gate current of the first transistor M1 to prevent voltage overshoot at the gate of the first transistor M1 and damage to the first transistor M1; the third gate resistor R2 can adjust the gate current of the third transistor M3 to prevent voltage overshoot at the gate of the third transistor M3 and damage to the third transistor M3.

[0091] The power drive circuit 422 includes a second transistor M2 and a fourth transistor M4; wherein the second transistor M2 is a P-channel MMOSFET and the fourth transistor M4 is an N-channel MOSFET; the first terminal of the second transistor M2 is electrically connected to the first power supply terminal 420_VCC of the drive control unit 420, the second terminal of the second transistor M2 and the first terminal of the fourth transistor M4 are both electrically connected to the gate G of the current switch T1, and the second terminal of the fourth transistor M4 is electrically connected to the second power supply terminal 420_VEE of the drive control unit 420; the gate of the second transistor M2 is electrically connected to the first terminal of the first transistor M1; and the gate of the fourth transistor M4 is electrically connected to the second terminal of the third transistor M3. In an optional embodiment, the gate of the second transistor M2 is further provided with a second gate resistor R4, and the gate of the fourth transistor M4 is further provided with a fourth gate resistor R10.

[0092] Specifically, the first transistor M1 and the third transistor M3 can convert the high and low level signals output by the first gate driver GDU1 into the gate drive signals of the second transistor M2 and the fourth transistor M4, which have a certain dead time, to prevent the second transistor M2 and the fourth transistor M4 in the power drive circuit 422 from being turned on at the same time.

[0093] For example, when the first transistor M1 is off, the gate of the second transistor M2 is pulled up to the first power supply terminal 420_VCC through the first pull-up resistor R3, and is at the same potential as the source S of the second transistor M2, so the second transistor M2 is off; when the first transistor M1 is on, the gate voltage of the second transistor M2 is pulled down to 420_VCC*R7 / (R3+R7) (the on-resistance of M1 is negligible, 420_VCC>0V, FGND=0V), forming a negative voltage difference with the source S, and the gate-source voltage of the second transistor M2 is M2_VGS = 420_VCC*R7 / (R3+R7). +R7)-420_VCC=-420_VCC*R3 / (R3+R7), by reasonably setting the resistance values ​​of the first pull-up resistor R3 and the first pull-down resistor R7, it is possible to make -420_VCC*R3 / (R3+R7)<M2_VTH (420_VCC>0V, M2_VTH<0V), so that the second transistor M2 is turned on when the first transistor M1 is turned on; wherein, the second gate resistor R4 can adjust the gate current of the second transistor M2 to avoid voltage overshoot at the gate of the second transistor M2, which could damage the second transistor M2.

[0094] When the third transistor M3 is turned on, the gate voltage of the fourth transistor M4 is pulled up to 420_VEE*R8 / (R8+R9) (the on-resistance of M3 is negligible, 420_VEE < 0V, FGND = 0V), forming a positive voltage difference with the source S of the fourth transistor M4. The gate-source voltage of the fourth transistor M4 is M4_VGS = |420_VEE|*R9 / (R8+R9). By properly setting the resistance values ​​of the second pull-up resistor R8 and the second pull-down resistor R9, it is possible to make M4_VGS > M4_ VTH (420_VEE < 0V, M4_VTH > 0V) is used to ensure that when the third transistor M3 is turned on, the fourth transistor M4 is turned on; when the third transistor M3 is turned off, the gate of the fourth transistor M4 is pulled down to the second power supply terminal 420_VEE through the second pull-down resistor R9, and is at the same potential as the source S of the fourth transistor M4, thus turning off the fourth transistor M4; wherein, the fourth gate resistor R10 can adjust the gate current of the fourth transistor M4 to avoid voltage overshoot at the gate of the fourth transistor M4, which could damage the fourth transistor M4.

[0095] For example, Figure 10This is a timing diagram of a gate voltage adjustment module provided in an embodiment of this application, which can be specifically referred to as... Figure 9 The circuit structure shown is for reference. Figure 10 At time t0, the main control module 10 inputs a voltage setting value VGE_Set to the digital-to-analog converter circuit 411 of the gate voltage adjustment module 10, so that the voltage control unit 410 provides a smaller voltage value VGE_Set (T1_Vth < VGE_Set < GDU_VCC) to the first power supply terminal 420_VCC of the drive control unit 420; the drive input terminal GDU_IN of the first gate driver GDU1 is at logic level 0, and the drive output terminal GDU_OUT of the first gate driver GDU1 outputs the voltage of the second power supply terminal GDU_VEE. At this time, M3_VGS and M1_VGS are negative (VEE), the third transistor M3 is turned on, and the first transistor M1 is turned off; the current ISD_M3 flows through the second pull-down resistor R 9. A positive voltage is formed between the gate and source of the fourth transistor M4, M4_VGS=|420_VEE|*R9 / (R8+R9) (the on-resistance of M3 is negligible, 420_VEE<0V, FGND=0V). By properly setting the resistance values ​​of the second pull-up resistor R8 and the second pull-down resistor R9, M4_VGS>M4_VTH (420_VEE<0V, M4_VTH>0V) can be made. At this time, the fourth transistor M4 is turned on, and the gate G of the current switch T1 is connected to the second power supply terminal 420_VEE through the fourth transistor M4. The gate voltage of the current switch T1 is 420_VEE, that is, the gate-emitter voltage T1_VGE of the current switch T1 is VGE_L1. At this time, the current switch T1 is turned off.

[0096] At time t1, the input of the first gate driver GDU1, GDU_IN, becomes logic level 1, and the output voltage of the drive output, GDU_OUT, begins to reverse in the direction of the voltage of the first power supply, GDU_VCC. At this time, M3_VGS and M1_VGS also begin to gradually increase along with the output voltage of the drive output, GDU_OUT.

[0097] At time t2, M3_VGS and M1_VGS increase to the threshold voltage M3_VTH of the third transistor M3 as the output voltage of the drive output terminal GDU_OUT increases. The third transistor M3 is turned off. The gate voltage of the fourth transistor M4 decreases to 420_VEE (420_VEE < 0V, FGND = 0V) after being discharged by the fourth gate resistor R10 and the second pull-down resistor R9. At this time, M4_VGS = 0V, and the fourth transistor M4 is turned off. At this time, the gate voltage of the current switch T1 is still the voltage of the second power supply terminal 420_VEE, that is, the gate-emitter voltage T1_VGE of the current switch T1 is still VGE_L1.

[0098] At time t3, as the output voltage of the drive output terminal GDU_OUT increases, M3_VGS and M1_VGS reach the threshold voltage M1_VTH of the first transistor M1. The first transistor M1 turns on, and the current flows through the first pull-up resistor R3 to form a negative voltage between the gate and source of the second transistor M2. M2_VGS = 420_VCC * R7 / (R3 + R7) - 420_VCC (the on-resistance of M1 is negligible, 420_VCC > 0V, FGND = 0V). Through reasonable settings... By setting the resistance values ​​of the first pull-up resistor R3 and the first pull-down resistor R7, M2_VGS < M2_VTH (420_VCC > 0V, M2_VTH < 0V). At this time, the second transistor M2 is turned on, and the gate current of the current switch T1 flows from the first power supply terminal 420_VCC of the drive control unit 420 through the second transistor M2 to the gate of the current switch T1. The gate voltage of the current switch T1 begins to rise, that is, the gate-emitter voltage T1_VGE of the current switch T1 begins to rise.

[0099] At time t4, the gate-emitter voltage T1_VGE of current switch T1 rises to the threshold voltage T1_VTH of current switch T1, and current switch T1 starts to turn on.

[0100] At time t5, the gate-emitter voltage T1_VGE of the current switch T1 rises to VGE_H1, and the current switch T1 is fully turned on.

[0101] At time t6, the drive input GDU_IN of the first gate driver GDU1 becomes logic level 0, and the output voltage of the drive output terminal GDU_OUT begins to reverse in the direction of the voltage of the second power supply terminal GDU_VEE. At this time, M3_VGS and M1_VGS also begin to gradually decrease along with the output voltage of the drive output terminal GDU_OUT.

[0102] At time t7, as the output voltage of the drive output terminal GDU_OUT decreases to the threshold voltage M1_VTH of the first transistor M1, the first transistor M1 is turned off, M2_VGS = 0V, the second transistor M2 is turned off, and the gate-emitter voltage T1_VGE of the current switch T1 remains VGE_H1.

[0103] At time t8, as the output voltage of the drive output terminal GDU_OUT decreases to the threshold voltage M3_VTH of the third transistor M3, the third transistor M3 turns on. The current ISD_M3 forms a positive voltage M4_VGS between the gate and source of the fourth transistor M4 through the second pull-down resistor R9, causing M4 to turn on. The gate current of the current switch T1 flows through the fourth transistor M4 to the second power supply terminal 420_VEE, and the gate voltage of the test T1 begins to decrease.

[0104] At time t9, the gate-emitter voltage T1_VGE of the current switch T1 decreases from VGE_H1 to VGE_L1, and the current switch T1 is turned off.

[0105] Based on the above embodiments, continue to refer to Figure 9 The maximum operating current of the second transistor M2 is greater than the maximum operating current of the first transistor M1, and also greater than the maximum operating current of the third transistor M3; the maximum operating current of the fourth transistor M4 is greater than the maximum operating current of the first transistor M1, and also greater than the maximum operating current of the third transistor M3.

[0106] For example, in the drive control unit 420, the first transistor M1 and the third transistor M3 of the dead zone generation circuit 421 can be low-power MOSFETs with fast switching speeds; the second transistor M2 and the fourth transistor M4 of the power drive circuit 422 can be high-power MOSFETs with strong current carrying capacity, which can provide a large gate drive current for the current switch T1.

[0107] In this embodiment, the maximum operating current of the first transistor M1 and the maximum operating current of the third transistor M3 can be the same, and the maximum operating current of the second transistor M2 and the maximum operating current of the fourth transistor M4 can be the same. In other embodiments, the maximum operating current of the first transistor M1 and the maximum operating current of the third transistor M3 can be different, and / or the maximum operating current of the second transistor M2 and the maximum operating current of the fourth transistor M4 can be different. This application does not limit this.

[0108] In an optional embodiment, the drive control unit 420 further includes a first guiding diode D1 and a second guiding diode D2; the anode of the first guiding diode D1 is electrically connected to the second electrode of the second transistor M2, and the cathode of the first guiding diode D1 is electrically connected to the gate G of the current switch T1; the anode of the second guiding diode D2 is electrically connected to the gate G of the current switch T1, and the cathode of the second guiding diode D2 is electrically connected to the first electrode of the fourth transistor M4.

[0109] For example, the first guiding diode D1 and the second guiding diode D2 may include Schottky diodes, which have a fast turn-on speed and low on-state voltage, and are able to guide the gate positive voltage and negative voltage of the current switch T1.

[0110] In addition, the drive control unit 420 also includes a fifth gate resistor R5 and a sixth gate resistor R6. The cathode of the first guiding diode D1 is electrically connected to the gate G of the current switch T1 through the fifth gate resistor R5, and the anode of the second guiding diode D2 is electrically connected to the gate G of the current switch T1 through the sixth gate resistor R6. The fifth gate resistor R5 and the sixth gate resistor R6 are current-limiting resistors for the gate turn-on and turn-off of the current switch T1, which can prevent voltage overshoot at the gate of the current switch T1 and damage to the current switch T1.

[0111] In yet another alternative implementation, refer to Figure 9 The drive control unit 420 also includes a second energy storage capacitor C2; the first plate of the second energy storage capacitor C2 is electrically connected to the second power supply terminal 420_VEE of the drive control unit 420, and the second plate of the second energy storage capacitor C2 is connected to the floating ground FGND.

[0112] The second energy storage capacitor C2 can maintain the voltage stability of the second power supply terminal 420_VEE.

[0113] In yet another alternative implementation, refer to Figure 9 The power module 20 includes a DC power supply DC and a third energy storage capacitor C3.

[0114] For example, the DC power supply DC includes a high-voltage DC power supply, and the third energy storage capacitor C3 includes a high-voltage capacitor bank. The third energy storage capacitor C3 can provide continuous and stable energy to the test circuit when the current in the test circuit changes rapidly and significantly, thereby improving the adaptability of the power supply module 20 to sudden current changes in the test circuit.

[0115] In another optional implementation, the gate driver has undervoltage protection. In this embodiment, by setting the gate voltage adjustment module 40, the gate voltage of the current switch T1 is adjusted by receiving the voltage setting signal from the main control module 10. This can make the gate voltage value lower than the positive voltage value of the gate driver's undervoltage protection value, thus breaking through the limitation of the existing gate driver's undervoltage protection value and realizing clamping protection in the short-circuit test of semiconductor power devices. In this way, the peak current when the power device under test is damaged can be effectively reduced, avoiding damage to the short-circuit current test system and application-end test fixtures and other equipment.

[0116] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A dynamic testing system for semiconductor power devices, characterized in that, include: The main control module, power supply module, overcurrent detection module, current switch, first gate driver, second gate driver, and gate voltage adjustment module are included. The power module, the overcurrent detection module, and the current switch are connected in series to form a test circuit with the power device under test. The first gate driver is electrically connected to the gate of the current switch through the gate voltage adjustment module; The second gate driver is used to connect to the gate of the power device under test; The main control module is electrically connected to the overcurrent detection module, the first gate driver, the second gate driver, and the gate voltage adjustment module, respectively. The first gate driver is used to receive a first control signal from the main control module and output a first gate drive signal according to the first control signal; the gate voltage adjustment module is used to receive the first gate drive signal and drive the current switch according to the first gate drive signal; the gate voltage adjustment module is also used to receive a voltage setting signal from the main control module and control the gate voltage of the current switch according to the voltage setting signal.

2. The dynamic testing system for semiconductor power devices according to claim 1, characterized in that, The gate voltage adjustment module includes a voltage control unit and a drive control unit; The input terminal of the voltage control unit is electrically connected to the main control module, and the output terminal of the voltage control unit is electrically connected to the first power supply terminal of the drive control unit. The input terminal of the drive control unit is electrically connected to the first gate driver, and the output terminal of the drive control unit is electrically connected to the gate of the current switch.

3. The dynamic testing system for semiconductor power devices according to claim 2, characterized in that, The voltage control unit includes a digital-to-analog converter circuit; The digital input terminal of the digital-to-analog converter is electrically connected to the main control module, and the analog output terminal of the digital-to-analog converter is electrically connected to the first power supply terminal of the drive control unit.

4. The dynamic testing system for semiconductor power devices according to claim 3, characterized in that, The voltage control unit also includes a voltage regulation circuit; The analog output terminal of the digital-to-analog converter circuit is electrically connected to the first power supply terminal of the drive control unit through the voltage regulation circuit.

5. The dynamic testing system for semiconductor power devices according to claim 4, characterized in that, The voltage regulation circuit includes an operational amplifier, a fifth transistor, and a first energy storage capacitor; The first power supply terminal of the operational amplifier and the first terminal of the fifth transistor are both electrically connected to the first power supply terminal of the voltage regulation circuit, and the second power supply terminal of the operational amplifier is grounded. The non-inverting input of the operational amplifier is electrically connected to the analog output of the digital-to-analog converter circuit; the inverting input of the operational amplifier is electrically connected to the second terminal of the fifth transistor, the first plate of the first energy storage capacitor, and the first power supply terminal of the drive control unit; the output of the operational amplifier is electrically connected to the third terminal of the fifth transistor; and the second plate of the first energy storage capacitor is grounded.

6. The dynamic testing system for semiconductor power devices according to claim 2, characterized in that, The drive control unit includes a dead zone generation circuit and a power drive circuit; The input terminal of the dead-time generation circuit is electrically connected to the drive output terminal of the first gate driver, the first output terminal of the dead-time generation circuit is electrically connected to the first input terminal of the power drive circuit, the second output terminal of the dead-time generation circuit is electrically connected to the second input terminal of the power drive circuit, and the output terminal of the power drive circuit is electrically connected to the gate of the current switch. The dead-time generation circuit is used to generate a first drive signal and a second drive signal having a dead time according to the first gate drive signal; the power drive circuit is used to drive the current switch according to the first drive signal and the second drive signal.

7. The dynamic testing system for semiconductor power devices according to claim 6, characterized in that, The dead zone generation circuit includes a first transistor, a third transistor, a first pull-up resistor, a second pull-up resistor, a first pull-down resistor, and a second pull-down resistor; wherein the first transistor is an N-channel MOSFET, and the third transistor is a P-channel MOSFET. The first terminal of the first transistor is electrically connected to the first power supply terminal of the drive control unit through a first pull-up resistor; the second terminal of the first transistor is electrically connected to the first terminal of the third transistor through a first pull-down resistor and a second pull-up resistor; the second terminal of the third transistor is electrically connected to the second power supply terminal of the drive control unit through a second pull-down resistor; the gates of the first transistor and the third transistor are both electrically connected to the drive output terminal of the first gate driver. The connection node between the first pull-down resistor and the second pull-up resistor is also electrically connected to the emitter or source of the current switch; The power drive circuit includes a second transistor and a fourth transistor; wherein the second transistor is a P-channel MOSFET and the fourth transistor is an N-channel MOSFET. The first terminal of the second transistor is electrically connected to the first power supply terminal of the drive control unit. The second terminal of the second transistor and the first terminal of the fourth transistor are both electrically connected to the gate of the current switch. The second terminal of the fourth transistor is electrically connected to the second power supply terminal of the drive control unit. The gate of the second transistor is electrically connected to the first terminal of the first transistor. The gate of the fourth transistor is electrically connected to the second terminal of the third transistor.

8. The dynamic testing system for semiconductor power devices according to claim 7, characterized in that, The maximum operating current of the second transistor is greater than the maximum operating current of the first transistor, and is also greater than the maximum operating current of the third transistor. The maximum operating current of the fourth transistor is greater than the maximum operating current of the first transistor, and is also greater than the maximum operating current of the third transistor.

9. The dynamic testing system for semiconductor power devices according to claim 7, characterized in that, The drive control unit further includes a first guiding diode and a second guiding diode; The anode of the first guiding diode is electrically connected to the second electrode of the second transistor, and the cathode of the first guiding diode is electrically connected to the gate of the current switch; The anode of the second guiding diode is electrically connected to the gate of the current switch, and the cathode of the second guiding diode is electrically connected to the first electrode of the fourth transistor.

10. The dynamic testing system for semiconductor power devices according to claim 7, characterized in that, The drive control unit also includes a second energy storage capacitor; The first plate of the second energy storage capacitor is electrically connected to the second power supply terminal of the drive control unit, and the second plate of the second energy storage capacitor is grounded.

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