Detection circuit and detection system for T-type three-level inverters

Abstract

This utility model discloses a detection circuit and detection system for a T-type three-level inverter. The T-type three-level inverter includes a first photovoltaic input polarity terminal, a second photovoltaic input polarity terminal, and at least one phase inverter branch. The inverter branch is connected between the internal nodes of the T-type three-level inverter and the corresponding output terminal of the inverter branch. Each phase inverter branch includes at least one switching transistor. The detection circuit includes: a test power supply module, a control module, a first test branch corresponding to each inverter branch, a second test branch, and a current detection module. The first test branch is connected in series between the first photovoltaic input polarity terminal and the corresponding output terminal of the inverter branch, and the second test branch is connected in series between the second photovoltaic input polarity terminal and the corresponding output terminal of the inverter branch. This solves the problems of damaging the sealing strip and low production efficiency when detecting the switching transistors in the T-type three-level inverter.

Description

Technical Field

[0001] This utility model relates to the field of detection technology, and in particular to the detection circuit and detection system for a T-type three-level inverter. Background Technology

[0002] A T-type three-level inverter is a grid-connected inverter device that addresses reactive power, harmonics, and low power factor issues on the low-voltage side by injecting current into the grid through parallel connection to a low-voltage line. The switching transistor is a critical component of the T-type three-level inverter, and its reliability almost entirely determines the overall reliability of the product. If the switching transistor fails, the T-type three-level inverter will essentially cease to function properly, losing its inverter function. Furthermore, the arcing generated by the failed transistor can damage other components within the T-type three-level inverter (such as the PCB board, capacitors, copper busbars, and drive circuits).

[0003] Therefore, the control and testing of the switching transistors are quite strict during the production process of T-type three-level inverters. Furthermore, after the T-type three-level inverter is manufactured, the casing is generally fully installed, and the sealing strip between the casing and the cover is tightened. If the switching transistors are tested using traditional methods, the casing of the T-type three-level inverter needs to be opened, and the testing device needs to be manually connected to the circuit board containing the switching transistors inside the inverter. This can damage the sealing strips and result in excessively long operation times, affecting production efficiency. Utility Model Content

[0004] This invention provides a detection circuit and detection system for a T-type three-level inverter to solve the problems of damaging the sealing strip and excessive operation time affecting production efficiency when detecting the switching transistors inside the T-type three-level inverter.

[0005] According to one aspect of the present invention, a detection circuit for a T-type three-level inverter is provided, which is applied to a T-type three-level inverter. The T-type three-level inverter includes a photovoltaic input first polarity terminal, a photovoltaic input second polarity terminal, at least one phase output terminal, and an inverter branch corresponding to the output terminal. The inverter branch is connected between the internal node of the T-type three-level inverter and the output terminal corresponding to the inverter branch.

[0006] The detection circuit of the T-type three-level inverter includes: a test power supply module, a control module, a test branch group corresponding to each inverter branch, and a current detection module corresponding to each inverter branch. The test branch group includes a first test branch and a second test branch. The first test branch is connected in series between the first polarity terminal of the photovoltaic input and the output terminal corresponding to the inverter branch of the first test branch. The second test branch is connected in series between the second polarity terminal of the photovoltaic input and the output terminal corresponding to the inverter branch of the second test branch.

[0007] The test power supply module is connected between the first polarity terminal of the photovoltaic input and the second polarity terminal of the photovoltaic input, and the test power supply module is also connected to the control module;

[0008] The current detection module is configured to detect the current in the inverter branch;

[0009] The inverter branch includes at least one switching transistor. The control module is connected to the control terminal of the first test branch and the control terminal of the second test branch, respectively, and is configured to control one of the first test branch and the second test branch corresponding to the inverter branch to which the switching transistor under test belongs to be turned on according to the switching transistor under test.

[0010] Optionally, the test power supply module includes a DC power supply and a power supply control switch;

[0011] The first terminal of the power supply control switch is connected to the first electrode of the DC power supply, the second terminal of the power supply control switch is connected to the first polarity terminal of the photovoltaic input, and the control terminal of the power supply control switch is connected to the control module.

[0012] The second terminal of the DC power supply is connected to the second polarity terminal of the photovoltaic input.

[0013] Optionally, the power supply control switch is a contactor.

[0014] Optionally, the first test branch includes a first test switch, a first terminal of the first test switch is connected to the first polarity terminal of the photovoltaic input, a second terminal of the first test switch is connected to the output terminal of the inverter branch corresponding to the first test switch, and a control terminal of the first test switch is connected to the control module.

[0015] The second test branch includes a second test switch. The first end of the second test switch is connected to the second polarity terminal of the photovoltaic input, the second end of the second test switch is connected to the output terminal of the inverter branch corresponding to the second test switch, and the control terminal of the second test switch is connected to the control module.

[0016] Optionally, both the first test switch and the second test switch are contactors.

[0017] Optionally, the T-type three-level inverter further includes a first capacitor, a second capacitor, and a second inductor. The first end of the second inductor is connected to the first polarity terminal of the photovoltaic input, the second end of the second inductor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second polarity terminal of the photovoltaic input.

[0018] The first end of the inverter branch is connected to the first end of the first capacitor, the second end of the inverter branch is connected to the second end of the first capacitor, the third end of the inverter branch is connected to the second end of the second capacitor, and the fourth end of the inverter branch is connected to the corresponding output end of the inverter branch.

[0019] Optionally, any phase of the inverter branch includes a first inductor, two switching transistors connected in series between the second end of the first capacitor and the first end of the first inductor and in opposite directions, and two switching transistors connected in series between the first end of the first capacitor and the second end of the second capacitor and in the same direction, wherein the second end of the first inductor is connected to the corresponding output terminal of the inverter branch.

[0020] Optionally, the current detection module includes a Hall sensor, which is mounted on the line at the first end of the first inductor.

[0021] According to another aspect of the present invention, a detection system for a T-type three-level inverter is provided, comprising the detection circuit for the T-type three-level inverter as described in any of the preceding aspects.

[0022] Optionally, the detection system for the T-type three-level inverter further includes an oscilloscope, which is connected to the current detection module.

[0023] The technical solution of this utility model embodiment provides a corresponding detection branch group for each phase in a T-type three-level inverter. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected between the first polarity terminal of the photovoltaic input and the output terminal of the phase in the T-type three-level inverter, and the second detection branch is connected between the second polarity terminal of the photovoltaic input and the output terminal of the phase. When detecting the switching transistor, the switching transistor and one of the first detection branch and the second detection branch are connected to form a current flow path. The fault detection of the switching transistor is achieved by detecting the current in the detection circuit. Since the first and second photovoltaic input terminals are the interfaces for connecting the T-type three-level inverter to the photovoltaic modules, and the output terminal is the interface for connecting to the power grid, the detection circuit in this invention can detect the switching transistors inside the T-type three-level inverter by connecting to the three ports: the first and second photovoltaic input terminals and the output terminal. This eliminates the need to disassemble the casing of the T-type three-level inverter, ensuring the integrity of the casing protection. At the same time, the connection between the detection circuit and the T-type three-level inverter is convenient and quick, shortening the testing time and improving production efficiency.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of the detection circuit of a T-type three-level inverter provided in this embodiment of the utility model;

[0027] Figure 2 A driving timing diagram of the detection circuit of a T-type three-level inverter provided for an embodiment of this utility model;

[0028] Figure 3 A circuit diagram for detecting the second switching transistor provided in an embodiment of this utility model;

[0029] Figure 4 A current waveform diagram on the first inductor during the testing of the second switching transistor is provided in this embodiment of the present invention.

[0030] Figure 5 A circuit diagram for detecting a third switching transistor is provided in an embodiment of this utility model;

[0031] Figure 6 A circuit diagram for detecting the first switching transistor provided in an embodiment of this utility model;

[0032] Figure 7 A circuit diagram for detecting the fourth switching transistor provided in this embodiment of the present invention;

[0033] Figure 8 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the utility model;

[0034] Figure 9 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the utility model;

[0035] Figure 10 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the present invention. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] Figure 1 This is a schematic diagram of the detection circuit for a T-type three-level inverter, provided in an embodiment of the present invention. The T-type three-level inverter includes a photovoltaic input first polarity terminal PV1, a photovoltaic input second polarity terminal PV2, at least one phase output terminal INV, and an inverter branch 10 corresponding to the output terminal INV. Each output terminal INV corresponds one-to-one with an inverter branch 10. The inverter branch 10 is connected between an internal node of the T-type three-level inverter and the corresponding output terminal INV. The photovoltaic input first polarity terminal PV1 and the photovoltaic input second polarity terminal PV2 are PV interfaces used to connect to the input interfaces of a photovoltaic array or solar panel; one is the positive terminal, and the other is the negative terminal.

[0039] The T-type three-level inverter also includes a first capacitor C1, a second capacitor C2, and a second inductor L2. The first end of the second inductor L2 is connected to the first polarity terminal PV1 of the photovoltaic input, the second end of the second inductor L2 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second polarity terminal PV2 of the photovoltaic input.

[0040] The first terminal of inverter branch 10 is connected to the first terminal of the first capacitor C1, the second terminal of inverter branch 10 is connected to the second terminal of the first capacitor C1, the third terminal of inverter branch 10 is connected to the second terminal of the second capacitor C2, and the fourth terminal of inverter branch 10 is connected to the corresponding output terminal INV of inverter branch 10. Each phase inverter branch 10 includes a first inductor L1, two switching transistors connected in series between the second terminal of the first capacitor C1 and the first terminal of the first inductor L1 with opposite directions, and two switching transistors connected in series between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2 with the same direction. The second terminal of the first inductor L1 is connected to the corresponding output terminal INV of inverter branch 10.

[0041] The detection circuit of the T-type three-level inverter includes: a test power supply module 13, a control module, a test branch group corresponding to each inverter branch 10, and a current detection module 11 corresponding to each inverter branch 10. The test branch group includes a first test branch 121 and a second test branch 122. The first test branch 121 is connected in series between the first polarity terminal PV1 of the photovoltaic input and the output terminal INV of the inverter branch 10 corresponding to the first test branch 121. The second test branch 122 is connected in series between the second polarity terminal PV2 of the photovoltaic input and the output terminal INV of the inverter branch 10 corresponding to the second test branch 122.

[0042] The test power supply module 13 is connected between the first polarity terminal PV1 of the photovoltaic input and the second polarity terminal PV2 of the photovoltaic input. The test power supply module 13 is also connected to the control module.

[0043] The current detection module 11 is configured to detect the current in the inverter branch 10;

[0044] The inverter branch 10 includes at least one switching transistor. The control module is connected to the control terminal of the first test branch 121 and the control terminal of the second test branch 122 respectively, and is configured to control one of the first test branch 121 and the second test branch 122 corresponding to the inverter branch 10 to which the switching transistor under test belongs to conduct according to the switching transistor under test.

[0045] A T-type three-level inverter can be a three-phase inverter, including phases A, B, and C. Correspondingly, it includes three-phase inverter branches: the inverter branch for phase A, the inverter branch for phase B, and the inverter branch for phase C. The devices and their connections in each inverter branch 10 are identical. The T-type three-level inverter includes three output terminals INV. The first and second test branches of the phase A inverter branch are connected to the output terminals of phase A, phase B, and phase C. When the T-type three-level inverter is a three-phase inverter, the performance of the switching transistors can be tested sequentially for each phase, or all three phases can be tested simultaneously. For any given phase, the four switching transistors in that phase's inverter branch are tested sequentially. During simultaneous testing of all three phases, the same number of switching transistors are turned on at the same time in each phase; for example, the first switching transistor T1 is tested simultaneously across all three phases. A T-type three-level inverter can be a single-phase inverter, such as... Figure 1 As shown, it includes only one inverter branch 10 and one output terminal INV.

[0046] The inverter branch 10 includes four switching transistors, denoted as first switching transistor T1, second switching transistor T2, third switching transistor T3, and fourth switching transistor T4, each of which is an IGBT. The first terminal of the first switching transistor T1 is connected to the first terminal of the first capacitor C1; the second terminal of the first switching transistor T1 is connected to the first terminal of the second switching transistor T2; the second terminal of the second switching transistor T2 is connected to the second polarity terminal PV2 of the photovoltaic input; the first terminal of the third switching transistor T3 is connected to the first terminal of the first inductor L1; the second terminal of the third switching transistor T3 is connected to the second terminal of the fourth switching transistor T4; the first terminal of the fourth switching transistor T4 is connected to the second terminal of the first capacitor C1; and the base of each switching transistor is connected to the control module. The first test branch 121 and / or the second test branch 122 may include switches, inductors, and other devices, without specific limitations. The current detection module 11 is connected to the first inductor L1 to obtain the current at the first inductor L1.

[0047] When testing the switching transistors, only one switching transistor is controlled to be turned on at any given time, and one of the first test branch 121 and the second test branch 122, which can form a circuit with the turned-on switching transistor, is turned on. Specifically, taking a T-type three-level inverter as a single-phase inverter as an example, in the first test stage, the control module controls the first switch T1 and the second test branch 122 to be turned on. The current flows out from the first end of the first capacitor C1, passes through the first switch T1, the output terminal INV, and the second test branch 122, and flows into the second end of the second capacitor C2. At the end of the first test stage, the first switch T1 is turned off, and the current value at the first inductor L1 before the first switch T1 is turned off is collected at the end of the first test stage. In one optional embodiment, both the first test branch 121 and the second test branch 122 include a switch and an inductor. The current value at the end of the first test stage is compared with the theoretical current value. If the deviation between the two is less than a preset range, it can be confirmed that the current values ​​are equal and the working performance of the first switch T1 is normal. Otherwise, it is determined that the performance of the first switch T1 is abnormal. In this test, the theoretical current of the first switch T1 is equal to the product of the voltage difference between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2 and the conduction time of the first switch T1, divided by the inductance value of the inductor in the second test branch 122. In the second test stage, the control module controls the second switch T2 and the first test branch 121 to conduct, and the performance verification process for the second switch T2 is similar to that for the first switch T1, and will not be repeated here. In the third test stage, the control module controls the third switch T3 and the first test branch 121 to conduct, and the performance verification process for the third switch T3 is similar to that for the first switch T1, and will not be repeated here. In the fourth test stage, the control module controls the fourth switch T4 and the second test branch 122 to conduct, and the performance verification process for the fourth switch T4 is similar to that for the first switch T1, and will not be repeated here.

[0048] The technical solution of this utility model embodiment provides a corresponding detection branch group for each phase in a T-type three-level inverter. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected between the first polarity terminal of the photovoltaic input and the output terminal of the phase in the T-type three-level inverter, and the second detection branch is connected between the second polarity terminal of the photovoltaic input and the output terminal of the phase. When detecting the switching transistor, the switching transistor and one of the first detection branch and the second detection branch are connected to form a current flow path. The fault detection of the switching transistor is achieved by detecting the current in the detection circuit. Since the first and second photovoltaic input terminals are the interfaces for connecting the T-type three-level inverter to the photovoltaic modules, and the output terminal is the interface for connecting to the power grid, the detection circuit in this invention can detect the switching transistors inside the T-type three-level inverter by connecting to the three ports: the first and second photovoltaic input terminals and the output terminal. This eliminates the need to disassemble the casing of the T-type three-level inverter, ensuring the integrity of the casing protection. At the same time, the connection between the detection circuit and the T-type three-level inverter is convenient and quick, shortening the testing time and improving production efficiency.

[0049] Continue to refer to Figure 1 Optionally, the inverter branch 10 also includes an inverter output switch Rly, which is connected in series between the second terminal of the first inductor L1 and the output terminal INV of the inverter branch 10.

[0050] Continue to refer to Figure 1 Optionally, the first test branch 121 includes a first test switch KM1, the first end of the first test switch KM1 is connected to the first polarity terminal PV1 of the photovoltaic input, the second end of the first test switch KM1 is connected to the output terminal INV of the inverter branch 10 corresponding to the first test switch KM1, and the control terminal of the first test switch KM1 is connected to the control module.

[0051] The second test branch 122 includes a second test switch KM2. The first end of the second test switch KM2 is connected to the second polarity terminal PV2 of the photovoltaic input. The second end of the second test switch KM2 is connected to the output terminal INV of the inverter branch 10 corresponding to the second test switch KM2. The control terminal of the second test switch KM2 is connected to the control module.

[0052] Optionally, each switch in each inverter branch 10 includes an anti-parallel diode. The first switch T1 includes a first diode D1, the second switch T2 includes a second diode D2, the third switch T3 includes a third diode D3, and the fourth switch T4 includes a fourth diode D4. The anode of each anti-parallel diode is connected to the second terminal of its respective switch, and the cathode is connected to the first terminal of its respective switch. When testing the switches, after turning off one switch, the current in the circuit can freewheel through the diodes in other switches to further verify whether the diodes are functioning correctly.

[0053] Each test branch includes only one switch, which is simple in structure and easy to implement. Optionally, both the first test switch KM1 and the second test switch KM2 are contactors. Contactors can switch large currents, and the contacts are made of high-quality materials, which are durable and can operate stably for a long time. They also allow high-frequency switching operations, and have high power carrying capacity, stability during frequent operation, convenient remote control, and safety protection functions.

[0054] Continue to refer to Figure 1 The current detection module 11 includes a Hall sensor, which is mounted on the line at the first end of the first inductor L1.

[0055] Continue to refer to Figure 1 Optionally, the test power supply module 13 includes a DC power supply 131 and a power supply control switch KM;

[0056] The first terminal of the power supply control switch KM is connected to the first terminal of the DC power supply 131, the second terminal of the power supply control switch KM is connected to the first polarity terminal PV1 of the photovoltaic input, and the control terminal of the power supply control switch KM is connected to the control module.

[0057] The second terminal of the DC power supply 131 is connected to the second polarity terminal PV2 of the photovoltaic input.

[0058] Because the current generated during the testing of the switching transistors in inverter branch 10 consumes energy in the copper busbar and inductor, it is necessary to set the DC bus of the T-type three-level inverter to be charged by the DC power supply 131 after it falls below a certain amplitude before subsequent tests can continue. This ensures the smooth progress of the switching transistor testing and the accuracy of the test results. At the start of the test, the DC power supply 131 can charge the T-type three-level inverter once. If half of the switching transistors are tested during the process, the DC power supply 131 can charge the T-type three-level inverter a second time. There is a disconnectable power supply control switch KM between the DC power supply 131 and the T-type three-level inverter under test. To ensure the safety of the DC power supply 131, after the DC power supply 131 has finished charging the DC bus of the T-type three-level inverter, the power supply control switch KM is disconnected before testing the switching transistors in inverter branch 10 of the T-type three-level inverter begins. Optionally, the power supply control switch KM can be a contactor.

[0059] Figure 2 Taking the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 as an example, the first terminal of each of them is a collector and the second terminal of each of them is an emitter, and the first terminal of the DC power supply 131 is a positive terminal and the second terminal is a negative terminal. Figure 2 This invention provides a timing diagram of the detection circuit for a T-type three-level inverter, illustrating that all switches are turned on at a high potential. Figure 3 This invention provides a circuit diagram for detecting the second switching transistor according to an embodiment of the present invention. Figure 4 This invention provides a current waveform diagram on the first inductor during the testing of the second switching transistor, as shown in this embodiment of the invention. Figure 4 The horizontal axis represents time (in seconds), and the vertical axis represents the current iL in the first inductor (in amperes). Figure 5 This invention provides a circuit diagram for detecting a third switching transistor according to an embodiment of the present invention. Figure 6 This invention provides a circuit diagram for detecting the first switching transistor according to an embodiment of the present invention. Figure 7 This invention provides a circuit diagram for detecting the fourth switching transistor according to an embodiment of the present invention. Figure 3 , Figure 5 , Figure 6 and Figure 7 The red line represents the current path of the switching transistor, and the blue line represents the freewheeling current path of the anti-parallel diode.

[0060] refer to Figures 2-7For the case where the second switch T2 needs to be tested, since the output port of the inductor cannot be connected to the DC bus + inside the T-type three-level inverter product, the first test branch containing the first test switch KM1 is connected to the first polarity terminal PV1 of the photovoltaic input, that is, connected to the DC bus + through the second inductor L2. After closing the first test switch KM1, a drive pulse is first applied to the second switch T2, turning on the second switch T2. Current flows out from the first terminal of the first capacitor C1, through the second inductor L2 and the first inductor L1, through the second switch T2, and ends at the second terminal of the second capacitor C2 (as shown by the red arrow). During this process, the current flowing through the second switch T2 increases linearly due to the current limiting effect of the first inductor L1 and the second inductor L2 in the circuit. When the drive pulse ends, the second switch T2 turns off, and the current rises to its maximum value and then begins to decrease. The inductor current can be monitored throughout the process using the current detection module 11. Given that the switching time of the second switch T2 is set to t1, the voltage between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2 is set to the first voltage U1, and the inductance values ​​of the first inductor L1 and the second inductor L2 are determined, the theoretical current value iL1 on the first inductor L1 at the turn-off time of the second switch T2 can be calculated using the following formula: Where t1 is the conduction time of the second switch T2, and L is the sum of the inductance values ​​of the first inductor L1 and the second inductor L2. This value is stored in the control module as the theoretical current value, and compared with the current value collected by the current detection module 11 during the above process. If the deviation is less than the preset deviation value, the first switch T1 is considered to be performing normally. The calculation method for the theoretical current values ​​of the first switch T1, the third switch T3, and the fourth switch T4 at the turn-off time is similar to that of the second switch T2, and will not be repeated hereafter. Simultaneously, after the first switch T1 is turned off, the current in the inductor freewheels through the first diode D1, and the current value gradually decreases. By monitoring the trend of current change at the first inductor L1, if there is a decreasing trend after the second switch T2 is turned off, it can be determined that the first diode D1 is performing normally. If the current drops to 0 in a very short time without a gradual decreasing trend, it is determined that the first diode D1 is malfunctioning. Figure 4 As shown, when the second switch T2 is functioning normally, during the first stage M1, the second switch T2 is in the conducting state, and the current in the first inductor L1, i.e., the current in the circuit, gradually increases. During the second stage M2 after the second switch T2 is turned off, if the first diode D1 is functioning normally, the current in the circuit gradually decreases to 0. Therefore, by monitoring the current during the test, it is possible to determine whether the performance of the second switch T2 and the first diode D1 is normal.

[0061] like Figure 5As shown, for the case where the third switch T3 needs to be tested, since the output port of the inductor cannot be connected to the DC bus + inside the T-type three-level inverter product, the first test branch containing the first test switch KM1 is connected to the first polarity terminal PV1 of the photovoltaic input, that is, connected to the DC bus + through the second inductor L2. After closing the first test switch KM1, a drive pulse is first applied to the third switch T3, turning on the third switch T3. Current flows out from the first terminal of the first capacitor C1, through the second inductor L2 and the first inductor L1, through the third switch T3 and the fourth diode D4, and finally flows into the second terminal of the first capacitor C1 (as shown by the red arrow in the loop). During this process, the current flowing through the third switch T3 increases linearly due to the current limiting effect of the first inductor L1 and the second inductor L2 in the loop. When the drive pulse ends, the third switch T3 turns off, and the current value on the first inductor L1 rises to its maximum value and then begins to decrease. The Hall effect sensor can monitor the inductor current throughout the process. By setting the switching time t2 of the third switch T3, the voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and determining the inductance values ​​of the first inductor L1 and the second inductor L2, the theoretical current value of the first inductor at the moment the third switch T3 is turned off can be obtained. This value is stored in the control module and compared with the current value collected by the current detection module during the process. The first capacitor C1 and the second capacitor C2 have the same capacitance value, and the voltage across the first capacitor C1 is equal to U1 / 2.

[0062] like Figure 6As shown, for the case where the first switch T1 needs to be tested, since the output port of the inductor cannot be connected to the DC bus - inside the T-type three-level inverter product, the second test branch containing the second test switch KM2 is connected to the second polarity terminal PV2 of the photovoltaic input, that is, connected to the DC bus - through the first inductor L1. After closing the second test switch KM2, a drive pulse is first applied to the first switch T1, turning on the first switch T1. Current flows out from the first terminal of the first capacitor C1, through the first switch T1, and then through the first inductor L1 into the second node PV2 (as shown by the red arrow in the loop). During this process, the current flowing through the first switch T1 increases linearly due to the current limiting effect of the first inductor L1 in the loop. When the drive pulse ends, the first switch T1 turns off, and the current value on the first inductor L1 freewheels through the second diode D2. The current value on the first inductor L1 rises to its maximum value and then begins to decrease. The Hall sensor can monitor the inductor current throughout the process. By setting the switching time t3 of the first switch T1, setting the voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and determining the inductance values ​​of the first inductor L1 and the second inductor L2, the theoretical current value of the current in the first inductor at the moment when the first switch T1 is turned off can be obtained. This value will be stored in the control module and compared with the current value collected by the current detection module during the process.

[0063] like Figure 7As shown, for the case where the fourth switch T4 needs to be tested, since the output port of the inductor cannot be connected to the DC bus - inside the T-type three-level inverter product, the second test branch containing the second test switch KM2 is connected to the second polarity terminal PV2 of the photovoltaic input. The second polarity terminal PV2 of the photovoltaic input is shorted to the DC bus - inside the T-type three-level inverter. After closing the second test switch KM2, a drive pulse is first applied to the fourth switch T4, turning it on. Current flows out from the second terminal of the first capacitor C1, through the fourth switch T4, and then through the third diode D3 and the first inductor L1 into the second node PV2 (as shown by the red arrow). During this process, the current flowing through the fourth switch T4 increases linearly due to the current limiting effect of the first inductor L1 in the circuit. When the drive pulse ends, the fourth switch T4 turns off, and the current value on the first inductor L1 freewheels through the second diode D2, rising to its maximum value and then decreasing. The Hall effect sensor can monitor the inductor current throughout the process. By setting the switching time t4 of the fourth switch T4, the voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and determining the inductance values ​​of the first inductor L1 and the second inductor L2, the theoretical current value of the first inductor at the moment the fourth switch T4 is turned off can be obtained. This value is stored in the control module and compared with the current value collected by the current detection module during the process. The first capacitor C1 and the second capacitor C2 have the same capacitance value, and the voltage across the second capacitor C2 is equal to U1 / 2.

[0064] In a typical T-type three-level inverter, the rated parameters of the third switch T3 and the fourth switch T4 are the same, and the rated parameters of the first switch T1 and the second switch T2 are the same. However, the rated parameters of the third switch T3 / fourth switch T4 are different from those of the first switch T1 / second switch T2. Although the total circuit inductance includes the first inductor L1 and the second inductor L2 when testing the third switch T3 / fourth switch T4, the turn-on time of the switches will be adjusted according to the different rated parameters of the third switch T3 / fourth switch T4.

[0065] The detection circuit of the T-type three-level inverter communicates with the host computer during the test. After the DC power supply is fully charged and the T-type three-level inverter completes its self-test, the T-type three-level inverter notifies the host computer that the switching transistor test can be started. The host computer sends a test start command to the T-type three-level inverter. Inside the T-type three-level inverter, the switching transistors in each phase inverter branch are tested according to the above procedure. After the test, the current in the test circuit is compared with the theoretical current value stored in the T-type three-level inverter itself to screen out the failed switching transistors and anti-parallel diodes and report the fault to the host computer.

[0066] This embodiment exemplifies the sequential testing of the second switch T2, the third switch T3, the first switch T1, and the fourth switch T4. Before testing the second switch T2, the power supply control switch KM is turned on to charge the first capacitor C1 and the second capacitor C2 via DC power. After testing the third switch T3 and before testing the first switch T1, the power supply control switch KM is turned on again to charge the first capacitor C1 and the second capacitor C2. In other embodiments, for any four switches in a phase inverter branch, the first switch T1, the fourth switch T4, the second switch T2, and the third switch T3 can also be tested sequentially. In other embodiments, the four switches can also be tested in other orders. The testing order for the four switches in any phase inverter branch can be set according to requirements and is not specifically limited.

[0067] Figure 8 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the present invention is shown below. Figure 8 , Figure 8 In this circuit, the first terminal of the first switch T1 is the collector, and the second terminal is the emitter; the first terminal of the second switch T2 is the collector, and the second terminal is the emitter; the first terminal of the third switch T3 is the emitter, and the second terminal is the collector; the first terminal of the fourth switch T4 is the emitter, and the second terminal is the collector; and the first terminal of the DC power supply 131 is the positive terminal, and the second terminal is the negative terminal. (Regarding...) Figure 8 The T-type three-level inverter shown controls the first switch T1 and the second test switch KM2 to be turned on when testing the first switch T1; controls the second test switch T2 and the first test switch KM1 to be turned on when testing the second switch T2; controls the third switch T3 and the second test switch KM2 to be turned on when testing the third switch T3; and controls the fourth switch T4 and the first test switch KM1 to be turned on when testing the fourth switch T4.

[0068] Figure 9 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the present invention is shown below. Figure 9 , Figure 9 In the circuit, the first terminal of the first switch T1 is the emitter and the second terminal is the collector; the first terminal of the second switch T2 is the emitter and the second terminal is the collector; the first terminal of the third switch T3 is the collector and the second terminal is the emitter; the first terminal of the fourth switch T4 is the collector and the second terminal is the emitter; and the first terminal of the DC power supply 131 is the negative terminal and the second terminal is the positive terminal. (Regarding...) Figure 9The T-type three-level inverter shown controls the first switch T1 and the second test switch KM2 to be turned on when testing the first switch T1; controls the second test switch T2 and the first test switch KM1 to be turned on when testing the second switch T2; controls the third switch T3 and the second test switch KM2 to be turned on when testing the third switch T3; and controls the fourth switch T4 and the first test switch KM1 to be turned on when testing the fourth switch T4.

[0069] Figure 10 A schematic diagram of the detection circuit of another T-type three-level inverter provided in this embodiment of the present invention is shown below. Figure 10 , Figure 10 In the circuit, the first terminal of the first switch T1 is the emitter and the second terminal is the collector; the first terminal of the second switch T2 is the emitter and the second terminal is the collector; the first terminal of the third switch T3 is the emitter and the second terminal is the collector; the first terminal of the fourth switch T4 is the emitter and the second terminal is the collector; and the first terminal of the DC power supply 131 is the negative terminal and the second terminal is the positive terminal. (Regarding...) Figure 10 The T-type three-level inverter shown controls the first switch T1 and the second test switch KM2 to be turned on when testing the first switch T1; controls the second test switch T2 and the first test switch KM1 to be turned on when testing the second switch T2; controls the third switch T3 and the first test switch KM1 to be turned on when testing the third switch T3; and controls the fourth switch T4 and the second test switch KM2 to be turned on when testing the fourth switch T4.

[0070] Figures 8 to 10 Although the structure of the T-type three-level inverter is similar to... Figure 1 There are slight differences, but the testing principles are similar, so I will not go into details here.

[0071] This utility model embodiment also provides a detection system for a T-type three-level inverter, including the detection circuit for the T-type three-level inverter in any of the above embodiments. Furthermore, the beneficial effects of the detection system for the T-type three-level inverter are the same as those of the detection circuit for the T-type three-level inverter, and will not be repeated here.

[0072] Optionally, the testing system for the T-type three-level inverter also includes an oscilloscope, which is connected to the current detection module to more intuitively display the waveform of the current in the first inductor during the test.

[0073] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A detection circuit for a T-type three-level inverter, applied to a T-type three-level inverter, characterized in that, The T-type three-level inverter includes a photovoltaic input first polarity terminal, a photovoltaic input second polarity terminal, at least one phase output terminal, and an inverter branch corresponding to the output terminal. The inverter branch is connected between the internal nodes of the T-type three-level inverter and the output terminal corresponding to the inverter branch. The detection circuit of the T-type three-level inverter includes: a test power supply module, a control module, a test branch group corresponding to each inverter branch, and a current detection module corresponding to each inverter branch. The test branch group includes a first test branch and a second test branch. The first test branch is connected in series between the first polarity terminal of the photovoltaic input and the output terminal corresponding to the inverter branch of the first test branch. The second test branch is connected in series between the second polarity terminal of the photovoltaic input and the output terminal corresponding to the inverter branch of the second test branch. The test power supply module is connected between the first polarity terminal of the photovoltaic input and the second polarity terminal of the photovoltaic input, and the test power supply module is also connected to the control module; The current detection module is configured to detect the current in the inverter branch; The inverter branch includes at least one switching transistor. The control module is connected to the control terminal of the first test branch and the control terminal of the second test branch, respectively, and is configured to control one of the first test branch and the second test branch corresponding to the inverter branch to which the switching transistor under test belongs to be turned on according to the switching transistor under test.

2. The detection circuit of the T-type three-level inverter according to claim 1, characterized in that, The test power supply module includes a DC power supply and a power supply control switch; The first terminal of the power supply control switch is connected to the first electrode of the DC power supply, the second terminal of the power supply control switch is connected to the first polarity terminal of the photovoltaic input, and the control terminal of the power supply control switch is connected to the control module. The second terminal of the DC power supply is connected to the second polarity terminal of the photovoltaic input.

3. The detection circuit for the T-type three-level inverter according to claim 2, characterized in that, The power supply control switch is a contactor.

4. The detection circuit of the T-type three-level inverter according to claim 1, characterized in that, The first test branch includes a first test switch, the first end of the first test switch is connected to the first polarity terminal of the photovoltaic input, the second end of the first test switch is connected to the output terminal of the inverter branch corresponding to the first test switch, and the control terminal of the first test switch is connected to the control module. The second test branch includes a second test switch. The first end of the second test switch is connected to the second polarity terminal of the photovoltaic input, the second end of the second test switch is connected to the output terminal of the inverter branch corresponding to the second test switch, and the control terminal of the second test switch is connected to the control module.

5. The detection circuit of the T-type three-level inverter according to claim 4, characterized in that, Both the first test switch and the second test switch are contactors.

6. The detection circuit for the T-type three-level inverter according to any one of claims 1-5, characterized in that, The T-type three-level inverter further includes a first capacitor, a second capacitor, and a second inductor. The first end of the second inductor is connected to the first polarity terminal of the photovoltaic input, the second end of the second inductor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second polarity terminal of the photovoltaic input. The first end of the inverter branch is connected to the first end of the first capacitor, the second end of the inverter branch is connected to the second end of the first capacitor, the third end of the inverter branch is connected to the second end of the second capacitor, and the fourth end of the inverter branch is connected to the corresponding output end of the inverter branch.

7. The detection circuit of the T-type three-level inverter according to claim 6, characterized in that, The inverter branch of any phase includes a first inductor, two switching transistors connected in series between the second end of the first capacitor and the first end of the first inductor and in opposite directions, and two switching transistors connected in series between the first end of the first capacitor and the second end of the second capacitor and in the same direction. The second end of the first inductor is connected to the corresponding output terminal of the inverter branch.

8. The detection circuit of the T-type three-level inverter according to claim 7, characterized in that, The current detection module includes a Hall sensor, which is mounted on the line at the first end of the first inductor.

9. A detection system for a T-type three-level inverter, characterized in that, The detection circuit includes the T-type three-level inverter as described in any one of claims 1-8.

10. The detection system for a T-type three-level inverter according to claim 9, characterized in that, It also includes an oscilloscope, which is connected to the current detection module.

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