Driving substrate, electronic paper display device, and electronic device

Abstract

This utility model discloses a driving substrate, an electronic paper display device, and an electronic device, relating to the technical field of display devices. The driving substrate includes multiple pixel units, each pixel unit including a bottom substrate, a thin film transistor assembly, and a driving electrode. The driving electrode is electrically connected to the thin film transistor. The thin film transistor assembly includes a first gate, a first semiconductor, and a second semiconductor. The first semiconductor and the second semiconductor are spaced apart along a first direction and disposed in the same structural layer. The first semiconductor and the second semiconductor are stacked with the first gate along a second direction.

Description

Technical Field

[0001] This utility model relates to a display device, and more particularly to a driving substrate, an electronic paper display device, and an electronic device. Background Technology

[0002] Electronic paper, with its passive light emission and paper-like image display characteristics, is widely used in display fields such as e-readers and electronic tags.

[0003] In related technologies, the current in electronic paper display devices is controlled by thin-film transistors. When the thin-film transistor in a pixel unit is short-circuited or damaged, that pixel unit will fail to display properly. Utility Model Content

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a driving substrate to improve the yield rate of electronic paper display devices.

[0005] According to a first aspect of the present invention, a driving substrate includes a plurality of pixel units, each pixel unit including a bottom substrate, a thin film transistor assembly and a driving electrode, wherein the driving electrode is electrically connected to the thin film transistor.

[0006] The thin-film transistor assembly includes a first gate, a first semiconductor, and a second semiconductor. The first semiconductor and the second semiconductor are spaced apart along a first direction. The first semiconductor and the second semiconductor are disposed in the same structural layer, and the first semiconductor and the second semiconductor are stacked with the first gate along a second direction, respectively.

[0007] According to some embodiments of the present invention, the driving substrate further includes an elastic abutment member, which is connected to the fixing member on the side facing the receiving cavity.

[0008] In some embodiments, the thin-film transistor assembly further includes a first source, a first drain, a second source, and a second drain;

[0009] The first source and the first drain are connected along the second direction and disposed on opposite sides of the first semiconductor;

[0010] The second source and the second drain are connected along the second direction and disposed on opposite sides of the second semiconductor;

[0011] The first source and the second source are partially connected in one structure, and the first drain and the second drain are partially connected in one structure.

[0012] In some embodiments, the driving substrate includes a first metal layer and a second metal layer stacked together, the first gate is formed on the first metal layer, and the first source, the second source, the first drain and the second drain are formed on the second metal layer.

[0013] In some embodiments, the thin-film transistor assembly further includes a second gate, a third semiconductor, and a fourth semiconductor, wherein the third semiconductor and the fourth semiconductor are disposed in the same layer and spaced apart along the first direction, and the third semiconductor and the fourth semiconductor are respectively stacked with the second gate in the second direction.

[0014] In some embodiments, the first gate and the second gate are spaced apart along a second direction, and there is an angle between the first direction and the second direction.

[0015] In some embodiments, the thin-film transistor assembly further includes a first source, a first drain, a second source, a second drain, a first interconnect layer, and a second interconnect layer;

[0016] In the first direction, the first source, the third semiconductor, the first interconnect layer, the first semiconductor, and the first drain are sequentially connected and disposed;

[0017] In the first direction, the second source, the fourth semiconductor, the second interconnect layer, the second semiconductor, and the second drain are sequentially connected and disposed;

[0018] The first source and the second source are partially connected in one structure, and the first drain and the second drain are partially connected in one structure.

[0019] In some embodiments, the driving substrate includes a first metal layer and a second metal layer stacked together, the first gate and the second gate are formed on the first metal layer, and the first source, the second source, the first drain, the second drain, the first interconnect layer and the second interconnect layer are formed on the second metal layer.

[0020] In some embodiments, the driving substrate further includes an insulating layer located between the thin-film transistor assembly and the driving electrode in the second direction, the insulating layer having a through hole, and the driving electrode being electrically connected to the thin-film transistor assembly at the through hole.

[0021] A second aspect of this application provides an electronic paper display device, which includes a top substrate, a driving substrate as described in any one of the first aspects of this application, and a dielectric layer. The top substrate includes a top electrode; the dielectric layer includes an electronic paste and is located between the top electrode and the driving electrode.

[0022] A third aspect of this application provides an electronic device including an electronic paper display device as provided in the second aspect of this application.

[0023] As can be seen from the above embodiments, the thin-film transistor assembly in this application uses a first semiconductor and a second semiconductor that are spaced apart. When the conductive path formed by one of the semiconductors becomes abnormal, the normal use of the pixel unit can be maintained through the conductive path formed by the other semiconductor, so that the current can be transmitted normally through the conductive path. This improves the stability of the thin-film transistor assembly and reduces the risk of leakage current in the driving electrode to a certain extent, thereby improving the yield of the product.

[0024] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0026] Figure 1 This is a schematic diagram of the hierarchical structure of the electronic paper display device provided in the embodiments of this application;

[0027] Figure 2 This is a planar schematic diagram of the internal structure of any pixel unit in Embodiment 1 of this utility model;

[0028] Figure 3 for Figure 2 A schematic diagram of the planar structure of the first metal layer, the first semiconductor, and the second semiconductor within any pixel unit;

[0029] Figure 4 for Figure 2 A schematic diagram of the planar structure of the first metal layer, the first semiconductor, the second semiconductor, and the second metal layer within any pixel unit;

[0030] Figure 5 This is a planar schematic diagram of the internal structure of any pixel unit in Embodiment 2 of this utility model;

[0031] Figure 6 for Figure 5 A schematic diagram of the planar structure of the first metal layer, the first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor within any pixel unit;

[0032] Figure 7 for Figure 5 A schematic diagram of the planar structure of the first metal layer, the first semiconductor, the second semiconductor, the third semiconductor, the fourth semiconductor, and the second metal layer within any pixel unit;

[0033] Figure 8 for Figure 5 A cross-sectional view of the marked AA within any pixel unit in the image;

[0034] Figure 9 A schematic diagram of an electronic device provided in an embodiment of this application.

[0035] Reference numerals: 100, electronic paper display device; 101, driving substrate; 102, dielectric layer; 103, top substrate; 110, first metal layer; 111, first gate; 112, second gate; 120, second metal layer; 121, first source; 122, second source; 123, first drain; 124, second drain; 125, first interconnect layer; 126, second interconnect layer; 131, first semiconductor; 132, second semiconductor; 133, third semiconductor; 134, fourth semiconductor; 140, insulating layer; 141, via; 150, driving electrode; 160, bottom substrate; 200, electronic device; 300, first direction; 400, second direction; 500, third direction. Detailed Implementation

[0036] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0037] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0038] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0039] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0040] In the description of this utility model, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0041] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0042] Electronic paper (ePaper) is a novel reflective display technology. Its core technology uses electronic ink to display images and text, achieving a display effect close to traditional paper. It boasts unique advantages such as paper-like display, low power consumption, and eye-friendliness. Major applications of ePaper include e-book readers, electronic tags, educational equipment, smart wearable devices, IoT displays, and advertising and information displays. With continuous technological advancements, the application scenarios of ePaper are expected to expand further, making it one of the important future development directions for display technology.

[0043] In related technologies, the electronic paper display device 100 uses a substrate (array) as a driving switch to control the electric field, and uses the electric field to control the movement of particles in the electronic paste to present the desired image. However, when the thin-film transistors in the substrate malfunction, the pixel unit where the thin-film transistor is located may not work properly, resulting in display abnormalities. The substrate (array) is the driving substrate 101 in this application.

[0044] To address the aforementioned issues, this application provides an electronic paper display device 100, wherein any thin-film transistor assembly of the electronic paper display device 100 includes at least two semiconductors to form two parallel conductive paths, so that if any conductive path formed by one of them malfunctions, the other can form a conductive path to maintain the normal operation of the pixel unit where the thin-film transistor assembly is located.

[0045] For example, the electronic paper display device 100 provided in this application can be a micro-cavity electronic paper display (MED) or other electronic paper display devices 100, without specific limitations.

[0046] Microcavity electronic paper displays (MEDs) primarily involve creating a dam structure on the surface of a thin-film transistor (TFT) assembly to surround each pixel unit. An electronic paste containing black and white particles for imaging is then used to fill the dielectric layer 102, and finally, the display is encapsulated with a top glass panel. The cavity formed by the multiple dam structures in the MED is thus called the microcavity structure. MEDs can control the color changes of the particles in the electronic paste using an electric field, achieving high contrast, high reflectivity, and a wide color gamut display effect through particle reflection.

[0047] Please see Figure 1 The first aspect of this application provides a driving substrate 101, which can be adapted to be applied to an electronic paper display device 100. The electronic paper display device 100 includes a top substrate 103, a driving substrate 101, and a dielectric layer 102.

[0048] The top substrate 103 includes a top electrode, and the driving substrate 101 includes multiple pixel units. Each pixel unit includes a bottom substrate 160, a thin-film transistor assembly, and a driving electrode 150. The driving electrode 150 is electrically connected to the thin-film transistor. The dielectric layer 102 includes an electronic paste and is located between the top electrode and the driving electrode 150. Current is controlled by the thin-film transistor assembly to create an electric field between the driving electrode 150 and the top electrode, thereby controlling the movement of charged particles in the electronic paste to display an image. An insulating layer 140 is also disposed between the thin-film transistor assembly and the driving electrode 150. A through-hole 141 is formed in the insulating layer 140, and the driving electrode 150 is electrically connected to the thin-film transistor assembly at the through-hole 141.

[0049] Please see Figure 2The thin-film transistor assembly includes a first gate 111, a first semiconductor 131, and a second semiconductor 132. The first semiconductor 131 and the second semiconductor 132 are spaced apart along a first direction 300, disposed in the same structural layer, and stacked with the first gate 111 along a second direction 400. If either the spaced-apart first semiconductor 131 or the second semiconductor 132 malfunctions, the other can maintain normal operation. The second direction 400 is the thickness direction of the driving substrate 101.

[0050] Please see Figure 3 , Figure 4 In one specific embodiment, the thin-film transistor assembly further includes a first source 121, a first drain 123, a second source 122, and a second drain 124. The first source 121 and the first drain 123 are connected and disposed on opposite sides of the first semiconductor 131 along a third direction 500, and the second source 122 and the second drain 124 are connected and disposed on opposite sides of the second semiconductor 132 along a third direction 500.

[0051] Among them, the first source 121 and the second source 122 are partially connected in one piece, and the first drain 123 and the second drain 124 are partially connected in one piece.

[0052] It is understood that the first semiconductor 131, the first gate 111, the first source 121, and the first drain 123 can form a single thin-film transistor, namely the first thin-film transistor, and the second semiconductor 132, the first gate 111, the second source 122, and the second drain 124 can form a single thin-film transistor, namely the second thin-film transistor. The first thin-film transistor and the second thin-film transistor are connected in parallel at the first source 121 and the second source 122, and in parallel at the first drain 123 and the second drain 124. If either the first thin-film transistor or the second thin-film transistor experiences an open circuit or other abnormal condition that prevents normal operation, the other transistor can be used to maintain operation and allow the pixel unit to be displayed normally.

[0053] In this embodiment, any pixel unit is a single-gate structure, that is, the thin-film transistor assembly includes only one gate, in which case the power consumption rate of the driving substrate 101 is low.

[0054] Please see Figure 5 , Figure 6In another specific embodiment, the thin-film transistor assembly further includes a second gate 112, a third semiconductor 133, and a fourth semiconductor 134. The third semiconductor 133 and the fourth semiconductor 134 are disposed on the same layer and spaced apart along the first direction 300, and the third semiconductor 133 and the fourth semiconductor 134 are stacked with the second gate 112 along the second direction 400. Compared with the previous embodiment, any pixel unit in this embodiment also includes a second gate 112. The first gate 111 and the second gate 112 are spaced apart along the third direction 500, and there is an angle between the first direction 300 and the third direction 500, which is usually 90°. If either the spaced third semiconductor 133 or the fourth semiconductor 134 malfunctions and cannot be used normally, the other can maintain normal operation.

[0055] Please see Figure 7 , Figure 8 The thin-film transistor assembly also includes a first source 121, a first drain 123, a second source 122, a second drain 124, a first interconnect layer 125, and a second interconnect layer 126.

[0056] In the first direction 300, a first source 121, a third semiconductor 133, a first interconnect layer 125, and a first drain 123 are sequentially connected. In the first direction 300, a second source 122, a fourth semiconductor 134, a second interconnect layer 126, a second semiconductor 132, and a second drain 124 are sequentially connected. Partial structures of the first source 121 and the second source 122 are integrally connected, as are partial structures of the first drain 123 and the second drain 124.

[0057] Specifically, the first source 121 is connected to the side of the third semiconductor 133 away from the first semiconductor 131, and the first drain 123 is connected to the side of the first semiconductor 131 away from the third semiconductor 133. The two ends of the first connection layer 125 are connected to the first semiconductor 131 and the third semiconductor 133, respectively. It can be understood that, compared to the previous embodiment, where the first semiconductor 131 is electrically connected to the third semiconductor 133 through the first connection layer 125, and then electrically connected to the first source 121 through the third semiconductor 133, correspondingly, the third semiconductor 133 is electrically connected to the first drain 123 in the same reverse manner, so that the first semiconductor 131, the first gate 111, the first source 121, and the first drain 123 form a first thin-film transistor, and the third semiconductor 133, the second gate 112, the first source 121, and the first drain 123 form a third thin-film transistor.

[0058] The second source 122 is connected to the side of the fourth semiconductor 134 away from the second semiconductor 132, and the second drain 124 is connected to the side of the second semiconductor 132 away from the fourth semiconductor 134. The two ends of the second connection layer 126 are connected to the second semiconductor 132 and the fourth semiconductor 134, respectively. It can be understood that, compared with the previous embodiment, the second semiconductor 132 is electrically connected to the fourth semiconductor 134 through the second connection layer 126, and then electrically connected to the second source 122 through the fourth semiconductor 134. Correspondingly, the fourth semiconductor 134 is electrically connected to the second drain 124 in the same reverse manner, so that the second semiconductor 132, the first gate 111, the second source 122 and the second drain 124 form a second thin-film transistor, and the fourth semiconductor 134, the second gate 111, the second source 122 and the second drain 124 form a fourth thin-film transistor.

[0059] In this configuration, portions of the structures of the first source 121 and the second source 122 are integrally connected, portions of the structures of the first drain 123 and the second drain 124 are integrally connected, and the first thin-film transistor and the second thin-film transistor are connected in parallel at the first source 121 and the second source 122, and also in parallel at the first drain 123 and the second drain 124. The third thin-film transistor and the fourth thin-film transistor are connected in parallel at the first source 121 and the second source 122, and also in parallel at the first drain 123 and the second drain 124.

[0060] If either the first or second thin-film transistor experiences an open circuit or other abnormality, rendering it unusable, the other transistor can form a conductive path to maintain operation and allow the pixel unit to display normally. Similarly, if either the third or fourth thin-film transistor experiences an open circuit or other abnormality, rendering it unusable, the other transistor can form a conductive path to maintain operation and allow the pixel unit to display normally.

[0061] In this embodiment, any pixel unit is a dual-gate structure, that is, the thin-film transistor assembly includes two gates spaced apart, in which case the charging rate of the driving substrate 101 is higher.

[0062] For example, a dielectric layer 102 is disposed between a top substrate 103 and a driving substrate 101, and the dielectric layer 102 forms a sealed cavity that contains an electronic paste, which includes a filling liquid and conductive particles distributed in the filling liquid.

[0063] For example, black and white particles can have different electrical charges. For instance, white particles may carry a negative charge and black particles may carry a positive charge; or white particles may carry a positive charge and black particles may carry a negative charge. No specific limitation is made here.

[0064] Black and white particles can undergo electrophoresis under the influence of voltage, controlling their positional distribution within the dielectric layer 102 and thus creating different grayscale levels on the screen surface. Utilizing the principle of attraction between positive and negative particles, when an electric field is applied, corresponding black or white particles move to the top of the dielectric layer 102, allowing the user to see black or white within that area (pixel unit). Applying different voltages to the same dielectric layer 102 will result in a half-black, half-white appearance at the top, allowing the user to see gray within that area (pixel unit).

[0065] Specifically, the first electrode layer 11 and the second electrode layer 21 work together to drive the black and white particles in the dielectric layer 102 to arrange themselves so as to display and switch between different images.

[0066] In some embodiments, the driving substrate 101 includes a first metal layer 110 and a second metal layer 120 stacked together. The first gate 111 in Embodiment 1 and the first gate 111 and second gate 112 in Embodiment 2 are both formed on the first metal layer 110, that is, all the above components are formed by processing the first metal layer 110, and the processing method can be etching or other processing methods. The first source 121, the second source 122, the first drain 123, and the second drain 124 in Embodiment 1 and the first source 121, the second source 122, the first drain 123, the second drain 124, the first interconnect layer 125, and the second interconnect layer 126 in Embodiment 2 are formed on the second metal layer 120, that is, all the above components are formed by processing the second metal layer 120, and the processing method can be etching or other processing methods.

[0067] The second aspect of this application also provides an electronic paper display device 100. It is understood that the electronic paper display device 100 is the same as the electronic paper display device 100 used on the driving substrate 101 in the first aspect of this application, and will not be described again here.

[0068] Please see Figure 9 The third aspect of this application also provides an electronic device 200, which includes the electronic paper display device 100 as provided in the second aspect of this application, which will not be described again here.

[0069] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A driving substrate, characterized in that, It includes multiple pixel units, each pixel unit including a bottom substrate, a thin film transistor assembly and a driving electrode, wherein the driving electrode is electrically connected to the thin film transistor; The thin-film transistor assembly includes a first gate, a first semiconductor, and a second semiconductor. The first semiconductor and the second semiconductor are spaced apart along a first direction. The first semiconductor and the second semiconductor are disposed in the same structural layer, and the first semiconductor and the second semiconductor are stacked with the first gate along a second direction, respectively.

2. The driving substrate according to claim 1, characterized in that, The thin-film transistor assembly further includes a first source, a first drain, a second source, and a second drain; The first source and the first drain are connected along the second direction and disposed on opposite sides of the first semiconductor; The second source and the second drain are connected along the second direction and disposed on opposite sides of the second semiconductor; The first source and the second source are partially connected in one structure, and the first drain and the second drain are partially connected in one structure.

3. The driving substrate according to claim 2, characterized in that, The driving substrate includes a first metal layer and a second metal layer stacked together, the first gate is formed on the first metal layer, and the first source, the second source, the first drain and the second drain are formed on the second metal layer.

4. The driving substrate according to claim 1, characterized in that, The thin-film transistor assembly further includes a second gate, a third semiconductor, and a fourth semiconductor. The third semiconductor and the fourth semiconductor are disposed on the same layer and spaced apart along the first direction, and the third semiconductor and the fourth semiconductor are respectively stacked with the second gate in the second direction.

5. The driving substrate according to claim 4, characterized in that, The first gate and the second gate are spaced apart along a third direction, and there is an angle between the first direction and the third direction.

6. The driving substrate according to claim 5, characterized in that, The thin-film transistor assembly further includes a first source, a first drain, a second source, a second drain, a first interconnect layer, and a second interconnect layer; In the first direction, the first source, the third semiconductor, the first interconnect layer, the first semiconductor, and the first drain are sequentially connected and disposed; In the first direction, the second source, the fourth semiconductor, the second interconnect layer, the second semiconductor, and the second drain are sequentially connected and disposed; The first source and the second source are partially connected in one structure, and the first drain and the second drain are partially connected in one structure.

7. The driving substrate according to claim 6, characterized in that, The driving substrate includes a first metal layer and a second metal layer stacked together. The first gate and the second gate are formed on the first metal layer, and the first source, the second source, the first drain, the second drain, the first interconnect layer and the second interconnect layer are formed on the second metal layer.

8. The driving substrate according to claim 1, characterized in that, The driving substrate further includes an insulating layer located between the thin-film transistor assembly and the driving electrode in the second direction. The insulating layer has a through hole, and the driving electrode is electrically connected to the thin-film transistor assembly at the through hole.

9. An electronic paper display device, characterized in that, include: The top substrate includes a top electrode; The driving substrate as described in any one of claims 1-8; A dielectric layer, comprising an electronic paste, is located between the top electrode and the driving electrode.

10. An electronic device, characterized in that, Includes the electronic paper display device as described in claim 9.

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