Negative voltage generation circuit based on multi-stage regulator control

Abstract

The purpose of this invention is to solve the technical problems of inconsistent output voltage accuracy and difficulty in accurately controlling the power-on sequence in existing technologies, which can even lead to startup failures. It provides a negative voltage generation circuit based on multi-stage voltage regulator control. The circuit employs a three-stage LDO architecture consisting of a front-stage positive LDO, a front-stage negative LDO, and a rear-stage negative LDO. The input terminals of the three-stage LDO architecture are connected to an external power supply unit, and the enable input terminal is connected to an external control unit. The front-stage positive LDO steps down the positive input voltage provided by the external power supply unit and outputs it to the rear-stage negative LDO. The front-stage negative LDO boosts the negative input voltage provided by the external power supply unit and outputs it to the rear-stage negative LDO. A resistor divider network is connected between the output terminal of the rear-stage negative LDO and ground. This resistor divider network, in conjunction with the adjustment pin ADJ of the rear-stage negative LDO, enables precise setting of the output voltage, and the output terminal is used to output the generated set negative voltage.

Description

Technical Field

[0001] This utility model relates to a negative voltage generation circuit, specifically a negative voltage generation circuit based on multi-stage voltage regulator control. Background Technology

[0002] In electronic systems, some high-performance sensors require precise negative voltage power supply and strict power-on sequence. For example, the Raycus 12K image detector requires a precise -0.7V power supply. Existing technologies typically use an operational amplifier combined with a transistor architecture to generate the negative voltage for power supply. However, the consistency of discrete components in this architecture is poor, which can easily lead to insufficient output voltage accuracy. Furthermore, the power-on sequence is difficult to control precisely, and improper power-on sequence management may result in incomplete negative voltage establishment or even damage to sensitive devices. In addition, the layout and parasitic parameters of discrete components may introduce additional power supply noise, affecting system stability.

[0003] In aerospace applications, the reliability of power systems is paramount. Satellites, probes, and other equipment typically employ multi-stage power management strategies, requiring strict power-up sequences. For example, FPGA power supply must follow the sequence 1.0V→1.8V→IO (2.5V / 3.3V), otherwise logic errors or device damage may occur. Simultaneously, power supplies in aerospace applications must possess radiation resistance and low noise characteristics to meet the demands of long lifespan and high stability. However, while existing LDO chips can provide stable negative voltage outputs, a single LDO chip cannot directly generate a specific voltage, and its enable control logic is complex. Different LDO chips have different enable level requirements, and improper control may lead to startup failure. Furthermore, LDO chips may exhibit unstable output voltage under no-load conditions, thus traditional solutions require additional load resistors, increasing system complexity. Utility Model Content

[0004] The purpose of this invention is to solve the technical problems of insufficient voltage accuracy of existing negative voltage power supply output, difficulty in accurately controlling the power-on sequence, and even leading to startup failure, and to provide a negative voltage generation circuit based on multi-stage voltage regulator control.

[0005] To achieve the above objectives, the technical solution provided by this utility model is as follows:

[0006] A negative voltage generation circuit based on multi-stage voltage regulator control, characterized in that it includes:

[0007] The three-stage LDO architecture consists of a pre-stage positive LDO, a pre-stage negative LDO, and a post-stage negative LDO. The input terminal of the three-stage LDO architecture is connected to an external power supply unit, and the enable input terminal is connected to an external control unit.

[0008] The input terminal of the pre-stage positive voltage LDO is connected to the positive output terminal of the external power supply unit, its ground terminal is connected to the output terminal of the pre-stage negative voltage LDO, and its output terminal is connected to the ground terminal of the post-stage negative voltage LDO. This is used to step down the positive input voltage provided by the external power supply unit and output it to the post-stage negative voltage LDO.

[0009] The input terminal of the pre-stage negative voltage LDO is connected to the negative output terminal of the external power supply unit, its ground terminal is grounded, and its output terminal is connected to the input terminal of the post-stage negative voltage LDO. It is used to boost the negative input voltage provided by the external power supply unit and output it to the post-stage negative voltage LDO.

[0010] The ground terminal of the subsequent negative voltage LDO is grounded, and a resistor voltage divider network is connected between its output terminal and the ground terminal. The resistor voltage divider network is used to sample the output voltage and, together with the adjustment pin ADJ of the subsequent negative voltage LDO, realizes the precise setting of the output voltage of the circuit system. The output terminal is used to output the generated set negative voltage, and the set negative voltage range is -0.5V to -1V.

[0011] The enable signal output pin (IO pin) of the external control unit is connected to the INH pins of the preceding positive voltage LDO and the preceding negative voltage LDO. The INH pin of the preceding negative voltage LDO is connected to an external pull-down resistor, and the INH pin of the following negative voltage LDO is connected to its high-level output and ground. This is used to manage the power-on sequence of each LDO in the three-stage LDO architecture, ensuring that the potential rises gradually from a low potential. Using the same type of LDO device simplifies material management, not only simplifying the circuit structure but also improving system reliability.

[0012] Furthermore, the resistor divider network includes resistors R1, R2, and R3;

[0013] One end of resistor R1 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is connected to one end of resistor R2 and connected to the adjustment pin ADJ. The other end of resistor R2 is grounded. One end of resistor R3 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is grounded.

[0014] Furthermore, the pre-stage positive voltage LDO steps down the positive input voltage to output a reference voltage V. out1 The calculation formula is:

[0015]

[0016] Where: R1 and R2 are the resistance values ​​of resistors R1 and R2, respectively; 1.227 is the voltage value of the adjustment pin ADJ;

[0017] The ratio between resistors R1 and R2 is set by adjusting the value of resistor R2, so that the reference voltage V... out1It conforms to its preset value; the reference voltage V out1 On the one hand, it serves as the positive reference ground for the subsequent negative pressure LDO, and on the other hand, it serves as the reference potential platform for the enable signal sent by the subsequent external control unit;

[0018] The preceding negative voltage LDO uses the boosted negative input voltage as the input voltage of the following negative voltage LDO, and also provides the initial negative voltage condition for the following negative voltage LDO during the initial power-on phase of the circuit system.

[0019] Furthermore, the output voltage V of the subsequent negative voltage LDO out2 The calculation formula is:

[0020]

[0021] Where: GND is the ground voltage of the subsequent negative voltage LDO; R3 is the resistance of resistor R3; R4 = R1 / R2; 1.227 is the voltage value of the adjustment pin ADJ;

[0022] The ratio of resistors R3 and R4 is set by adjusting the values ​​of resistors R2 and R3, so that the output voltage value V is... out2 It conforms to its preset output value.

[0023] Furthermore, R1 is a 1kΩ resistor, used to provide a minimum load current of 1mA under no-load conditions, in order to avoid output instability of the three-stage LDO architecture.

[0024] Furthermore, when the ground terminal of the subsequent negative voltage is grounded, the voltage value output by the adjustment pin ADJ is always -1.227V.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) This utility model adopts a three-stage LDO architecture consisting of a front-stage positive voltage LDO, a front-stage negative voltage LDO, and a rear-stage negative voltage LDO. Through the collaborative work between each LDO chip, the output voltage of the circuit system of this utility model is precisely controlled by the resistor voltage divider network in conjunction with the adjustment pin ADJ to provide the negative voltage required to power the module to be powered on. At the same time, it can precisely manage the power-on sequence of the external power supply unit and each LDO chip according to the enable signal sent by the external control unit, ensuring that the potential is established from low to high, thereby improving the stability and consistency of the circuit system.

[0027] (2) The resistor voltage divider network connected between the output terminal and ground terminal of the negative voltage LDO in this invention consists of resistors R1, R2 and R3. Among them, resistor R1 is a 1kΩ resistor, which allows the circuit system of this invention to reasonably set the voltage divider resistor value and avoid the problem of each LDO chip being unloaded while ensuring the output voltage accuracy. No additional load design is required, and the static power consumption and hardware complexity of the circuit system are reduced.

[0028] (3) The circuit system of this utility model has a compact structure, strong adaptability and high integration, and is easy to deploy quickly. Compared with the existing negative voltage scheme composed of operational amplifier + transistor, the circuit system of this utility model is better in terms of output voltage ripple control, and has a stronger ability to suppress power supply interference and voltage fluctuation. Attached Figure Description

[0029] Figure 1 This is a circuit system structure diagram of an embodiment of a negative voltage generation circuit based on multi-stage voltage regulator control according to this utility model;

[0030] Figure 2 This is a partial circuit diagram of the negative voltage LDO in the embodiment of this utility model;

[0031] Figure 3 This is a schematic diagram of the voltage output timing of the circuit system in an embodiment of this utility model. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] This embodiment uses the Raycus 12K image detector as an example. The power supply to the control system FPGA chip must follow the sequence of 1.0V→1.8V→10 (2.5V / 3.3V). The power-on sequence when providing a -0.7V negative voltage to the Raycus 12K image detector is as follows: Figure 3 As shown, this embodiment provides a negative voltage generation circuit based on multi-stage voltage regulator control to provide a precise -0.7V voltage for the Ruixin Microelectronics 12K image detector, addressing the power-on sequence of the FPGA chip. Figure 1As shown, the circuit specifically includes a pre-stage positive voltage LDO (LW4913), a pre-stage negative voltage LDO (LW7913), and a post-stage negative voltage LDO (LW7913). The output terminal of the pre-stage positive voltage LDO is connected to the ground terminal of the post-stage negative voltage LDO, and the ground terminal is connected to the output terminal of the pre-stage negative voltage LDO. The output terminal of the pre-stage negative voltage LDO is connected to the input terminal of the post-stage negative voltage LDO, and its ground terminal is grounded. The ground terminal of the post-stage negative voltage LDO is grounded, and a resistor voltage divider network is connected between its output terminal and the ground terminal. The circuit is powered by the positive and negative output terminals of the external power supply unit. The input terminals are connected to the input terminals of the preceding positive and negative LDOs, respectively, providing a 5V voltage source for the circuit system. An FPGA chip is used as an external control unit. The enable signal output of the FPGA chip is connected to the INH pins of the preceding positive and negative LDOs. The INH pin of the subsequent negative LDO is connected to its high-level output terminal and ground, used to manage the power-on sequence of each LDO in the three-stage LDO architecture, ensuring that the potential rises gradually from low to high. A filter capacitor C is also connected to the input terminal of the subsequent negative LDO. IN And grounded.

[0034] like Figure 2 As shown, the resistor divider network includes resistors R1, R2, and R3, and a filter capacitor C. OUT One end of resistor R1 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is connected to one end of resistor R2 and connected to the adjustment pin ADJ of the subsequent negative voltage LDO. The other end of resistor R2 is grounded; one end of resistor R3 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is grounded; filter capacitor C OUT One end is connected to the output terminal of the subsequent negative voltage LDO, and the other end is grounded; it can sample the output voltage of the output terminal of the subsequent negative voltage LDO, and output the sampled voltage to the adjustment pin ADJ combined with the resistor for precise voltage division, so as to realize the accurate setting of the output voltage of the system circuit; R1 is a 1kΩ resistor, which is intended to naturally share the load of about 1mA, eliminating the need for an external dummy load circuit specially designed to prevent no-load, and reducing the static power consumption and hardware complexity of the circuit system.

[0035] The voltage generation principle of this circuit system is as follows:

[0036] 1. First-stage voltage regulator

[0037] The preamplifier positive voltage LDO (LW4913) is supplied with a +5V input voltage V from an external power supply unit. in1 Perform voltage reduction, and then convert the reduced reference voltage V out1 The voltage V is output from its output terminal and transmitted to the ground terminal of the subsequent negative voltage LDO (LW7913) as a reference potential platform for the enable signal sent by the subsequent external control unit. Simultaneously, the ground terminal of the subsequent negative voltage LDO (LW7913) is grounded. Therefore, this reference voltage V...out1 As the positive reference ground of the subsequent negative voltage LDO (LW7913), it ensures that the circuit system has a stable bias; its calculation formula is:

[0038]

[0039] Where: R1 and R2 are the resistance values ​​of resistors R1 and R2, respectively; 1.227 is the voltage value of the adjustment pin ADJ; the ratio of resistors R1 and R2 is set by adjusting the resistance value of resistor R2, so that the reference voltage V... out1 It meets its preset value.

[0040] 2. Second-stage voltage regulation

[0041] The preamplifier negative voltage LDO (LW7913) converts the -5V input voltage V in0 After being boosted, the voltage V becomes the input voltage V of the subsequent negative voltage LDO. out0 At the same time, it provides the initial negative voltage condition as a subsequent negative voltage LDO during the initial power-on stage of the circuit system.

[0042] 3. Third-stage voltage regulation

[0043] The reference voltage V output from the front-end positive voltage LDO (LW4913) out1 As the positive reference ground of the subsequent negative voltage LDO (LW7913), the voltage output of the preceding negative voltage LDO (LW7913) is used as the input voltage of the subsequent negative voltage LDO (LW7913). R4 is set to R1 / R2. The ratio of resistors R1 and R2 is set by adjusting the value of resistor R2. The output voltage obtained after voltage division by the voltage divider network through its adjustment pin ADJ is...

[0044]

[0045] Where: R3 is the resistance value of resistor R3; 1.227 is the voltage value of the adjustment pin ADJ; the ratio of resistor R3 to R4 is set by adjusting the resistance values ​​of resistor R2 and resistor R3.

[0046] This circuit system obtains a negative voltage higher than -1.2V by connecting the ground terminal of the subsequent negative voltage LDO (LW7913) to V+, but only if V+-1.227>0.

[0047] Because the Ruixin Microelectronics 12K image detector requires an input voltage of -0.7V and a maximum current of 22mA, and has a strict power-on sequence, although the existing op-amp + transistor solution can meet the requirements, the power-on sequence is not easy to control, and the consistency of discrete components is not easy to guarantee. Therefore, a negative voltage generation circuit based on multi-stage voltage regulator control is used. According to the FPGA chip's power supply needs to follow the sequence of 1.0V→1.8V→10 (2.5V / 3.3V), the above-mentioned negative voltage generation circuit based on multi-stage voltage regulator control is used for power supply. The voltage output diagram of each stage of the circuit system during the power supply process is shown in the figure. Figure 3 As shown, the negative voltage generation circuit is used as follows:

[0048] S1. Set the resistance of resistor R2 to 1.27kΩ and the resistance of resistor R3 to 1.kΩ.

[0049] S2. During the core voltage power supply stage of the FPGA chip, the external power supply unit first connects a -5V input voltage to the input terminal of the front-end negative voltage LDO. The front-end positive voltage LDO is not powered on. At this time, the INH pin of the front-end negative voltage LDO is in a pull-down state, which triggers the front-end negative voltage LDO to conduct and outputs a -4V voltage, which is then transmitted to the input terminal of the subsequent negative voltage LDO.

[0050] Since the front-end positive voltage LDO is not powered on at this time, its output is GND or close to GND, which causes the INH pin of the subsequent negative voltage LDO to form a voltage divider between the ground terminal and its adjustment pin ADJ. Based on the conduction voltage of the reverse diode inside the subsequent negative voltage LDO, and according to the ratio of resistor R3 and resistor R4, the subsequent negative voltage LDO is further controlled to conduct, and the output voltage of the circuit system is -2.8V.

[0051] S3. During the auxiliary voltage power supply stage of the FPGA chip, an external power supply unit provides a +5V input voltage to the input terminal of the front-stage positive voltage LDO. At this time, the FPGA chip's I / O is in a floating state. Since the INH pin of the front-stage positive voltage LDO is floating, it is turned on by default, so the control function of the FPGA chip is temporarily disabled, causing the front-stage positive voltage LDO to conduct. According to the ratio of resistors R1 and R2, the front-stage positive voltage LDO outputs a +1.5V voltage to the ground terminal of the subsequent negative voltage LDO. This causes the INH pin of the subsequent negative voltage LDO to form a voltage divider between the ground terminal and its adjustment pin ADJ. Based on the conduction voltage of the reverse diode inside the subsequent negative voltage LDO, and according to the ratio of resistors R3 and R4, the subsequent negative voltage LDO is further controlled to conduct and output, resulting in an output voltage of -0.7V for the circuit system.

[0052] S4. During the FPGA chip loading process, the enable of the front-stage positive voltage LDO is turned off, so that the front-stage positive voltage LDO is in the off state. At this time, the output of the circuit system is -2.8V.

[0053] S5. After the FPGA chip is loaded, the logic control program is started, and a high level of +3.3V is supplied to the INH pin of the front-stage positive voltage LDO and the front-stage negative voltage LDO to turn off their outputs, so that the output of the circuit system is 0V.

[0054] S6. According to the power-on sequence of the modules to be powered on, the FPGA chip outputs an enable signal to the INH pins of the front-stage negative voltage LDO and the front-stage positive voltage LDO to control their enable. Based on the ratio of resistors R1 and R2, and resistors R3 and R4, the output terminal of the front-stage negative voltage LDO outputs a voltage of -2.2V and transmits it to the input terminal of the rear-stage negative voltage LDO. The output terminal of the front-stage positive voltage LDO outputs a voltage of +1.5V and transmits it to the ground terminal of the rear-stage negative voltage LDO. This causes the INH pin of the rear-stage negative voltage LDO to form a voltage divider between the ground terminal and its adjustment pin ADJ. Based on the voltage divider and the conduction voltage of the reverse diode inside the rear-stage negative voltage LDO, the rear-stage negative voltage LDO is further controlled to conduct and output, resulting in an output voltage of -0.7V for the circuit system.

[0055] Since the FPGA chip is positioned before the I / O, the I / O is essentially floating. Therefore, it is necessary to pay attention to the enabling status of the external power supply unit and each LDO chip, as detailed in Table 1:

[0056] Table 1

[0057]

[0058] Specifically: RSW1101 is used to power the front-end positive voltage (LW4913) and front-end negative voltage (LW7913); RSW1201 is powered on earliest and is used to start the core logic power supply in the FPGA chip to ensure that the FPGA chip can start loading configuration; RSS0508 is used to provide the FPGA chip with the appropriate IO level drive capability to ensure that the IO pins can obtain a stable voltage output at the moment of power-on.

[0059] The above are merely embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the technical solution of this utility model should be included within the protection scope of this utility model. Furthermore, it should be noted that the accompanying drawings are merely illustrative and are not drawn to scale, and should not be construed as limiting the actual scope of protection claimed by this utility model.

Claims

1. A negative voltage generation circuit based on multi-stage voltage regulator control, characterized in that, include: The three-stage LDO architecture consists of a pre-stage positive LDO, a pre-stage negative LDO, and a post-stage negative LDO. The input terminal of the three-stage LDO architecture is connected to an external power supply unit, and the enable input terminal is connected to an external control unit. The input terminal of the pre-stage positive voltage LDO is connected to the positive output terminal of the external power supply unit, its ground terminal is connected to the output terminal of the pre-stage negative voltage LDO, and its output terminal is connected to the ground terminal of the post-stage negative voltage LDO. This is used to step down the positive input voltage provided by the external power supply unit and output it to the post-stage negative voltage LDO. The input terminal of the pre-stage negative voltage LDO is connected to the negative output terminal of the external power supply unit, its ground terminal is grounded, and its output terminal is connected to the input terminal of the post-stage negative voltage LDO. It is used to boost the negative input voltage provided by the external power supply unit and output it to the post-stage negative voltage LDO. The ground terminal of the subsequent negative voltage LDO is grounded, and a resistor voltage divider network is connected between its output terminal and the ground terminal. The resistor voltage divider network is used to sample the output voltage and, together with the adjustment pin ADJ of the subsequent negative voltage LDO, realizes the precise setting of the output voltage of the circuit system. The output terminal is used to output the generated set negative voltage, and the set negative voltage range is -0.5V to -1V. The enable signal output pin (IO pin) of the external control unit is connected to the INH pins of the preceding positive voltage LDO and the preceding negative voltage LDO. The INH pin of the preceding negative voltage LDO is connected to an external pull-down resistor. The INH pin of the following negative voltage LDO is connected to its high-level output and ground. This is used to manage the power-on sequence of each LDO in the three-stage LDO architecture, ensuring that the potential rises gradually from a low potential.

2. The negative voltage generation circuit based on multi-stage voltage regulator control according to claim 1, characterized in that: The resistor voltage divider network includes resistors R1, R2, and R3; One end of resistor R1 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is connected to one end of resistor R2 and connected to the adjustment pin ADJ. The other end of resistor R2 is grounded. One end of resistor R3 is connected to the output terminal of the subsequent negative voltage LDO, and the other end is grounded.

3. The negative voltage generation circuit based on multi-stage voltage regulator control according to claim 2, characterized in that: The pre-stage positive voltage LDO steps down the positive input voltage to output a reference voltage V. out1 The calculation formula is: Where: R1 and R2 are the resistance values ​​of resistors R1 and R2, respectively; 1.227 is the voltage value of the adjustment pin ADJ; The ratio between resistors R1 and R2 is set by adjusting the value of resistor R2, so that the reference voltage V... out1 It conforms to its preset value; the reference voltage V out1 On the one hand, it serves as the positive reference ground for the subsequent negative pressure LDO, and on the other hand, it serves as the reference potential platform for the enable signal sent by the subsequent external control unit; The preceding negative voltage LDO uses the boosted negative input voltage as the input voltage of the following negative voltage LDO, and also provides the initial negative voltage condition for the following negative voltage LDO during the initial power-on phase of the circuit system.

4. The negative voltage generation circuit based on multi-stage voltage regulator control according to claim 3, characterized in that: The output voltage V of the subsequent negative voltage LDO out2 The calculation formula is: Where: GND is the ground voltage of the subsequent negative voltage LDO; R3 is the resistance of resistor R3; R4 = R1 / R2; 1.227 is the voltage value of the adjustment pin ADJ; The ratio of resistors R3 and R4 is set by adjusting the values ​​of resistors R2 and R3, so that the output voltage value V is... out2 It conforms to its preset output value.

5. The negative voltage generation circuit based on multi-stage voltage regulator control according to claim 4, characterized in that: The resistor R1 is a 1kΩ resistor, used to provide a minimum load current of 1mA under no-load conditions, in order to avoid output instability of the three-stage LDO architecture.

6. The negative voltage generation circuit based on multi-stage voltage regulator control according to claim 1, characterized in that: When the ground terminal of the subsequent negative voltage is grounded, the voltage value output by the adjustment pin ADJ is always -1.227V.

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