Start-up circuit and bandgap device

Abstract

This disclosure relates to startup circuits and bandgap devices. A startup circuit is provided for a bandgap circuit providing a reference voltage, the current mirror of which includes a first MOS transistor. The startup circuit includes: a second transistor and a third transistor in a current mirror configuration, their control terminals coupled via a first resistor; and a fourth MOS transistor located between a terminal for applying a supply voltage and the control terminal of the second transistor, the fourth MOS transistor being in a current mirror configuration relative to the first MOS transistor.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. FR2408815, filed on August 9, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to the start-up circuit of a bandgap reference voltage circuit, a bandgap device, and an associated method of operation. Background Technology

[0004] Many known electronic devices include a bandgap circuit for generating a reference voltage that is generally independent of temperature.

[0005] These devices require a startup circuit to enable them to operate at a preferred operating point.

[0006] The current startup circuit has significant drawbacks.

[0007] The startup circuit of the bandgap circuit that generates the reference voltage needs to be improved. Utility Model Content

[0008] One embodiment overcomes some or all of the disadvantages of known startup circuits.

[0009] One embodiment provides a startup circuit for a bandgap circuit for generating a reference voltage, the bandgap circuit having a current mirror including a first MOS transistor, the startup circuit including: a second transistor and a third transistor in a current mirror configuration, the control terminals of which are coupled through a first resistor; and a fourth MOS transistor located between a terminal for applying a supply voltage and the control terminal of the second transistor, the fourth MOS transistor being current mirrored relative to the first MOS transistor.

[0010] The fourth transistor can be directly connected to the control terminal of the second transistor.

[0011] One embodiment provides a method for activating a bandgap circuit for generating a reference voltage, the bandgap circuit having a current mirror including a first MOS transistor, the method comprising: disconnecting the activation circuit from the generation circuit by turning on a fourth transistor, the activation circuit having: a second transistor and a third transistor in a current mirror configuration, the control terminals of which are coupled through a first resistor; and a fourth MOS transistor located between a terminal for applying a supply voltage and the control terminal of the second transistor, the fourth MOS transistor being current mirrored relative to the first MOS transistor.

[0012] In one embodiment, the current source couples a terminal for applying the supply voltage to a control terminal of a third transistor, and a terminal for applying the supply voltage to a conduction node of a second transistor.

[0013] In one embodiment, the second transistor couples the control terminal of the third transistor to ground via a second resistor.

[0014] In one embodiment, the size of the third transistor is at least N times larger than the size of the second transistor, where N ranges from 2 to 10 (inclusive).

[0015] In one embodiment, the second and third transistors are NMOS type, while the fourth transistor is PMOS type.

[0016] In one embodiment, the second and third transistors are bipolar type, while the fourth transistor is PMOS type.

[0017] One embodiment provides a bandgap device for generating a reference voltage, including the aforementioned startup circuit and a bandgap circuit for generating the reference voltage, the bandgap circuit including: a first branch having a first transistor connected in series with a fifth bipolar transistor; and a third resistor coupled to ground and connected in series with a fourth resistor coupled to the emitter of the fifth transistor; a second resistor configured to receive a voltage proportional to absolute temperature across its terminals, and a third resistor configured to receive a voltage complementary to absolute temperature across its terminals.

[0018] In one embodiment, the control terminal of the fourth MOS transistor is coupled to the control terminal of the first transistor; and the third transistor couples the midpoint between the first transistor and the fifth transistor to the midpoint between the third transistor and the fourth resistor in the generation circuit.

[0019] In one embodiment, the generating circuit includes a second branch having a sixth transistor connected in series with a seventh bipolar transistor, the control terminals of the fifth and seventh transistors being coupled to a first node, and the control terminals of the first, fourth, and sixth transistors being coupled to each other.

[0020] In one embodiment, the midpoint of the sixth and seventh transistors is coupled to the control terminals of the first, fourth, and sixth transistors.

[0021] In one embodiment, the generation circuit includes a third branch having: an eighth transistor that couples a terminal for applying a supply voltage to an output node of the generation circuit, and a control terminal of the eighth transistor that is coupled to the midpoint between a first transistor and a fifth transistor; a fifth resistor that couples the first node to ground; and a sixth transistor that couples the output node to the first node.

[0022] In one embodiment, a capacitor couples the midpoint between the first and fifth transistors to the output node.

[0023] In one embodiment, the first, sixth, and eighth transistors are PMOS type.

[0024] In one embodiment, the second resistor has a value equal to the value of the third resistor multiplied by N.

[0025] In one embodiment, the size of the fifth transistor is at least M times the size of the seventh transistor, where M ranges from 2 to 10 (inclusive).

[0026] One embodiment provides a method of using the above-described apparatus, comprising activating a generation circuit using a startup circuit and then deactivating the startup circuit.

[0027] In one aspect, a startup circuit is provided for a bandgap circuit that provides a reference voltage, the bandgap circuit including a current mirror having a first transistor, the startup circuit including: a second transistor and a third transistor in a current mirror configuration, control terminals of the second transistor and the third transistor being coupled through a first resistor; and a fourth transistor coupled between a terminal for applying a supply voltage and the control terminal of the second transistor, the fourth transistor being in a current mirror configuration with the first transistor.

[0028] In some embodiments, the startup circuit further includes a current source that couples a terminal for applying a supply voltage to a control terminal of a third transistor, and a terminal for applying a supply voltage to a conduction terminal of a second transistor.

[0029] In some embodiments, the startup circuit further includes a second resistor, wherein the second transistor couples the control terminal of the third transistor to ground via the second resistor.

[0030] In some embodiments, the size of the third transistor is at least N times larger than the size of the second transistor, where N ranges from 2 to 10, including the terminal value. In some embodiments, the second and third transistors are NMOS transistors, while the fourth transistor is a PMOS transistor. In some embodiments, the second and third transistors are bipolar transistors, while the fourth transistor is a PMOS transistor.

[0031] In some embodiments, the fourth transistor is directly connected to the control terminal of the second transistor.

[0032] In another aspect, a bandgap device for providing a reference voltage is provided, comprising: a startup circuit according to the embodiments described herein; and a bandgap circuit for providing the reference voltage, the bandgap circuit including a first branch having a first transistor connected in series with a fifth transistor, wherein the fifth transistor is a bipolar transistor.

[0033] In some embodiments, the bandgap circuit further includes: a third resistor coupled to ground, the third resistor being connected in series with a fourth resistor coupled to the emitter of a fifth transistor; wherein the fourth resistor is configured to receive a voltage across its terminals proportional to absolute temperature, and the third resistor is configured to receive a voltage across its terminals complementary to absolute temperature.

[0034] In some embodiments, the fourth transistor has a control terminal coupled to the control terminal of the first transistor; and the third transistor couples the midpoint between the first transistor and the fifth transistor to the midpoint between the third resistor and the fourth resistor.

[0035] In some embodiments, the bandgap circuit further includes a second branch having a sixth transistor connected in series with the seventh transistor, wherein the seventh transistor is a bipolar transistor, the control terminals of the fifth and seventh transistors are both coupled to the first node, and the control terminals of the first, fourth, and sixth transistors are coupled to each other.

[0036] In some embodiments, the midpoint of the sixth and seventh transistors is coupled to the control terminals of the first, fourth, and sixth transistors.

[0037] In some embodiments, the bandgap circuit further includes a third branch having: an eighth transistor that couples a terminal for applying a supply voltage to an output node of the bandgap circuit, and a control terminal of the eighth transistor that is coupled to the midpoint between the first and fifth transistors; a fifth resistor that couples the first node to ground; and a ninth transistor that couples the output node to the first node.

[0038] In some embodiments, a capacitor couples the midpoint of the first and fifth transistors to the output node. In some embodiments, the first, sixth, and eighth transistors are PMOS transistors. In some embodiments, the size of the fifth transistor is at least M times larger than the size of the seventh transistor, where M ranges from 2 to 10, including the terminal value.

[0039] On the other hand, a bandgap device for providing a reference voltage is provided, comprising:

[0040] According to the startup circuit, which further includes a second resistor and a second transistor coupling the control terminal of the third transistor to ground via the second resistor; and a bandgap circuit for providing a reference voltage, the bandgap circuit including: a first branch having the first transistor connected in series with a fifth transistor, wherein the fifth transistor is a bipolar transistor.

[0041] In some embodiments, the bandgap circuit includes: a third resistor coupled to ground, connected in series with a fourth resistor coupled to the emitter of a fifth transistor, the fourth resistor being configured to receive a voltage across its terminals proportional to absolute temperature, and the third resistor being configured to receive a voltage across its terminals complementary to absolute temperature; wherein a second resistor has a value equal to the value of the third resistor multiplied by a value of N, where N ranges from 2 to 10, including the terminal value.

[0042] In some embodiments, the bandgap circuit includes: a third resistor coupled to ground, connected in series with a fourth resistor coupled to the emitter of a fifth transistor, the third resistor being configured to receive a voltage across its terminals proportional to absolute temperature, and the fourth resistor being configured to receive a voltage across its terminals complementary to absolute temperature; wherein a second resistor has a value equal to the value of the third resistor multiplied by a value of N, where N ranges from 2 to 10, including the terminal value. Attached Figure Description

[0043] The foregoing features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings, which are given in an illustrative rather than restrictive manner in the following description of specific embodiments, in which:

[0044] Figure 1 The diagram illustrates a bandgap device used to generate a reference voltage.

[0045] Figure 2 The illustration shows the source Figure 1 One module of the device shown;

[0046] Figure 3 The illustration shows the source Figure 1 A module of the device shown; and

[0047] Figure 4 The illustration shows the source Figure 1 A module of the device shown. Detailed Implementation

[0048] In the various figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may have identical structure, dimensions, and material properties.

[0049] For clarity, only detailed illustrations and descriptions are provided for operations and elements useful for understanding the embodiments described herein.

[0050] Unless otherwise indicated, when two elements are said to be connected together, it means a direct connection without any intermediate elements other than the conductor, while when two elements are said to be coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0051] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as the terms "above", "below", "higher", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), the orientation shown in the figure is considered.

[0052] Unless otherwise specified, the expressions “approximately,” “about,” “substantially,” and “around” indicate within 10% or 10°, and preferably within 5% or 5°.

[0053] Figure 1 The diagram illustrates a bandgap device 100 used to generate a reference voltage.

[0054] The device 100 includes a startup circuit 120 connected to a bandgap circuit 110 for generating a reference voltage.

[0055] In the example shown, the startup circuit 120 is coupled (preferably connected) to the terminal Vcc for applying voltage and coupled to ground.

[0056] In the example shown, the bandgap circuit 110 includes a first branch 102 having a transistor MP2 connected in series with a bipolar transistor Q1 (e.g., NPN type). Transistor MP2 couples a terminal for applying the supply voltage Vcc to the collector of transistor Q1. The first branch 102 also includes a resistor R2 that couples ground to node NT. Resistor R2 is connected in series with resistor R1, which couples node NT to the emitter of transistor Q1. In one example, resistor R1 is between 1 kOhm and 10 kOhm (e.g., 3 kOhm), while resistor R2 is between 1 kOhm and 20 kOhm.

[0057] In the example shown, the bandgap circuit 110 includes a second branch 103 having a transistor MP3 (e.g., a PMOS) connected in series with bipolar transistor Q2. The control terminals of transistors Q1 and Q2 are coupled (preferably connected) together and coupled to node N3. The emitter of transistor Q2 is coupled (preferably connected) to node NT. The control terminals of transistors MP2 and MP3 are coupled (preferably connected) together and coupled to node N4. In one example, node N4 is also coupled (preferably connected) to the midpoint between transistors MP3 and Q2.

[0058] Therefore, transistors MP2 and MP3 are current mirrors.

[0059] In one example, the size of transistor Q1 is at least M times larger than the size of transistor Q2, where M ranges from 2 to 10 (inclusive). In this paper, the size of a bipolar transistor is, for example, the surface area of ​​its base. A transistor with a size M times larger can be realized by connecting M transistors in parallel.

[0060] In the example shown, the bandgap circuit 110 also includes a third branch 104. The third branch 104 includes a transistor MP4 that couples a terminal for applying the supply voltage Vcc to the output node NOUT of the bandgap circuit 110. The control terminal of transistor MP4 is coupled to the midpoint N2 of transistors MP2 and Q1. The third branch 104 also includes a resistor R4 coupling node N3 to ground, and a resistor R3 coupling the output node NOUT to node N3.

[0061] In one example, capacitor Cc couples the midpoint N2 of transistors MP2 and Q1 to the output node NOUT. This capacitor is configured as a stable loop.

[0062] In the illustrated example, the bandgap circuit 110 may also optionally include a transistor MP5, whose control terminal is coupled (preferably connected) to the control terminals of transistors MP2 and MP3 to form a current mirror. Transistor MP5 couples a terminal for applying the supply voltage Vcc to node N5, where the output current of device 100 can be measured.

[0063] exist Figure 1 In the diagram, transistors MP2, MP3, MP4, and MP5 are of the PMOS type.

[0064] By appropriately selecting the ratio of resistors R2 to R1, resistor R2 can be configured to receive a voltage Vptat across its terminals that is proportional to the absolute temperature, while resistor R1 is further configured to receive a voltage Vctat across its terminals that is complementary to the absolute temperature. For this first approximation, this results in a temperature-independent voltage at node N3 that approximates the value of the silicon bandgap (i.e., 1.26V). Resistors R3 and R4 then act as a voltage divider bridge to obtain a reference voltage at the output node NOUT.

[0065] The bandgap circuit 110 includes two stable operating points. One of these operating points results in zero current at the output node NOUT. The startup circuit 120 allows this operating point to be bypassed by temporarily grounding the control terminal of transistor MP4, enabling the bandgap circuit 110 to operate at its rated current.

[0066] Figure 2 The diagram shows... Figure 1 A module of the device shown. In particular, Figure 2 An example of the startup circuit 220 is illustrated.

[0067] The startup circuit 220 shown includes a current source 222 that couples a terminal for applying the supply voltage Vcc to node N20. A transistor MN1 (e.g., an NMOS type) couples node N20 to ground.

[0068] The startup circuit 220 also includes a transistor MP21 (e.g., PMOS type) that couples the terminal to which the supply voltage Vcc is applied to node N21. The control terminal of transistor MP21 is coupled (preferably connected) to the control terminal of transistor MP2 in the bandgap circuit 110 to form a current mirror.

[0069] The startup circuit 220 also includes a transistor MN2 (e.g., an NMOS type) that couples node N21 to ground. The control terminals of transistors MN2 and MN1 are coupled to each other (preferably connected) and coupled to node N20.

[0070] Another transistor MPST (e.g., PMOS type) couples node N2 of bandgap circuit 110 to ground. The control terminal of transistor MPST is coupled (preferably connected) to node N21.

[0071] To start up, transistor MN1 is turned off (i.e., not conducting). The gate-source voltage of transistor MN2 is set by the current I0 flowing from current source 222 through transistor MN1. Then, node N21 is grounded. The drain-source voltage of transistor MPST drops by a few mV and node N2 is grounded. Therefore, the gate-source voltage of transistor MP4 increases significantly, thereby reducing its drain-source resistance. As a result, a large current flows through resistors R3 and R4, which in turn increases the voltage at node N3. Since the voltage at node N3 has increased, current can flow through transistors Q1 and Q2, thereby reducing the voltage at node N4. Bandgap circuit 110 is thus started up. Transistor MP21 replicates the current flowing through transistors Q1 and Q2, which is greater than the current flowing through transistor MN2. Node N21 has a voltage increased to Vcc, thereby turning off transistor MPST. This has the effect of turning off startup circuit 220.

[0072] Although Figure 2 The example shown enables the bandgap circuit 110 to be started, but during startup, before the voltage stabilizes, this results in a large current peak (e.g., more than ten times the rated current) and a high transition voltage at nodes N5 and NOUT.

[0073] In addition, oscillations may occur during startup.

[0074] Figure 3 The diagram shows... Figure 1 A module of the device shown. In particular, Figure 3 An example of the startup circuit 320 is illustrated.

[0075] The illustrated startup circuit 320 includes a current source 322 that couples a terminal for applying voltage Vcc to node N30. A transistor QB1 (e.g., bipolar NPN or NMOS type) couples node N30 to ground. Node N30 is coupled (preferably connected) to the control terminal of transistor QB1.

[0076] The startup circuit 320 also includes a transistor QB2 (e.g., a bipolar NPN or NMOS type) that couples node N2 to node NT of the bandgap circuit 110. The control terminals of transistors QB1 and QB2 are coupled to each other (preferably connected) and coupled to node N30.

[0077] During startup, current is supplied by current source 322 to discharge capacitor Cc of bandgap circuit 110. Therefore, node N2 is connected to node NT (close to ground). The increased current flowing through resistors R1 and R2 causes a gradual decrease in the base-emitter voltage, resulting in a reduction in the startup current. When the generation circuit is started, the base-emitter voltage of transistor QB2 is low enough to turn off transistor QB2, and no current flows through it.

[0078] Compared to circuit 220, startup circuit 320 allows for limiting the current peak during startup.

[0079] However, the time required to establish a stable signal at the output node NOUT can reach 20μs, while stability is expected to be achieved in less than 5μs. In fact, when the voltage at node NT reaches tens of mV, transistor QB2 is clamped, thus limiting its ability to discharge to the gate of transistor MP4.

[0080] In order to overcome Figure 2 and Figure 3 The example startup circuit shown has disadvantages. An embodiment provides a startup circuit for generating a circuit whose current mirror includes a first MOS transistor. The startup circuit includes: a second transistor and a third transistor in the current mirror, whose control terminals are coupled through a first resistor; and a fourth MOS transistor located between a terminal for applying a supply voltage and the control terminal of the second transistor, the fourth MOS transistor being in the current mirror relative to the first MOS transistor.

[0081] This allows for limiting current overload during startup, and also allows for limiting the time required to establish a stable signal at the output node NOUT to approximately 5 μs.

[0082] Figure 4 The diagram shows... Figure 1 A module of the device shown. In particular, Figure 4 An embodiment of the startup circuit 420 is illustrated.

[0083] The startup circuit 420 shown includes a current source 422 that couples a terminal for applying the supply voltage Vcc to node N1. In an example not shown, the current source is located outside the startup circuit. A transistor MNR (e.g., NPN bipolar or NMOS type) couples node N1 to ground.

[0084] In the example shown, the startup circuit includes a transistor MNP (e.g., NPN bipolar or NMOS type) that connects node N2 to node NT of bandgap circuit 110. A resistor ROFF couples (preferably connects) the control terminals of transistors MNR and MNP to each other. In one example, the resistor ROFF is between 100 kOhm and 900 kOhm. Node N1 is coupled (preferably connected) to the control terminal of transistor MNP.

[0085] In the example shown, the startup circuit 420 includes a transistor MP1 (e.g., PMOS type) that couples a terminal for applying voltage Vcc to the control terminal NB of transistor MNR. The control terminal of transistor MP1 is coupled (preferably connected) to node N4 of bandgap circuit 110, that is, coupled (preferably connected) to the control terminals of transistors MP2 and MP3, thereby forming a current mirror.

[0086] In an optional example, the size of transistor MNP is at least N times the size of transistor MNR, where N ranges from 2 to 10 (inclusive). In this document, the size of a MOS transistor is, for example, the surface area of ​​its gate or the ratio of its width to its length. For example, an N-fold increase in transistor size can be achieved by connecting N transistors in parallel. This allows for a reduction in the time required to stabilize the output voltage.

[0087] In an optional example, transistor MNR couples node N1 to ground via resistor RB. In one example, resistor RB has a value such that the voltage drop is the same as the voltage drop at node NT. In another example, resistor RB has a value equal to the value of resistor R2 multiplied by the value of N. This helps prevent the voltage between nodes N1 and NT from dropping too quickly during startup. Therefore, the current is Figure 3 The resistor RB is N times larger than the one shown in the example. This reduces the time required to stabilize the output voltage. In one example, the resistor RB is between 0 Ohm and 900 kOhm.

[0088] The operation of the startup circuit 420, for example, in a general sense, is related to... Figure 3 Similar to that shown, the difference is that, in order to disconnect the startup circuit, transistor MP1 replicates the current and injects it into resistor ROFF, thereby reducing the voltage present at the control terminal of transistor MNP by several hundred mV, for example, between 100mV and 1V, i.e., below its threshold, thus quickly turning off transistor MNP. Therefore, with Figure 2 and Figure 3 Compared to the example shown, this startup circuit disconnects faster and without overload.

[0089] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. In particular, Figure 4 The transistors MNR and MNP in the example shown can be bipolar transistors, such as NPN type. Those skilled in the art will also be able to invert the transistor type NMOS to PMOS, or NPN to PNP, and vice versa, by modifying the associated voltages and arranging the circuit according to their knowledge.

[0090] Finally, based on the functional descriptions provided above, the actual implementations of the embodiments and variations described herein are within the capabilities of those skilled in the art. In particular, those skilled in the art can use them with… Figure 1 The different bandgap circuits 110 described herein are used to implement the startup circuit 420. For example, the startup circuit can be a Brokaw-type circuit, as long as it contains a current mirror that can be replicated by transistor MP1, and the replicated current causes a voltage drop that quickly turns off transistor MNP to cause the startup circuit to disconnect.

Claims

1. A startup circuit for a bandgap circuit providing a reference voltage, characterized in that, The bandgap circuit includes a current mirror with a first transistor, and the startup circuit includes: The second and third transistors are configured as a current mirror, and their control terminals are coupled through a first resistor; and The fourth transistor is coupled between the terminal for applying the supply voltage and the control terminal of the second transistor, and the fourth transistor and the first transistor are in a current mirror configuration.

2. The startup circuit according to claim 1, characterized in that, It also includes a current source, which will: The terminal for applying the supply voltage is coupled to the control terminal of the third transistor, and The terminal used to apply the supply voltage is coupled to the conductive terminal of the second transistor.

3. The startup circuit according to claim 1, characterized in that, It also includes a second resistor, through which the control terminal of the third transistor is coupled to ground by the second transistor.

4. The starting circuit according to claim 1, characterized in that, The size of the third transistor is at least N times larger than the size of the second transistor, where N ranges from 2 to 10, including the terminal value.

5. The startup circuit according to claim 1, characterized in that, The second and third transistors are NMOS transistors, while the fourth transistor is a PMOS transistor.

6. The startup circuit according to claim 1, characterized in that, The second and third transistors are bipolar transistors, while the fourth transistor is a PMOS transistor.

7. The starting circuit according to claim 1, characterized in that, The fourth transistor is directly connected to the control terminal of the second transistor.

8. A bandgap device for providing a reference voltage, characterized in that, include: The startup circuit according to claim 1; as well as A bandgap circuit for providing a reference voltage, the bandgap circuit including a first branch having a first transistor connected in series with a fifth transistor, wherein the fifth transistor is a bipolar transistor.

9. The bandgap device according to claim 8, wherein the bandgap circuit further comprises: A third resistor coupled to ground, the third resistor being connected in series with a fourth resistor coupled to the emitter of the fifth transistor; The fourth resistor is configured to receive a voltage across its terminals that is proportional to the absolute temperature, and the third resistor is configured to receive a voltage across its terminals that is complementary to the absolute temperature.

10. The bandgap device according to claim 9, characterized in that, in: The fourth transistor has a control terminal coupled to the control terminal of the first transistor; as well as The third transistor couples the midpoint between the first and fifth transistors to the midpoint between the third and fourth resistors.

11. The bandgap device according to claim 9, characterized in that, The bandgap circuit also includes a second branch having a sixth transistor connected in series with the seventh transistor, wherein the seventh transistor is a bipolar transistor, the control terminals of the fifth and seventh transistors are coupled to the first node, and the control terminals of the first, fourth and sixth transistors are coupled to each other.

12. The bandgap device according to claim 11, characterized in that, The midpoint of the sixth and seventh transistors is coupled to the control terminals of the first, fourth, and sixth transistors.

13. The bandgap device according to claim 11, characterized in that, The bandgap circuit further includes a third branch, which has the following characteristics: The eighth transistor has a terminal for applying the supply voltage coupled to the output node of the bandgap circuit, and a control terminal for the eighth transistor coupled to the midpoint between the first and fifth transistors. A fifth resistor, which couples the first node to ground; as well as The ninth transistor couples the output node to the first node.

14. The bandgap device according to claim 13, characterized in that, The capacitor couples the midpoint between the first and fifth transistors to the output node.

15. The bandgap device according to claim 13, characterized in that, The first, sixth, and eighth transistors are PMOS transistors.

16. The bandgap device according to claim 11, characterized in that, The size of the fifth transistor is at least M times larger than the size of the seventh transistor, where M ranges from 2 to 10, including the terminal value.

17. A bandgap device for providing a reference voltage, characterized in that, include: The startup circuit according to claim 1, wherein the startup circuit further includes a second resistor, and the second transistor couples the control terminal of the third transistor to ground via the second resistor; as well as A bandgap circuit for providing a reference voltage, the bandgap circuit comprising: The first branch has the first transistor connected in series with the fifth transistor, wherein the fifth transistor is a bipolar transistor.

18. The bandgap device for providing a reference voltage according to claim 17, characterized in that, The bandgap circuit includes: a third resistor coupled to ground, connected in series with a fourth resistor coupled to the emitter of a fifth transistor, the fourth resistor being configured to receive a voltage across its terminals proportional to absolute temperature, and the third resistor being configured to receive a voltage across its terminals complementary to absolute temperature; wherein a second resistor has a value equal to the value of the third resistor multiplied by a value of N, where N ranges from 2 to 10, including the terminal value.

19. The bandgap device for providing a reference voltage according to claim 17, characterized in that, The bandgap circuit includes: a third resistor coupled to ground, connected in series with a fourth resistor coupled to the emitter of a fifth transistor, the third resistor being configured to receive a voltage across its terminals proportional to absolute temperature, and the fourth resistor being configured to receive a voltage across its terminals complementary to absolute temperature; wherein a second resistor has a value equal to the value of the third resistor multiplied by a value of N, where N ranges from 2 to 10, including the terminal value.

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