Voltage selection circuit

Abstract

This utility model relates to a voltage selection circuit, comprising: a control chip 1, a display interface 2, a first MOSFET PQ12B, a second MOSFET PQ12A, a third MOSFET PQ29, a fourth MOSFET PQ11, a first power supply P3V3, a second power supply P5V, and a third power supply DC_IN; the first MOSFET PQ12B, the second MOSFET PQ12A, the third MOSFET PQ29, and the fourth MOSFET PQ11 are all NMOS transistors; the gate of the first MOSFET PQ12B is connected to the control chip 1 to receive the control signal from the control chip 1, the source is grounded, and the drain is connected via... The first resistor PR206 is connected to the third power supply DC_IN, and one path is connected to the gate of the second MOSFET PQ12A and the gate of the third MOSFET PQ29; one path of the source of the third MOSFET PQ29 is grounded, and the other path is connected to the power supply pin of display interface 2, and the drain is connected to the first power supply P3V3; the source of the second MOSFET PQ12A is grounded, and one path of the drain is connected to the third power supply DC_IN via the second resistor PR204, and the other path is connected to the gate of the fourth MOSFET PQ11; one path of the source of the fourth MOSFET PQ11 is grounded, and the other path is connected to the power supply pin of display interface 2, and the drain is connected to the second power supply P5V.

Description

Technical Field

[0001] This utility model relates to the field of electronic computer technology, and in particular to a voltage selection circuit. Background Technology

[0002] In this era of diversified information technology, computer equipment is widely used in industrial control, enterprise office, user interaction, entertainment, and other applications. For different application areas or scenarios, users also have diverse needs regarding the display configuration of computer equipment.

[0003] LVDS (Low Voltage Differential Signaling) is a low-swing differential signaling technology that enables signals to be transmitted at speeds of hundreds of Mbps over differential PCB pairs or balanced cables. Its low voltage amplitude and low current drive output achieve low noise and low power consumption. LVDS screens are display devices based on low-voltage differential signaling technology, offering advantages such as low power consumption, interference resistance, high transmission efficiency, and stable transmission of high-definition image signals in complex environments. They are a mainstream display solution in industrial control, consumer electronics, and automotive displays.

[0004] Computer equipment may require different LVDS screens for different work scenarios because different LVDS screens have different power supply voltages. For example, the two most common LVDS screens supply 3.3V and 5V respectively. To quickly connect to these two types of LVDS screens, the computer equipment needs to be configured with separate power supplies providing 3.3V and 5V, and be able to easily switch between them. See also... Figure 1 The conventional approach in existing technology is to connect two power supplies to two pins (pin 1 and pin 3) of a three-pin connector 1', respectively. The third pin (pin 2) of the three-pin connector 1' is connected to the display interface 2'. By using a jumper cap to select whether to connect to pin 1 or pin 3, the display interface 2' can be connected to a power supply with a different voltage. However, the drawback of this approach is that every time a different LVDS screen is switched, the computer equipment needs to be disassembled and the jumper cap moved to the corresponding pin, which is inconvenient for use and maintenance. Furthermore, disassembling and reassembling the equipment also consumes time and labor costs. Summary of the Invention

[0005] Therefore, the purpose of this utility model is to provide a voltage selection circuit that can conveniently switch between different voltage power supplies.

[0006] To achieve the above objectives, this utility model provides a voltage selection circuit, comprising: a control chip, a display interface, a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a first power supply, a second power supply, and a third power supply; the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are all NMOS transistors; The gate of the first MOSFET is connected to the control chip to receive control signals from the control chip, its source is grounded, and its drain is connected to the third power supply via a first resistor and to the gates of the second and third MOSFETs. The source of the third MOSFET is grounded and connected to the power supply pin of the display interface, and its drain is connected to the first power supply. The source of the second MOSFET is grounded, and its drain is connected to the third power supply via a second resistor and to the gate of the fourth MOSFET. The source of the fourth MOSFET is grounded and connected to the power supply pin of the display interface, and its drain is connected to the second power supply.

[0007] The gate of the first MOS transistor is connected to the control chip via a third resistor and grounded via a fourth resistor; a first capacitor is connected between the gate and source of the first MOS transistor.

[0008] The third resistor has a resistance of 1 kΩ, the fourth resistor has a resistance of 100 kΩ, and the first capacitor has a capacitance of 0.1 μF.

[0009] The drain of the first MOSFET is connected to the third power supply via the first resistor, grounded via the fifth resistor, and connected to the gates of the second and third MOSFETs.

[0010] The first resistor has a resistance of 100 kΩ, and the fifth resistor has a resistance of 100 kΩ.

[0011] The source of the third MOS transistor is grounded via the second capacitor and connected to the power supply pin of the display interface via the other end; the source of the fourth MOS transistor is grounded via the third capacitor and connected to the power supply pin of the display interface via the other end.

[0012] The capacitance of both the second and third capacitors is 22μF.

[0013] The gate of the fourth MOS transistor is connected to the third power supply via the second resistor, grounded via the sixth resistor, connected to the drain of the second MOS transistor, and grounded via the fourth capacitor.

[0014] The second resistor has a resistance of 57.6 kΩ, the sixth resistor has a resistance of 100 kΩ, and the fourth capacitor has a capacitance of 0.1 μF.

[0015] The first and second MOSFETs are implemented using a dual MOSFET LBSS138DW1T1G; the third and fourth MOSFETs are both ZM200N02T; the control chip is an EC (Embedded Controller), and the EC is model IT5571E.

[0016] The voltage selection circuit is used to provide different voltages to different LVDS screens.

[0017] The third power supply is the motherboard power supply. The motherboard power supply is a 12V power supply, the first power supply is a 3.3V power supply, and the second power supply is a 5V power supply.

[0018] The source of the third MOS transistor is connected to the power supply pin of the display interface via the first diode; the source of the fourth MOS transistor is connected to the power supply pin of the display interface via the second diode.

[0019] Both the first diode and the second diode are of model LMBR140FT1G.

[0020] The beneficial effects of this utility model are as follows: The voltage selection circuit of this utility model controls the voltage selection through the control chip. Only the software needs to select the corresponding power supply voltage, and the control chip will send the corresponding control signal to connect the display interface to different power supplies. It is easy to operate and does not require disassembling the whole machine to select the jumper, saving time and labor costs. Attached Figure Description

[0021] The technical solution and other beneficial effects of this utility model will become apparent from the following detailed description of specific embodiments, in conjunction with the accompanying drawings.

[0022] Figure 1 A schematic diagram of the circuit principle for voltage selection using a three-pin connector in existing technology;

[0023] Figure 2 This is a circuit diagram of an embodiment of the voltage selection circuit of this utility model;

[0024] Figure 3 for Figure 2 A schematic diagram of the pin wiring for the display interface section of the voltage selection circuit;

[0025] Figure 4 for Figure 2 A schematic diagram of the pin wiring for the control chip section of the voltage selection circuit. Detailed Implementation

[0026] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.

[0027] See Figure 2-4 This utility model provides a voltage selection circuit, including: a control chip 1, a display interface 2, a first MOSFET PQ12B, a second MOSFET PQ12A, a third MOSFET PQ29, a fourth MOSFET PQ11, a first power supply P3V3, a second power supply P5V, and a third power supply DC_IN; the first MOSFET PQ12B, the second MOSFET PQ12A, the third MOSFET PQ29, and the fourth MOSFET PQ11 are all NMOS transistors; The gate (G) of the first MOSFET PQ12B is connected to pin 112 of the control chip 1 to receive the control signal LVDS_P5V from the control chip 1. Its source (S) is grounded, and its drain (D) is connected via a first resistor PR206 to the third power supply DC_IN, and another connection is made to the gate (G) of the second MOSFET PQ12A and the gate (pin 1 of the third MOSFET PQ29). The source (pin 2 of the third MOSFET PQ29) is grounded on one side and connected to the power supply pin of the display interface 2 on the other. The drain of the third MOSFET PQ29 (pin 3) is connected to the first power supply P3V3; the source (S) of the second MOSFET PQ12A is grounded, and its drain (D) is connected to the third power supply DC_IN via the second resistor PR204, and to the gate of the fourth MOSFET PQ11 (pin 1 of the fourth MOSFET PQ11). The source of the fourth MOSFET PQ11 (pin 2 of the fourth MOSFET PQ11) is grounded, connected to the power supply pin of the display interface 2, and its drain (pin 3 of the fourth MOSFET PQ11) is connected to the second power supply P5V.

[0028] When the control chip 1 outputs a high-level signal, the first MOSFET PQ12B is turned on, the drain of the first MOSFET PQ12B is at a low level, the second MOSFET PQ12A and the third MOSFET PQ29 are turned off, the first power supply P3V3 is not connected to the power supply pin of the display interface 2, the gate of the fourth MOSFET PQ11 is pulled up to the third power supply DC_IN, the fourth MOSFET PQ11 is turned on, and the second power supply P5V is connected to the power supply pin of the display interface 2 to supply power to the display interface 2. When the control chip 1 outputs a low-level signal, the first MOSFET PQ12B is turned off, the gates of the second MOSFET PQ12A and the third MOSFET PQ29 are pulled up to the third power supply DC_IN, and the second MOSFET PQ12A and the third MOSFET PQ29 are turned on. The first power supply P3V3 is connected to the power supply pin of the display interface 2 to supply power to the display interface 2. At this time, the gate of the fourth MOSFET PQ11 is pulled down to ground, the fourth MOSFET PQ11 is turned off, and the second power supply P5V is not connected to the power supply pin of the display interface 2.

[0029] Therefore, the voltage selection circuit of this utility model controls the voltage selection through the control chip. Only the software needs to select the corresponding power supply voltage, and the control chip will send the corresponding control signal to connect the display interface to different power supplies, so as to provide different power supply voltages for different screens. It is easy to operate, does not require disassembling the whole machine to select the jumper, and saves time and labor costs.

[0030] Preferably, the gate of the first MOS transistor PQ12B is connected to the control chip 1 via a third resistor PR209 and grounded via a fourth resistor PR210; a first capacitor PC229 is connected between the gate and source of the first MOS transistor PQ12B.

[0031] Specifically, Figure 2-4 In a preferred embodiment of the present invention shown, the resistance of the third resistor PR209 is 1 kΩ, the resistance of the fourth resistor PR210 is 100 kΩ, and the capacitance of the first capacitor PC229 is 0.1 μF.

[0032] Preferably, the drain of the first MOSFET PQ12B is connected to the third power supply DC_IN via the first resistor PR206, grounded via the fifth resistor PR208, and connected to the gate of the second MOSFET PQ12A and the gate of the third MOSFET PQ29.

[0033] Specifically, Figure 2-4 In a preferred embodiment of the present invention shown, the resistance of the first resistor PR206 is 100 kΩ, and the resistance of the fifth resistor PR208 is 100 kΩ.

[0034] Preferably, the source of the third MOSFET PQ29 is grounded via the second capacitor PC230 and connected to the power supply pin of the display interface 2; the source of the fourth MOSFET PQ11 is grounded via the third capacitor PC227 and connected to the power supply pin of the display interface 2.

[0035] Specifically, Figure 2-4In a preferred embodiment of the present invention shown, the capacitance of both the second capacitor PC230 and the third capacitor PC227 is 22μF.

[0036] Preferably, the gate of the fourth MOS transistor PQ11 is connected to the third power supply DC_IN through the second resistor PR204, grounded through the sixth resistor PR205, connected to the drain of the second MOS transistor PQ12A, and grounded through the fourth capacitor PC228.

[0037] Specifically, Figure 2-4 In a preferred embodiment of the present invention shown, the resistance of the second resistor PR204 is 57.6 kΩ, the resistance of the sixth resistor PR205 is 100 kΩ, and the capacitance of the fourth capacitor PC228 is 0.1 μF.

[0038] Preferably, the source of the third MOSFET PQ29 is connected to the power supply pin of the display interface 2 via the first diode D1; the source of the fourth MOSFET PQ11 is connected to the power supply pin of the display interface 2 via the second diode D2.

[0039] Preferably, Figure 2-4 In a preferred embodiment of the present invention shown, the first MOSFET PQ12B and the second MOSFET PQ12A are implemented using dual MOSFETs LBSS138DW1T1G; the third MOSFET PQ29 and the fourth MOSFET PQ11 are both ZM200N02T; the first diode D1 and the second diode D2 are both LMBR140FT1G; and the control chip 1 is an EC, with the EC model being IT5571E.

[0040] Specifically, Figure 2-4 In a preferred embodiment of the present invention shown, the voltage selection circuit is used to provide different voltages to different LVDS screens. The third power supply DC_IN is the motherboard power supply. The motherboard power supply is a 12V power supply, the first power supply P3V3 is a 3.3V power supply, and the second power supply P5V is a 5V power supply.

[0041] It is understood that the specific component models and values ​​in the circuit of this utility model can be selected according to the motherboard type of the specific applicable electronic device or smart device, and will not be elaborated here.

[0042] In summary, the voltage selection circuit of this utility model controls the voltage selection through a control chip. Only the software needs to select the corresponding power supply voltage, and the control chip will send the corresponding control signal to connect the display interface to different power supplies. It is easy to operate, does not require disassembling the whole machine to select the jumper, and saves time and labor costs.

[0043] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the appended claims of this utility model.

Claims

1. A voltage selection circuit, characterized by, include: The system includes a control chip (1), a display interface (2), a first MOSFET (PQ12B), a second MOSFET (PQ12A), a third MOSFET (PQ29), a fourth MOSFET (PQ11), a first power supply (P3V3), a second power supply (P5V), and a third power supply (DC_IN); the first MOSFET (PQ12B), the second MOSFET (PQ12A), the third MOSFET (PQ29), and the fourth MOSFET (PQ11) are all NMOS transistors. The gate of the first MOS transistor (PQ12B) is connected to the control chip (1) to receive the control signal from the control chip (1). Its source is grounded, and its drain is connected to the third power supply (DC_IN) via the first resistor (PR206) and to the gates of the second MOS transistor (PQ12A) and the third MOS transistor (PQ29). The source of the third MOS transistor (PQ29) is grounded and connected to the power supply pin of the display interface (2). Its drain is connected to the first power supply (P3V3). The source of the second MOS transistor (PQ12A) is grounded, and its drain is connected to the third power supply (DC_IN) via the second resistor (PR204) and to the gate of the fourth MOS transistor (PQ11). The source of the fourth MOS transistor (PQ11) is grounded and connected to the power supply pin of the display interface (2). Its drain is connected to the second power supply (P5V).

2. The voltage selection circuit of claim 1, wherein, The gate of the first MOS transistor (PQ12B) is connected to the control chip (1) through the third resistor (PR209) and grounded through the fourth resistor (PR210); a first capacitor (PC229) is connected between the gate and source of the first MOS transistor (PQ12B).

3. The voltage selection circuit of claim 2, wherein, The third resistor (PR209) has a resistance of 1 kΩ, the fourth resistor (PR210) has a resistance of 100 kΩ, and the first capacitor (PC229) has a capacitance of 0.1 μF.

4. The voltage selection circuit of claim 1, wherein, The drain of the first MOSFET (PQ12B) is connected to the third power supply (DC_IN) through the first resistor (PR206), grounded through the fifth resistor (PR208), and connected to the gate of the second MOSFET (PQ12A) and the gate of the third MOSFET (PQ29).

5. The voltage selection circuit as described in claim 4, characterized in that, The first resistor (PR206) has a resistance of 100 kΩ, and the fifth resistor (PR208) has a resistance of 100 kΩ.

6. The voltage selection circuit as described in claim 1, characterized in that, The source of the third MOS transistor (PQ29) is grounded through the second capacitor (PC230) and connected to the power supply pin of the display interface (2); the source of the fourth MOS transistor (PQ11) is grounded through the third capacitor (PC227) and connected to the power supply pin of the display interface (2).

7. The voltage selection circuit as described in claim 6, characterized in that, The capacitance of both the second capacitor (PC230) and the third capacitor (PC227) is 22μF.

8. The voltage selection circuit as described in claim 1, characterized in that, The gate of the fourth MOS transistor (PQ11) is connected to the third power supply (DC_IN) through the second resistor (PR204), grounded through the sixth resistor (PR205), connected to the drain of the second MOS transistor (PQ12A), and grounded through the fourth capacitor (PC228).

9. The voltage selection circuit as described in claim 8, characterized in that, The second resistor (PR204) has a resistance of 57.6 kΩ, the sixth resistor (PR205) has a resistance of 100 kΩ, and the fourth capacitor (PC228) has a capacitance of 0.1 μF.

10. The voltage selection circuit as described in claim 1, characterized in that, The first MOSFET (PQ12B) and the second MOSFET (PQ12A) are implemented using a dual MOSFET LBSS138DW1T1G; the third MOSFET (PQ29) and the fourth MOSFET (PQ11) are both ZM200N02T; the control chip (1) is an EC, and the EC is model IT5571E; the voltage selection circuit is used to provide different voltages to different LVDS screens.

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