A fuse trimming circuit

Abstract

The utility model discloses a fuse trimming circuit relates to electronic circuit technical field, aims at solving the problem of the area of switch tube being too big in fuse trimming circuit, including: fuse, one end of fuse is connected power supply, N type switch tube is realized through isolation type NMOS pipe, the drain of N type switch tube is connected the other end of fuse, buffer module, the output of buffer module is connected N type switch tube. A kind of fuse trimming circuit in the utility model can greatly reduce the width-length ratio of switch tube by using the parasitic NPN opening of isolation NMOS pipe to increase the current passing ability of switch tube, prevent chip area from being wasted, reduce the cost of product.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a fuse adjustment circuit. Background Technology

[0002] Fuse trimming circuits are widely used in various high-performance chips to reduce the adverse effects of process variations on the circuit, thereby improving product performance and yield. A typical fuse trimming circuit consists of a thin fuse made of polysilicon or metal, a switching transistor that controls the flow of a large current through the fuse and ensures that the fuse melts due to overcurrent at high temperatures, and other control circuitry. However, in existing technologies, the large current required for fuse melting necessitates a large aspect ratio for the switching transistor, resulting in a larger chip area and increased product cost.

[0003] For example, Chinese patent CN115857605A discloses a fuse trimming circuit, comprising: a fuse trimming control unit, an erroneous trimming protection unit, and a trimming position control unit. The fuse trimming control unit generates a first trimming enable signal during the trimming period and a first trimming disable signal during the non-trimming period based on a first fuse programming control signal. The trimming position control unit generates a second trimming enable signal during the trimming period and a second trimming disable signal during the non-trimming period based on a second fuse programming control signal, and is capable of trimming based on the first and second trimming enable signals during the trimming period. The erroneous trimming protection unit generates a data read disable signal during the trimming period and a data read enable signal during the non-trimming period based on the erroneous trimming control signal, wherein the data read enable signal is less than the first trimming enable signal. However, the fuse blowing in Chinese patent CN115857605A requires a large current, resulting in a large aspect ratio for the switching transistor, occupying a large chip area, and increasing cost. Utility Model Content

[0004] To address the issue of excessively large switching transistor area in fuse adjustment circuits, this invention proposes a fuse adjustment circuit that utilizes the parasitic NPN turn-on of an isolated NMOS transistor to increase the current-carrying capacity of the switching transistor. This significantly reduces the width-to-length ratio of the switching transistor, preventing wasted chip area and lowering product costs.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a fuse adjustment circuit, comprising: a fuse, one end of which is connected to a power supply; an N-type switch, implemented by an isolated NMOS transistor, the drain of which is connected to the other end of the fuse; and a buffer module, the output of which is connected to the N-type switch.

[0006] In this technical solution, the parasitic NPN transistor of the N-type switching transistor is used to increase the current carrying capacity of the switching transistor. While maintaining the current carrying capacity of the N-type switching transistor connected to the fuse, the area is reduced to 1 / 5 to 1 / 10 of the original area, thereby reducing the cost of the fuse adjustment circuit.

[0007] Preferably, the buffer module includes a first inverter and a second inverter connected to the first inverter, wherein the input terminal of the first inverter is the input terminal of the buffer module, and the output terminal of the second inverter is the output terminal of the buffer module.

[0008] Preferably, the source of the N-type switch is grounded, and the gate of the N-type switch receives the adjustment input signal. The adjustment input signal is connected to the body terminal of the N-type switch after passing through the first inverter and the second inverter in sequence.

[0009] Preferably, a parasitic NPN transistor is formed inside the N-type switch transistor. The body terminal of the N-type switch transistor corresponds to the base of the parasitic NPN transistor, the source terminal of the N-type switch transistor corresponds to the emitter of the parasitic NPN transistor, and the drain terminal of the N-type switch transistor corresponds to the collector of the parasitic NPN transistor. The base of the parasitic NPN transistor of the N-type switch transistor is connected to the output terminal of the second inverter. The parasitic NPN transistor is turned on when the N-type switch transistor is turned on, so as to increase the conductivity of the N-type switch transistor.

[0010] Preferably, the buffer module includes: a first inverter, whose input terminal receives a trimming input signal and whose output terminal is connected to the input terminal of a second inverter; and a second inverter, whose output terminal is connected to the body terminal of an N-type switching transistor.

[0011] Preferably, the buffer module includes a voltage follower, the input of which receives a trimming input signal, and the output is connected to the body of an N-type switching transistor.

[0012] Preferably, the second inverter is composed of a set of PMOS transistors and NMOS transistors, with the drains of the PMOS transistors and the drains of the NMOS transistors connected together, and the gates of the PMOS transistors and the gates of the NMOS transistors connected together.

[0013] Preferably, the conductive path of the N-type switch includes the channel conductive path of the intrinsic NMOS transistor and the common-emitter amplification conductive path of the parasitic NPN transistor.

[0014] Preferably, the current flowing through the N-type switch after the parasitic NPN transistor is turned on is 5 to 10 times the current flowing through the N-type switch when the parasitic NPN transistor is not turned on.

[0015] Preferably, the width-to-length ratio of the PMOS and NMOS transistors in the second inverter is adjusted according to the electrical parameters of the parasitic NPN transistor of the N-type switch to ensure that the parasitic NPN transistor operates within a reasonable amplification range.

[0016] The beneficial effects of this utility model are: it reduces the chip area to 1 / 5 to 1 / 10 of the original area, thereby reducing the cost of the fuse adjustment circuit. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an existing fuse adjustment circuit.

[0018] Figure 2 This is a circuit diagram of a fuse adjustment circuit according to Embodiment 1 of this utility model.

[0019] Figure 3a This is a schematic diagram of the structure of an isolated NMOS transistor in a fuse adjustment circuit according to this utility model.

[0020] Figure 3b This is a schematic diagram of the structure of an isolated NMOS transistor in a fuse adjustment circuit according to this utility model.

[0021] Figure 4 This is a circuit diagram of a fuse adjustment circuit according to Embodiment 3 of this utility model.

[0022] Reference numerals in the attached diagram: 1: N-type switch; 1-1: Isolation deep N-well; 1-2: Isolation SiO2; 2: Fuse; 3: Buffer module; 3-1: First inverter; 3-2: Second inverter; 4: Adjustment input signal. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only one preferred embodiment of this utility model and are only used to explain this utility model. They do not limit the scope of protection of this utility model. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0024] Existing fuse adjustment circuits generally include: a thin fuse made of polysilicon or metal, a switching transistor that controls the flow of a large current through the fuse and ensures that the fuse melts due to overcurrent caused by high temperature, and other control circuits.

[0025] When a fuse is not blown, it is usually connected in parallel with components such as resistors or capacitors. Because the fuse's resistance is relatively small, it can short-circuit these components, preventing them from functioning properly. After the fuse blows, its resistance increases rapidly, approaching an open circuit, and the components connected in parallel with it can then operate normally in the circuit. Alternatively, when the fuse is not blown, a node in the circuit receives a logic level through the fuse and some other circuitry. After the fuse blows, it disconnects from this logic level, causing the logic level at that node to reverse after the fuse blows.

[0026] like Figure 1 As shown, the existing mainstream fuse tuning circuit consists of a fuse and a switching transistor.

[0027] One end of the fuse is connected to a power supply potential, which can provide a large current to blow the fuse. The other end is connected to ground through a switching transistor. After the adjustment signal is input, the switching transistor turns on, and a large current flows through the fuse. After a period of time, the fuse blows due to overcurrent caused by high temperature.

[0028] Because fuses require a large current to blow—for example, the thin polysilicon fuses commonly used in integrated circuits typically require 10mA-50mA of current to melt after a certain period—the switching transistors need to have the ability to conduct large currents, i.e., a large aspect ratio, thus occupying a large chip area. After the fuse blows, the switching transistor becomes ineffective, no longer needing to carry current, yet still occupying a large chip area. Therefore, large switching transistors significantly waste chip area and increase product costs.

[0029] Example 1 This embodiment provides a fuse adjustment circuit, such as Figure 2 As shown, it includes an N-type switch 1, a fuse 2, and a buffer module 3, which can significantly reduce the chip area and lower manufacturing costs.

[0030] In this embodiment, the fuse is made of fine wires made of polycrystalline silicon or metal, with one end connected to the power supply and the other end connected to the drain of the N-type switching transistor.

[0031] When the fuse is not blown, the resistance is small and can be regarded as a short circuit; after the fuse blows, the resistance approaches infinity, realizing the switching of circuit state.

[0032] It should be noted that the N-type switch used in this embodiment is an isolated NMOS transistor, which has an N-type isolation well between its base (B) and P-Sub terminals, resulting in parasitic structures, such as... Figure 3a As shown.

[0033] In this embodiment, the N-type switch can be manufactured using a deep N-well isolation process. In some other embodiments, the N-type switch can also be manufactured using an SOI process, such as... Figure 3b As shown.

[0034] By using an isolated NMOS transistor, the body potential can be avoided from being clamped, ensuring that the base of the parasitic NPN transistor can be independently controlled, thus enabling the parasitic NPN transistor to conduct normally.

[0035] The drain of the N-type switch is connected to the other end of the fuse, the source is grounded, the gate receives the adjustment input signal, and the body is connected to the output of the buffer module.

[0036] The N-type switching transistor has a parasitic NPN transistor. The body terminal of the isolated NMOS transistor corresponds to the base of the parasitic NPN transistor, the source terminal of the isolated NMOS transistor corresponds to the emitter terminal of the parasitic NPN transistor, and the drain terminal of the isolated NMOS transistor corresponds to the collector terminal of the parasitic NPN transistor, forming a common-emitter structure.

[0037] The buffer module can be implemented by an even number of inverters. In this embodiment, the buffer module is implemented by two inverters, specifically including two stages of inverters, namely the first inverter 3-1 and the second inverter 3-2.

[0038] The input terminal of the first inverter receives the adjustment input signal, and the output terminal is connected to the input terminal of the second inverter.

[0039] The input terminal of the second inverter is connected to the output terminal of the first inverter, and the output terminal is connected to the body terminal of the N-type switching transistor.

[0040] The second inverter consists of a set of PMOS and NMOS transistors. The source of the PMOS transistor is connected to the power supply, and the gates of the PMOS and NMOS transistors are connected together. The drain of the PMOS transistor is connected to the drain of the NMOS transistor and serves as the output terminal. The gates of both transistors receive the output signal of the first inverter.

[0041] The adjustment input signal passes through the first inverter and then through the second inverter to the body terminal of the switching transistor.

[0042] The body terminal of the N-type switching transistor serves as the base of the parasitic NPN transistor. When the voltage at the B terminal exceeds the turn-on voltage of the parasitic NPN transistor, the parasitic NPN transistor turns on, forming a common-emitter amplification conduction path from the drain to the source.

[0043] In this embodiment, the turn-on voltage of the parasitic NPN transistor is generally 0.7-0.8V, and the base voltage should be greater than the turn-on voltage, which can be 1V-3V.

[0044] In some other implementations, the second inverter may also employ the same structure as the first inverter.

[0045] like Figure 2 As shown in Figure -3, to clearly illustrate the working principle, the internal structure of the second inverter is drawn, and the N-type switch is shown with its B terminal (body terminal) and the parasitic NPN transistor formed by its D and S terminals. Connecting the B terminal to the output of the second inverter is equivalent to connecting the base of the parasitic NPN transistor to the output of the second inverter.

[0046] In this embodiment, unlike conventional switching transistors where the base (B) and source (S) terminals are connected together, the base (B) terminal is connected to a specific potential. After adjusting the input signal buffer module, appropriate voltage and current are generated to ensure that the base (B) terminal remains at the specific voltage.

[0047] When the input adjustment signal is low, the N-type switch is turned off, the B-terminal potential is grounded through the NMOS transistor, and no current flows through the fuse.

[0048] Specifically, when the adjustment input signal is low, the first inverter outputs a high level, the second inverter outputs a low level, the body terminal ground potential of the N-type switch is pulled down to a low level by the second inverter, the gate of the N-type switch is at a low level, so the N-type switch is cut off, there is no conductive channel between the drain and the source, no current flows through the fuse, and the circuit is in its initial state.

[0049] When the input adjustment signal goes high, the N-type switch turns on, and current begins to flow through the fuse. Simultaneously, this high-level signal passes through two inverters and reaches terminal B, raising the voltage at terminal B. When the voltage exceeds the turn-on voltage of the parasitic NPN transistor (typically 0.7-0.8V), the NPN transistor will also turn on, allowing a larger current to flow through the fuse.

[0050] At this point, the N-type switch's conductive path changes from one to two: the intrinsic NMOS channel conductive path plus the parasitic NPN common-emitter amplification conductive path. In typical CMOS processes, the conductivity of this parasitic NPN is approximately 5-10 times that of an NMOS transistor of the same area. Therefore, the current flowing through the N-type switch is approximately 5-10 times that of an N-type switch of the same size in the on-state. Achieving the same conductivity while occupying only 1 / 5 to 1 / 10 of the original switch area significantly saves space in the fuse adjustment circuit and reduces costs.

[0051] Specifically, when the adjustment signal goes high, the circuit's workflow can be divided into the following four steps.

[0052] The first step is to initially turn on the isolated NMOS transistor.

[0053] When the adjustment input signal is high, the gate voltage of the N-type switch increases. After exceeding the threshold voltage, the intrinsic channel of the N-type switch is turned on, forming the first conductive path, namely drain D → channel → source S, and current begins to flow through the fuse.

[0054] The second step is to adjust the voltage at the driver end of the buffer module.

[0055] A high-level signal is inverted to a low level by the first inverter and then input to the second inverter. The PMOS transistor of the second inverter is turned on and the NMOS transistor is turned off, and the output voltage rises to close to the power supply voltage.

[0056] The third step is to activate the parasitic NPN tube.

[0057] When the voltage at terminal B exceeds the turn-on voltage of the parasitic NPN transistor, the base-emitter junction of the parasitic NPN transistor becomes forward biased, and the NPN transistor conducts, forming a second conductive path: drain (D, collector of the parasitic NPN transistor) → base → emitter (source (S)). At this point, the conductivity of the N-type switch is contributed by both the intrinsic channel and the parasitic NPN transistor, resulting in a significant increase in total current, reaching 5-10 times the current flowing through a similarly sized NMOS transistor in the on-state.

[0058] The fourth step is to blow the fuse.

[0059] The increased current flows through the fuse, causing it to melt due to overcurrent caused by high temperature. After melting, the fuse resistance approaches infinity, and the circuit state switches, such as when parallel components are connected or the node level flips.

[0060] In this embodiment, the width-to-length ratio of the PMOS and NMOS transistors in the second inverter is adjusted according to the electrical parameters of the parasitic NPN transistor, such as the current amplification factor β, base resistance, and turn-on voltage.

[0061] For example, increasing the width-to-length ratio of the PMOS transistor can improve the rise speed of the base voltage, ensuring that the parasitic NPN transistor quickly enters the amplification region; at the same time, it can prevent the NMOS transistor from being too strong, which would cause the base voltage to be too low and thus fail to activate the NPN transistor.

[0062] The fuse adjustment circuit of this embodiment can improve current capability and optimize area. Through the common-emitter amplification effect of the parasitic NPN transistor, the width-to-length ratio of the N-type switch can be reduced to 1 / 5-1 / 10 of the traditional solution under the same current requirement, which significantly reduces the chip area and reduces manufacturing cost.

[0063] The fuse adjustment circuit of this embodiment is designed based on conventional CMOS, SOI, BCD and other processes. It only requires adjusting the parameters of the buffer module and using isolated NMOS transistors. No additional process steps are required, and it is easy to integrate.

[0064] In a fuse adjustment circuit of this embodiment, the parasitic NPN transistor and the intrinsic NMOS transistor work together to ensure stable current during fuse blowing, reduce the problem of blowing failure due to insufficient current, and achieve high reliability.

[0065] Through the above embodiments, the present invention achieves the improvement of the switching transistor current capability by using parasitic devices without adding complex circuits, effectively solving the problem of excessively large switching transistor area in traditional fuse adjustment circuits.

[0066] Example 2 This embodiment provides a fuse adjustment circuit, which is used in a motor drive chip to precisely control the speed and direction of the motor. It mainly consists of a fuse array, a control logic unit, a buffer module, an N-type switch array, and a digital-to-analog converter (DAC).

[0067] The fuse array consists of multiple fuses, one end of which is connected to the power supply. The melting state of these fuses will determine the parameter settings of the motor drive chip.

[0068] The control logic unit receives external control signals to control the adjustment operation of the fuses, and at the same time processes the status information read from the fuse array.

[0069] Similar to Embodiment 1, the buffer module contains multiple inverters for logical processing of control signals to drive subsequent N-type switching transistors.

[0070] In the N-type switch array, the drain of each N-type switch is connected to the other end of a fuse, the source is grounded, and the gate is connected to the output of the buffer module to control the on / off state of the fuse.

[0071] The digital-to-analog converter module converts the status information of the fuse array into an analog signal, which will be used to precisely control the speed and direction of the motor.

[0072] The connection and working method of each part are explained in detail below.

[0073] Each fuse in the fuse array corresponds to a parameter setting bit of the motor driver chip. The control logic unit determines which fuses need to be blown by outputting control signals based on externally input adjustment commands.

[0074] For example, when it is necessary to adjust the motor speed, the control logic unit will output a corresponding signal, causing the fuse for the corresponding speed parameter setting to blow.

[0075] The control signals output by the control logic unit first enter the buffer module for logic processing. The buffer module inverts and shapes the signals before driving the N-type switching transistor array.

[0076] When the buffer module outputs a high level, the corresponding NMOS isolated switch is turned on, causing current to flow through the fuse connected to the switch. When the current is large enough, the fuse blows.

[0077] The fuse array's fuse-blown state is transmitted to the digital-to-analog converter (DAC) module in the form of digital signals. The DAC module then converts these digital signals into corresponding analog voltage or current signals.

[0078] For example, different fuse state combinations can correspond to different analog voltage values, which will be used as control signals for the motor drive chip to precisely control the motor speed.

[0079] Different combinations of fuse array states correspond to different motor speed settings. By adjusting the fuses through the control logic unit, the analog signal output by the digital-to-analog converter module can be changed. This analog signal is input to the speed control circuit of the motor driver chip, adjusting the motor's drive voltage or current, thereby achieving precise control of the motor speed.

[0080] For example, when it is necessary to increase the motor speed, the control logic unit can blow a specific fuse to make the digital-to-analog converter output a higher analog voltage, thereby increasing the motor's drive voltage and achieving an increase in speed.

[0081] Similarly, certain combinations of fuse array states can be used to control the rotation direction of the motor. The control logic unit modifies the corresponding fuses to change the polarity or level of the analog signal output by the digital-to-analog converter module, and inputs this signal into the direction control circuit of the motor driver chip, thereby achieving precise control of the motor's rotation direction.

[0082] The fuse adjustment circuit of this embodiment can achieve high-precision control. Through fuse adjustment technology, precise control of motor speed and direction can be achieved, improving the performance of the motor drive system. Moreover, the motor parameter settings can be flexibly adjusted by adjusting the fuse according to different application requirements. Once the fuse blows, its state will remain stable and unaffected by external interference, ensuring the long-term stability of the motor drive system.

[0083] In industrial production lines, precise motor control is crucial for ensuring product quality and production efficiency. This fuse trimming circuit can be applied to various industrial motor drive systems to achieve precise control of motor speed and direction.

[0084] In smart home devices, such as smart curtains and smart fans, precise motor control can enhance the user experience. This fuse adjustment circuit can be applied to the motor driver chips of these devices to achieve precise motor control.

[0085] It should be noted that, in this embodiment, appropriate fuse material and size should be selected to ensure that the fuse does not blow accidentally during normal operation and can reliably blow when required; the driving capability of the buffer module should be strong enough to ensure reliable driving of the N-type switching transistor. At the same time, the inverter's delay time should be considered to avoid affecting the accuracy of fuse adjustment.

[0086] Example 3 Unlike Embodiment 1, the buffer module in this embodiment can be a voltage follower constructed from operational amplifiers, such as... Figure 4 As shown, the body terminal B of the N-type switch is connected to the output of the buffer module, which is the output of the operational amplifier.

[0087] The inverting input and output of the operational amplifier are connected together, and the non-inverting input is connected to the adjustment input signal.

[0088] It should be noted that there are multiple ways to implement a buffer module, and in some other implementations, other methods can also be used to achieve the same buffer effect.

Claims

1. A fuse adjustment circuit, characterized in that, include: Fuse (2), one end of which is connected to the power supply; N-type switch (1), implemented by an isolated NMOS transistor, the drain of which is connected to the other end of the fuse (2); buffer module (3), the output of which is connected to the N-type switch.

2. The fuse adjustment circuit according to claim 1, characterized in that, The buffer module includes a first inverter (3-1) and a second inverter (3-2) connected to the first inverter. The input terminal of the first inverter is the input terminal of the buffer module, and the output terminal of the second inverter is the output terminal of the buffer module.

3. A fuse adjustment circuit according to claim 2, characterized in that, The source of the N-type switch is grounded, and the gate of the N-type switch receives the adjustment input signal. The adjustment input signal passes through the first inverter (3-1) and the second inverter (3-2) in sequence and is then connected to the body terminal of the N-type switch (1).

4. A fuse adjustment circuit according to claim 3, characterized in that, The N-type switch has a parasitic NPN transistor inside. The body of the N-type switch corresponds to the base of the parasitic NPN transistor, the source of the N-type switch corresponds to the emitter of the parasitic NPN transistor, and the drain of the N-type switch corresponds to the collector of the parasitic NPN transistor. The base of the parasitic NPN transistor of the N-type switch (1) is connected to the output terminal of the second inverter (3-2). The parasitic NPN transistor is turned on when the N-type switch (1) is turned on.

5. A fuse adjustment circuit according to claim 1, characterized in that, The buffer module (3) includes: a first inverter (3-1), whose input terminal receives the adjustment input signal and whose output terminal is connected to the input terminal of the second inverter (3-2); and a second inverter (3-2), whose output terminal is connected to the body terminal of the N-type switch (1).

6. A fuse adjustment circuit according to claim 1, characterized in that, The buffer module (3) includes a voltage follower, the input of which receives a tuning input signal and the output is connected to the body of the N-type switching transistor (1).

7. A fuse adjustment circuit according to claim 2 or 5, characterized in that, The second inverter is composed of a set of PMOS transistors and NMOS transistors, with the drains of the PMOS transistors and the drains of the NMOS transistors connected together, and the gates of the PMOS transistors and the gates of the NMOS transistors connected together.

8. A fuse adjustment circuit according to claim 4, characterized in that, The conductive path of the N-type switch (1) includes the channel conductive path of the intrinsic NMOS transistor and the common-emitter amplification conductive path of the parasitic NPN transistor.

9. A fuse adjustment circuit according to claim 4, characterized in that, After the parasitic NPN transistor is turned on, the current flowing through the N-type switch (1) is 5 to 10 times the current flowing through the N-type switch (1) when the parasitic NPN transistor is not turned on.

10. A fuse adjustment circuit according to claim 7, characterized in that, The width-to-length ratio of the PMOS and NMOS transistors in the second inverter (3-2) is adjusted according to the electrical parameters of the parasitic NPN transistor of the N-type switch.

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