Display panel and display device

Abstract

This disclosure provides a display panel and display device, relating to the field of display technology, for reducing the width of the peripheral area of ​​a display panel, improving the consistency of the peripheral area width in different display panels, and reducing the difficulty of bending the display panel. The display panel has a main area and an auxiliary area, the main area including a display area and a peripheral area. The boundary between the main area and the auxiliary area is a first boundary, the dimension of the first boundary along a second direction being smaller than the maximum dimension of the display area and the auxiliary area along the second direction. Multiple scan signal lines are disposed in the main area and spaced apart along the second direction. A row of pixel circuits is electrically connected to at least one scan signal line. A gate driving circuit is disposed in the auxiliary area, and the dimension of its arrangement area along the second direction in the auxiliary area is larger than the dimension of the first boundary along the second direction. One end of a connecting line is electrically connected to the gate driving circuit, and the other end is electrically connected to a scan signal line. The above display panel is used to display images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display devices have been widely used, and people's requirements for display devices are also getting higher and higher. Among them, narrow bezels are an important development direction for display devices, and how to reduce the bezel width of display panels is a technical problem that urgently needs to be solved. Utility Model Content

[0003] The purpose of the embodiments of this disclosure is to provide a display panel and a display device for reducing the width of the peripheral area of ​​the display panel, improving the consistency of the width of the peripheral area in different display panels, and reducing the difficulty of bending the display panel.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display panel is provided. The display panel has a main area and an auxiliary area located on at least one side of the main area along a first direction. The main area includes a display area and a peripheral area surrounding the display area, and at least a portion of the auxiliary area is configured to bend to the backlight side of the main area. The boundary between the main area and the auxiliary area is a first boundary, and the dimension of the first boundary along a second direction is smaller than the maximum dimension of the display area and the auxiliary area along the second direction. The display panel includes a plurality of pixel circuits, a plurality of scan signal lines, a gate driving circuit, and a plurality of connecting lines. The plurality of pixel circuits are disposed in the display area, and the plurality of sub-pixel arrays are arranged; the first direction is the row direction of the plurality of pixel circuits, and the second direction is the column direction of the plurality of pixel circuits. The plurality of scan signal lines are disposed in the main area and are spaced apart along the second direction. A row of pixel circuits is electrically connected to at least one scan signal line. The gate driving circuit is disposed in the auxiliary area, and the dimension of the arrangement area of ​​the gate driving circuit in the auxiliary area along the second direction is larger than the dimension of the first boundary along the second direction. The two ends of the connecting line extend into the main body area and the auxiliary area, respectively. One end of the connecting line is electrically connected to the gate driving circuit, and the other end is electrically connected to a scanning signal line.

[0006] In the aforementioned display panel, the portion connecting the auxiliary area and the main area can be bent to allow at least a portion of the auxiliary area to be bent to the backlight side of the main area. The auxiliary area may not occupy the bezel width of the display device, or may occupy only a very small portion of the bezel width. The gate driving circuit is disposed within the auxiliary area, does not occupy space in the peripheral area, and when the auxiliary area is bent to the back side of the main area, the gate driving circuit is also disposed on the backlight side of the main area. This helps to reduce the width of the peripheral area in the main area, thereby facilitating the achievement of a narrow bezel in the display device. Furthermore, since the gate driving circuit is disposed on the backlight side of the main area, even when facing display panels with different pixel circuits, regardless of the number of scan driving circuits included in the gate driving circuit or whether the width of the auxiliary area changes, the width of the peripheral area will not be affected. This improves the consistency of the peripheral area width in different display panels, which is beneficial for unifying the bezel width of different display panels. Additionally, the corner of the main area near the first boundary and located in the second direction is arc-shaped, and / or, the corner of the auxiliary area near the first boundary and located in the second direction is arc-shaped. This helps reduce stress at the corners of the main and / or auxiliary areas, avoids stress concentration at the corners, and reduces the risk of collisions and damage at the corners of the main and / or auxiliary areas.

[0007] In some embodiments, the first boundary includes a trace segment and non-trace segments located on both sides of the trace segment. The plurality of connecting lines intersect the trace segment of the first boundary but do not intersect the non-trace segments. The gate driving circuit includes a plurality of first shift registers and a plurality of second shift registers. The first shift registers and the trace segment are disposed opposite each other along the first direction, and the second shift registers and the trace segment are disposed offset along the second direction. The plurality of connecting lines include a plurality of first connecting lines and a plurality of second connecting lines. The plurality of first connecting lines extend generally along the first direction and are electrically connected to the first shift register, with their other ends electrically connected to a scan signal line. The plurality of second connecting lines are electrically connected to the second shift register, and each second connecting line includes a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment connected sequentially. The first sub-segment is disposed in the auxiliary region, extends along the first direction, and is electrically connected at one end to the second shift register. The second sub-segment is disposed in the auxiliary region and extends along the second direction. The third segment extends generally along the first direction, with one end extending to the auxiliary area and the other end extending to the display area. The fourth segment extends along the second direction, and the end furthest from the third segment is electrically connected to the scan signal line.

[0008] In some embodiments, the first segment, the third segment, and the first connecting line comprise the same material and are disposed in the same layer; and / or, the second segment and the first segment are located in different film layers.

[0009] In some embodiments, in two adjacent second connection lines, the first and third segments of the first connection line are closer to the reference line than the first and third segments of the second connection line, respectively; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

[0010] In some embodiments, in two adjacent second connection lines, the first segment of the first connection line is closer to the reference line than the first segment of the second connection line, and the third segment of the first connection line is farther from the reference line than the third segment of the second connection line; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

[0011] In some embodiments, among two adjacent second connection lines, the second segment of one second connection line electrically connected to the second shift register near the reference line is closer to the main body region than the second segment of the other second connection line; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

[0012] In some embodiments, in at least two adjacent second connection lines, the dimension of the first segment of one second connection line electrically connected to the second shift register near the reference line along the first direction is greater than the dimension of the other second connection line along the first direction.

[0013] In some embodiments, the plurality of pixel circuits includes a plurality of first pixel circuit rows and a plurality of second pixel circuit rows, the first pixel circuit rows being electrically connected to the first connection line, and the second pixel circuit rows being electrically connected to the second connection line. In at least two adjacent second pixel circuit rows, the number of pixel circuits included in the row farther from the first pixel circuit row is less than the number of pixel circuits included in the row farther from the first pixel circuit row, and the distance between the row farther from the first pixel circuit row and the auxiliary region in the first direction is greater than the distance between the row farther from the first pixel circuit row and the auxiliary region in the first direction. In two second connection lines electrically connected to two cascaded second shift registers, the fourth segment of one second connection line electrically connected to a row of second pixel circuits farther from the first pixel circuit is farther from the auxiliary region than the fourth segment of the other second connection line.

[0014] In some embodiments, the main body area further includes a fan-out area located on the side of the peripheral area away from the display area along the second direction. The display panel also includes multiple data lines and multiple data fan-out lines. The multiple data lines are disposed within the display area, and one data line is electrically connected to a column of pixel circuits. Each of the multiple data fan-out lines includes a first sub-fan-out line and a second sub-fan-out line. The first sub-fan-out line is disposed within the display area and extends along the first direction, with one end electrically connected to the data line located at the edge of the display area along the first direction, and the other end extending to the middle of the display area along the first direction. The second sub-fan-out line extends along the second direction, with one end electrically connected to the first sub-fan-out line and the other end extending to the fan-out area. The fourth sub-segment and the second sub-fan-out line are made of the same material and are disposed in the same layer.

[0015] In some embodiments, the orthographic projections of the fourth sub-segment and the pixel circuit along the thickness direction of the display panel at least partially overlap.

[0016] In some embodiments, the plurality of pixel circuits includes a plurality of first pixel circuit columns and a plurality of second pixel circuit columns. The plurality of first pixel circuit columns are located on the side of the second pixel circuit columns closer to the auxiliary area. Each group of first pixel circuit columns includes at least two first pixel circuit columns. The distance between two adjacent first pixel circuit columns in a group is less than the distance between two adjacent groups of first pixel circuit columns, and the distance between two adjacent groups of first pixel circuit columns is greater than the distance between two adjacent second pixel circuit columns. The fourth sub-segment is disposed between two adjacent groups of first pixel circuit columns, and the orthographic projection of the fourth sub-segment and the pixel circuits along the thickness direction of the display panel does not coincide.

[0017] In some embodiments, the main body area further includes a fan-out area located on the side of the peripheral area away from the display area along the second direction. The display panel also includes a plurality of drive signal lines extending from the fan-out area into the auxiliary area and electrically connected to the gate drive circuit. At least one of the drive signal lines is electrically connected to the gate drive circuit along the second direction near the fan-out area. And / or, a portion of at least one drive signal line is located on the side of the gate drive circuit away from the main body area, extends along the second direction to the side of the gate drive circuit away from the fan-out area, and is electrically connected to the portion of the gate drive circuit away from the fan-out area.

[0018] In some embodiments, the plurality of drive signal lines extend from the fan-out area along the peripheral area to the auxiliary area. Alternatively, the plurality of drive signal lines include interconnected first and second portions, the first portion extending from the fan-out area along a second direction through the peripheral area on one side of the display area and into the display area, and the second portion extending from the display area along the first direction into the auxiliary area.

[0019] In some embodiments, the display panel further includes a first power line, a second power line, and a plurality of third power lines. The first power line is disposed in the peripheral area and at least partially surrounds the display area. The second power line is disposed in the auxiliary area and located on the side of the gate driving circuit closer to the main area, and extends along the second direction. The plurality of third power lines are spaced apart along the second direction and extend along the first direction, and both ends of the third power lines are electrically connected to the first power line and the second power line, respectively.

[0020] In some embodiments, the width of the second power trace is greater than the width of the first power trace.

[0021] In some embodiments, the dimension of the second power trace along the second direction is less than or equal to the dimension of the first boundary along the second direction. The two outermost third power traces along the second direction are respectively connected to the ends of the second power trace along the second direction.

[0022] In some embodiments, the orthographic projections of the plurality of connecting lines and the plurality of third power supply traces along the thickness direction of the display panel do not at least partially overlap.

[0023] In some embodiments, the auxiliary area includes a bend area adjacent to the first boundary. The plurality of connecting lines are divided into multiple groups along the second direction, each group comprising multiple connecting lines. At least one connecting line located in the central region of a group of connecting lines along the second direction is a target connecting line, which extends from the bend area to the display area along the first direction. Connecting lines located on either side of the target connecting line in a group of connecting lines include interconnected straight segments and oblique segments; the straight segments extend from the bend area to the peripheral area along the first direction, and the oblique segments extend obliquely away from the target connecting line along the direction from the peripheral area to the display area. Two adjacent straight segments belonging to two adjacent groups of connecting lines have a first interval, and two adjacent straight segments in a group of connecting lines have a second interval; the first interval is greater than the second interval. At least a portion of the third power supply trace is disposed within the first interval.

[0024] In some embodiments, the display panel further includes a plurality of virtual signal lines. The plurality of virtual signal lines are disposed in the auxiliary area and within the first interval, extending along the first direction and arranged along the second direction within the first interval. The virtual signal lines are electrically insulated from the gate driving circuit and the scan signal lines, respectively. The interval between two adjacent virtual signal lines, the interval between an adjacent virtual signal line and a straight line segment, and the interval between two adjacent straight line segments are equal.

[0025] In some embodiments, the plurality of connecting lines includes a plurality of first connecting lines and a plurality of second connecting lines. A set of connecting lines that includes both first connecting lines and second connecting lines includes a first number of connecting lines; a set of connecting lines that includes only the first connecting lines includes a second number of connecting lines; the first number is less than the second number.

[0026] In some embodiments, the main body region and the auxiliary region are equal in size along the second direction, and the ends of the main body region and the auxiliary region on the same side along the second direction are substantially flush.

[0027] In some embodiments, the corner of the main body region near the first boundary and located at the end in the second direction is arc-shaped; and / or, the corner of the auxiliary region near the first boundary and located at the end in the second direction is arc-shaped.

[0028] In some embodiments, the auxiliary region includes a bending region adjacent to the first boundary. The auxiliary region includes at least one layer of inorganic material stacked together, the inorganic material layer including a plurality of grooves disposed in the bending region.

[0029] In some embodiments, the bending axis of the bending region is located on the side of the bending region near the main body region along the center line of the bending region in the first direction.

[0030] In some embodiments, the bending radius of the bending area is 0.06 mm to 1.6 mm.

[0031] In some embodiments, the display panel has one auxiliary area; or, the display panel has two auxiliary areas.

[0032] In some embodiments, the interval between the display area and the auxiliary area is less than or equal to 0.6 mm.

[0033] On the other hand, some embodiments of this disclosure provide a display device, which includes a driving circuit board and a display panel as described in any of the above embodiments. The driving circuit board is electrically connected to the display panel.

[0034] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of a display device according to some embodiments;

[0037] Figure 2 This is a structural diagram of a display device according to some embodiments;

[0038] Figure 3A This is a structural diagram of a display panel including an auxiliary area according to some embodiments;

[0039] Figure 3B This is a structural diagram of a display panel according to some embodiments, when it includes two auxiliary areas;

[0040] Figure 4 This is a diagram showing the film layer structure of a display panel according to some embodiments;

[0041] Figure 5 This is a partial enlarged view of a display panel according to some embodiments;

[0042] Figure 6 This is a connection structure diagram showing a "near-to-near" method for the second connecting line according to some embodiments;

[0043] Figure 7 This is another partial enlarged view of a display panel according to some embodiments;

[0044] Figure 8 This is a connection structure diagram showing a "near-to-far" method for the second connecting line according to some embodiments;

[0045] Figure 9 This is a connection structure diagram of data cables when a display panel adopts FIP technology according to some embodiments;

[0046] Figure 10 This is yet another partial enlarged view of a display panel according to some embodiments;

[0047] Figure 11AThis is a structural diagram showing that, according to some embodiments, drive signal lines are arranged in the peripheral region and connected to the lower side of the gate drive circuit;

[0048] Figure 11B This is a structural diagram showing that some drive signal lines are arranged in the display area and connected to the lower side of the gate drive circuit according to some embodiments;

[0049] Figure 12 This is a structural diagram of a power supply voltage signal line according to some embodiments;

[0050] Figure 13 This is a structural diagram showing the grouping of connecting lines according to some embodiments. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0055] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0056] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0057] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0058] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0059] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0060] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0061] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, “approximately” or “about” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0063] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] See Figure 1 Embodiments of this disclosure provide a display device 1000, which is a product with image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0066] For example, the display device 1000 can be a mobile phone, wireless device, personal digital assistant (PDA), wearable device, augmented reality (AR) device, virtual reality (VR) device, handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc. For example, as Figure 1 As shown, the display device 1000 can be a mobile phone.

[0067] From the perspective of the light emission type of the display device 1000, the display device 1000 can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, or a liquid crystal display (LCD) display device. From the perspective of the form of the display device 1000, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The following describes some embodiments of this disclosure illustratively using a rectangular and flat organic light-emitting diode display device as an example. However, the embodiments of this disclosure are not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0068] See Figure 2In some embodiments, the display device 1000 may include a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board 1200 may also include other circuit structures, which will not be listed here. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition; specific limitations are not specified here.

[0069] Continue reading Figure 2 The display panel 1100 has a display area AA and a peripheral area BB. The peripheral area BB is located at least on one side of the display area AA. For example, the peripheral area BB is arranged around the display area AA. The display area AA is the area on the display panel 1100 used to display images. The display area AA has a plurality of sub-pixels P, and the sub-pixels P are the smallest light-emitting units on the display panel 1100. The peripheral area BB can be used, for example, to set control signal lines (including but not limited to clock signal lines, power supply voltage signal lines, and initialization voltage signal lines). Of course, the function of the peripheral area BB is not limited to this, and the undisclosed embodiments will not be described in detail.

[0070] At least some of the aforementioned sub-pixels P can emit light of different colors. For example, the multiple sub-pixels P include red light sub-pixels that emit red light, green light sub-pixels that emit green light, and blue light sub-pixels that emit blue light, so that the display panel can achieve color display.

[0071] Each of the multiple sub-pixels P includes a pixel circuit 100 and a light-emitting device 200. The multiple pixel circuits 100 included in the multiple sub-pixels P can be arranged in an array, that is, the multiple pixel circuits 100 are arranged in multiple rows and multiple columns. Specifically, a row of pixel circuits 100 includes multiple pixel circuits 100 arranged along a first direction X, and the multiple rows of pixel circuits 100 are arranged along a second direction Y; a column of pixel circuits 100 includes multiple pixel circuits 100 arranged along the second direction Y, and the multiple columns of pixel circuits 100 are arranged along the first direction X. That is, the first direction X is the row direction in which the multiple pixel circuits 100 are arranged, the second direction Y is the column direction in which the multiple pixel circuits are arranged, and the first direction X and the second direction Y intersect. For example, the second direction Y is perpendicular to the first direction X.

[0072] The pixel circuit 100 may include a plurality of thin film transistors (TFTs) and at least one capacitor Cst. The pixel circuit 100 is used to drive the light-emitting device 200 to emit light. Exemplarily, the pixel circuit 100 may be a "5T1C" circuit, a "7T1C" circuit, a "7T2C" circuit, or an "8T1C" circuit, etc. The embodiments of this disclosure are not limited to these, and any other pixel circuit can be considered as long as the same technical concept is applied. Here, "T" refers to a TFT, and the number before "T" indicates the number of TFTs; "C" refers to a capacitor, and the number before "C" indicates the number of capacitors Cst.

[0073] Continue reading Figure 2 The display panel 1100 may further include multiple scan signal lines GL and multiple data signal lines DL. The multiple data signal lines DL extend along a first direction X and are spaced apart along a second direction Y. A row of pixel circuits 100 is electrically connected to at least one scan signal line GL. The multiple data signal lines DL extend along the second direction Y and are spaced apart along the first direction X. One data signal line DL is electrically connected to a column of pixel circuits 100. A row of pixel circuits 100 is electrically connected to at least one scan signal line GL. The scan signal line GL is configured to transmit a scan control signal to the row of pixel circuits 100 to control the conduction and cutoff of corresponding thin-film transistors in the pixel circuits. The data signal lines DL are configured to transmit data signals to the column of pixel circuits 100 to generate corresponding drive currents in the pixel circuits.

[0074] The display panel may also include a Gate Driver on Array (GOA) circuit. The gate driver circuit 30 is electrically connected to multiple scan signal lines GL and to the pixel circuit 100 via the scan signal lines GL, and is configured to transmit scan signals to the scan signal lines GL and the pixel circuit 100. The gate driver circuit 30 may include multiple scan driver circuits, and each scan driver circuit may include multiple cascaded shift registers. A scan signal line is electrically connected to a shift register, and the shift register is configured to transmit scan signals to the scan signal line electrically connected to that shift register. Here, the gate driver circuit refers to the sum of circuits used to drive all scan signal lines, the scan driver circuit refers to circuits used to drive the same transistors in different rows of pixel circuits, and the shift register refers to the smallest circuit unit configured to output a scan signal. Depending on the structural differences of the pixel circuits, the gate driver circuit may include a varying number of scan driver circuits; for example, the gate driver circuit may include, but is not limited to, EM scan driver circuits and Gate scan driver circuits.

[0075] In the following embodiments of this disclosure, unless otherwise specified, the description of "adjacent scan signal lines" refers to two scan signal lines electrically connected to two cascaded shift registers of the same scan driving circuit. Similarly, the description of "adjacent first connection line / second connection line" refers to two first connection lines / second connection lines electrically connected to two cascaded shift registers of the same scan driving circuit.

[0076] In related technologies, the aforementioned gate driving circuit is typically located in the peripheral area of ​​the display panel. Since the gate driving circuit requires a certain lateral (width direction of the peripheral area) space, this results in a relatively large peripheral area, which is not conducive to reducing the width of the peripheral area or achieving a narrow bezel in the display device. Furthermore, for display panels with different pixel circuits, the gate driving circuit may contain different numbers of scan driving circuits. In this case, the width occupied by the gate driving circuit is unequal, leading to unequal bezel widths for different display panels, which is not conducive to unifying the bezel width across different products.

[0077] To solve at least one of the above technical problems, see [reference] Figure 3A and Figure 3B The present disclosure provides a display panel 1100, which includes a main area 11 and an auxiliary area 12 located on at least one side of the main area 11 along a first direction X. The main area 11 includes a display area AA and a peripheral area BB surrounding the display area AA. The structures of the display area AA and the peripheral area BB are described above and will not be repeated here.

[0078] At least a portion of the auxiliary area 12 is configured to be bent toward the backlight side of the main body area 11, that is, the portion of the auxiliary area 12 connected to the main body area 11 can be bent so as to bend at least a portion of the auxiliary area 12 toward the backlight side of the main body area 11. Figure 3A and Figure 3B The diagram shown is a structural diagram of the display panel 1100 in its unfolded state. The auxiliary area 12 may not occupy the width of the display device's bezel, or may occupy only a very small portion of the display device's bezel width. The backlight side of the main area 11 refers to the side furthest from the display panel used for displaying the image.

[0079] The display panel 1100 includes a gate driving circuit 30, which is disposed within an auxiliary area 12. For example, the auxiliary area 12 can be completely bent to the backlight side of the main area AA. In this way, the gate driving circuit 30 does not occupy space in the peripheral area BB. Furthermore, with the auxiliary area 12 bent to the back side of the main area 11, the gate driving circuit 30 is also disposed on the backlight side of the main area 11. This helps to reduce the width of the peripheral area BB in the main area 11, thereby facilitating the achievement of a narrow bezel in the display device. Moreover, since the gate driving circuit 30 is disposed on the backlight side of the main area 11, even when facing display panels with different pixel circuits, regardless of the number of scan driving circuits included in the gate driving circuit 30 or whether the width of the auxiliary area 12 changes, the width of the peripheral area BB will not be affected. This improves the consistency of the width of the peripheral area BB in different display panels 1100, and helps to unify the bezel width of different display panels.

[0080] For example, such as Figure 3A As shown, when the gate driving circuit 30 employs single-sided driving, the display panel 1100 may include an auxiliary area 12, which is disposed on one side of the main body area 11 along the first direction X. Alternatively, as... Figure 3B As shown, when the gate driving circuit 30 adopts a dual-sided driving method, the display panel 1100 may include two auxiliary areas 12, which are respectively disposed on opposite sides of the main body area 11 along the first direction X. For example, the two auxiliary areas 12 may be symmetrically disposed.

[0081] like Figure 3A and Figure 3B As shown, in some embodiments, the boundary between the main area 11 and the auxiliary area 12 is a first boundary L1, which extends along the second direction Y. The auxiliary area 12 may include a bending area 13 adjacent to the first boundary L1. The bending area 13 is bendable, and by bending the bending area 13, the rest of the auxiliary area 12, except for the bending area 13, can be completely bent to the backlight side of the display panel 1100.

[0082] See Figure 4In some embodiments, when the display panel 1100 is an OLED display panel, the display panel 1100 may include a substrate 20. The substrate 20 may include a semiconductor layer, at least one gate layer, and multiple inorganic material layers. The multiple inorganic material layers may include at least one of a gate insulating layer and a passivation layer. The display panel 1100 may also include a first source / drain conductive layer SD1, a first planarization layer PLN1, a second source / drain conductive layer SD2, a second planarization layer PLN2, a third source / drain conductive layer SD3, a third planarization layer PLN3, an anode layer 21, a light-emitting functional layer EL, a cathode layer 22, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, a second inorganic encapsulation layer CVD2, an insulating layer TBL, a touch electrode layer TMB, and a protective layer TOC, arranged sequentially along a direction away from the substrate 20. Among these, at least one of the first planarization layer PLN1, the second planarization layer PLN2, the third planarization layer PLN3, the light-emitting functional layer EL, and the organic encapsulation layer IJP may include organic materials, for example, all of the above-mentioned film layers may include organic materials.

[0083] The inorganic material layer may include multiple grooves 24 (Etch Bending B MASK, or EBB groove) disposed in the bending area 13. In this way, the multiple grooves 24 can reduce the bending difficulty of the bending area 13 and reduce the risk of the bending area 13 breaking.

[0084] In some embodiments, see Figure 5 The bending area 13 includes a bending axis L2, which is located on the side of the bending area 13 closer to the main body area 11 than the center line L3 along the first direction X. In other words, the bending axis L2 of the bending area 13 is closer to the main body area 11 than the center line L3. This allows the auxiliary area 12 to be bent to the backlight side of the main body area 11 to a large extent, thereby reducing the bezel width occupied by the auxiliary area 12 and helping to reduce the bezel width of the display device.

[0085] The bending radius of the bending area 13 can be 0.06mm to 1.6mm, so that as much of the auxiliary area 12 can be bent to the backlight side of the main body area 11 as possible. For example, the bending radius of the bending area 13 can be 0.06mm, 0.08mm, 1.1mm, 1.3mm or 1.6mm, etc.

[0086] like Figure 3AAs shown, in some embodiments, the dimension D1 of the first boundary L1 along the second direction Y is smaller than the maximum dimension D2 of the display area AA along the second direction Y, and smaller than the maximum dimension of the auxiliary area 12 along the second direction Y. That is, both ends of the main body area 11 and the auxiliary area 12 extend beyond the ends of the first boundary L1 along the second direction Y, meaning the ends of the main body area 11 and the auxiliary area 12 are not connected along the second direction Y. This facilitates the formation of arc-shaped corners at the ends of the main body area 11 near the auxiliary area 12 along the second direction Y, and also reduces the connection length between the main body area 11 and the auxiliary area 12, thereby reducing the bending difficulty of the auxiliary area 12 and reducing the bending stress when bending the auxiliary area 12. The dimension D4 of the arrangement area of ​​the gate driving circuit 30 within the auxiliary area 12 along the second direction Y is larger than the dimension D1 of the first boundary L1 along the second direction Y, thus increasing the arrangement space of the gate driving circuit 30.

[0087] See Figure 3A and Figure 3B In some embodiments, the size of the main body region 11 along the second direction Y is equal to the size of the auxiliary region 12 along the second direction Y, and the ends of the main body region 11 and the auxiliary region 12 on the same side along the second direction Y are approximately flush. In this way, the size D3 of the auxiliary region 12 along the second direction Y can be greatly increased while ensuring that the auxiliary region 12 can be completely bent to the backlight side of the main body region 11, which is beneficial to increasing the arrangement space of the gate driving circuit 30.

[0088] In some embodiments, such as Figure 3A and Figure 3B As shown, the corner of the main body region 11 near the first boundary L1 and located at the end in the second direction Y is arc-shaped, and / or, the corner of the auxiliary region 12 near the first boundary L1 and located at the end in the second direction Y is arc-shaped. This helps to reduce the stress at the corners of the main body region 11 and / or the auxiliary region 12, avoids stress concentration at the corners of the main body region 11 and / or the auxiliary region 12, and helps to reduce the risk of collision and damage at the corners of the main body region 11 and / or the auxiliary region 12.

[0089] See Figure 5 The display panel 1100 also includes multiple connecting lines 40, with both ends of the connecting lines 40 extending into the main area 11 and the auxiliary area 12, respectively. One end of each connecting line 40 is electrically connected to the gate driving circuit 30, and the other end is electrically connected to a scan signal line GL. The connecting lines 40 are used to electrically connect the gate driving circuit 30 to the scan signal line GL, so that the gate driving circuit 30 can transmit a scan signal to the scan signal line GL.

[0090] In some embodiments, see Figure 3A and Figure 5The first boundary L1 includes a routing segment L11 and non-routing segments L12 located on both sides of the routing segment L11. Multiple connecting lines 40 intersect with the routing segment L11 of the first boundary L1 but do not intersect with the non-routing segments L12. That is, multiple connecting lines 40 are located on the routing segment L11 of the first boundary L1, and the ends of the multiple connecting lines 40 along the second direction Y of the first boundary L1 are spaced apart. Research has found that during the bending process of the auxiliary area 12, the ends of the first boundary L1 are at greater risk of stress concentration and damage. Positioning the multiple connecting lines 40 away from the ends of the first boundary L1 helps reduce the risk of the connecting lines 40 failing under stress.

[0091] The gate drive circuit 30 includes multiple first shift registers 31 and multiple second shift registers 32. The first shift registers 31 and the trace segment L11 are arranged opposite each other along a first direction X, and the second shift registers 32 and the trace segment L11 are staggered along a second direction. Multiple connection lines 40 include multiple first connection lines 41 and multiple second connection lines 42. The multiple first connection lines 41 extend generally along the first direction X, with one end electrically connected to a first shift register 31 and the other end electrically connected to a scan signal line GL. The multiple second connection lines 42 are electrically connected to the second shift registers 32. In other words, the first shift register 31 located on the side of the trace segment L11 along the first direction X is electrically connected to the scan signal line GL through the first connection lines 41, and the second shift register 32, staggered from the trace segment L11 along the second direction Y, is electrically connected to the scan signal line GL through the second connection lines 42.

[0092] Each second connecting line 42 includes a first sub-segment 421, a second sub-segment 422, a third sub-segment 423, and a fourth sub-segment 424 connected sequentially. The first sub-segment 421 is located in the auxiliary area 12, extends along the first direction X, and is electrically connected at one end to the second shift register 32. The second sub-segment 422 is located in the auxiliary area 12 and extends along the second direction Y. The third sub-segment 423 extends entirely along the first direction X, with one end extending to the auxiliary area 12 and the other end extending to the display area AA. The fourth sub-segment 424 extends along the second direction Y, and the end furthest from the third sub-segment 423 is electrically connected to the scan signal line GL. The second connecting lines are broken line segments, which facilitates the electrical connection between the second shift register 32 and the scan signal line GL within the display area AA.

[0093] In some embodiments, the first segment 421, the third segment 423, and the first connecting line 41 are made of the same material and are disposed in the same layer, and / or the second segment 422 is located in a different film layer than the first segment 421. In this way, the first connecting line 41 and the second connecting line 42 can be arranged through two conductive layers, which can greatly reduce the wiring difficulty of the first connecting line 41 and the second connecting line 422, and also avoid short circuits between the second segment 422 and the first connecting line 41. Exemplarily, the first segment 421 and the second segment 422, as well as the second segment 422 and the third segment 423, can be connected through vias passing between them.

[0094] like Figure 5 As shown, in some embodiments, the plurality of pixel circuits 100 include a plurality of first pixel circuit rows 110 and a plurality of second pixel circuit rows 120. The first pixel circuit rows 110 are electrically connected to the first connecting line 41, and the second pixel circuit rows 120 are electrically connected to the second connecting line 42. That is, the first pixel circuit row 110 is a pixel circuit row that is disposed opposite to the trace segment L11 of the first boundary L1 along the first direction X; the second pixel circuit row 120 is a pixel circuit row that is disposed offset from the trace segment L11 of the first boundary L1 along the second direction Y. In at least two adjacent second pixel circuit rows 120, the one farther away from the first pixel circuit row 110 includes fewer pixel circuits 100 than the other.

[0095] For example, when the corner of the main area 11 is an arc-shaped corner, in the multiple rows 120 of second pixel circuits in the display area AA that are arranged opposite to the arc-shaped corner along the first direction X, the number of pixel circuits in each row 120 decreases along the second direction Y, from the middle to both ends. For example, as Figure 5 As shown, in the multi-row pixel circuits 100 located at the arc-shaped corner above the display area AA and the main body area 11, the number of pixel circuits 100 in the upper second pixel circuit row 120 is less than the number of pixel circuits 100 in the lower second pixel circuit row 120. Correspondingly, in two adjacent scan signal lines GL, the load of the scan signal line GL electrically connected to the upper second pixel circuit row 120 is less than the load of the scan signal line GL electrically connected to the lower second pixel circuit row 120.

[0096] See Figure 5 and Figure 6In some embodiments, the straight line containing the first connecting line 41 closest to the plurality of second shift registers 32 is taken as the reference line L4. Among two adjacent second connecting lines 42, the first segment 421 and the third segment 423 of the first connecting line are closer to the reference line L4 than the first segment 421 and the third segment 423 of the second connecting line. For example, among the multiple second connecting lines 42 electrically connected to the plurality of second shift registers 32 located on the same side as the plurality of first shift registers 31, the multiple first segments 421 are numbered sequentially along the second direction Y, pointing from the first side to the second side, and the multiple third segments 423 are numbered sequentially along the second direction Y, pointing from the second side to the first side. First segments 421 and third segments 423 with the same number are electrically connected by a second segment 422. In this application, the above connection method is referred to as "near-to-near," meaning that the first segment 421 closer to the reference line L4 is electrically connected to the third segment 423 closer to the reference line L4.

[0097] For example, such as Figure 5 and Figure 6 As shown, among the multiple second connection lines 42 that are electrically connected to the multiple second shift registers 32 located above the multiple first shift registers 31, the multiple first segments 421 are numbered 1, 2, 3, ..., (n-1) and (n-2) in the direction from top to bottom along the second direction Y; the multiple third segments 423 are numbered 1, 2, 3, ..., (n-1) and (n-2) in the direction from bottom to top along the second direction Y, and the first segments 421 and the multiple third segments 423 with the same number are electrically connected.

[0098] like Figure 5 and Figure 6 The connection method of the second connection lines 42 shown follows the cascading order of multiple shift registers (the order of output scan signals). Among adjacent second connection lines 42, the length of the second connection line 42 electrically connected to the previous stage second shift register 32 is longer than the length of the second connection line 42 electrically connected to the next stage second shift register 32. The resistance and parasitic capacitance of the second connection line 42 electrically connected to the previous stage second shift register 32 are both greater than those of the second connection line 42 electrically connected to the next stage second shift register 32. In other words, according to the cascading order of multiple second connection lines 42 with shift registers, the load of the multiple second connection lines 42 decreases. Correspondingly, according to the cascading order of multiple second connection lines 42 with shift registers, the load of the scan signal lines GL electrically connected to the multiple second connection lines 42 increases. This balances the total load of the different second connection lines 42 and the scan signal lines GL electrically connected to the second connection lines 42, reducing the voltage difference of the scan signals on different scan signal lines GL.

[0099] In one example, such as Figure 6As shown, the gate driving circuit 30 may include a first scan driving circuit (e.g., EM-GOA) and a second scan driving circuit (e.g., Gate-GOA). Each row of pixel circuits is electrically connected to two scan signal lines GL. Each shift register included in the first scan driving circuit is configured to transmit a first scan signal to two rows of pixel circuits, and each shift register included in the second scan driving circuit is configured to transmit a first scan signal to one row of pixel circuits. Within the main body region 11, a first scan signal line GL1 is provided for every two rows of pixel circuits, and one first scan signal line GL1 can be electrically connected to two rows of pixel circuits; a second scan signal line GL2 is provided for each row of pixel circuits, and one second scan signal line GL2 can be electrically connected to one row of pixel circuits.

[0100] See Figure 7 and Figure 8 In some embodiments, the straight line containing the first connection line 41 closest to the plurality of second shift registers 32 is taken as the reference line L4. Among two adjacent second connection lines 42, the first segment 421 of one (the first one) is closer to the reference line L4 than the first segment 421 of the other (the second one), and the third segment 423 of the first one is farther away from the reference line L4 than the third segment 423 of the second one. The above connection method is referred to as "near connection far" in this application, that is, the first segment 421 closer to the reference line L4 is electrically connected to the third segment 423 farther away from the reference line L4. For example, among the multiple second connection lines 42 that are electrically connected to the multiple second shift registers 32 located on the same side of the multiple first shift registers 31, the multiple first sub-segments 421 and the multiple third sub-segments 423 are respectively numbered in the direction of the second direction Y and from the first side (one of the upper side and the lower side) to the second side (the other of the upper side or the lower side). The first sub-segments 421 and the third sub-segments 423 with the same number are formed by an electrical connection through a second sub-segment 422.

[0101] For example, such as Figure 7 and Figure 8 As shown, among the multiple second connection lines 42 that are electrically connected to the multiple second shift registers 32 located above the multiple first shift registers 31, the multiple first sub-segments 421 and the multiple third sub-segments 423 are numbered 1, 2, 3, ..., (n-1) and (n-2) in the second direction Y from top to bottom, and the first sub-segments 421 and the multiple third sub-segments 423 with the same number are electrically connected.

[0102] like Figure 7 and Figure 8The connection method of the second connection lines 42 shown, according to the cascaded order of multiple shift registers (the order of output scan signals), means that the length of the second connection line 42 electrically connected to the previous stage second shift register 32 is approximately equal to the length of the second connection line 42 electrically connected to the next stage second shift register 32. The resistance and parasitic capacitance of the second connection line 42 electrically connected to the previous stage second shift register 32 are also approximately equal to those of the second connection line 42 electrically connected to the next stage second shift register 32. In other words, according to the cascaded order of the multiple second connection lines 42 with the shift registers, the load of the multiple second connection lines 42 is approximately equal, resulting in a uniform display effect on the display panel.

[0103] For example, when the voltage value of the scan signal output by the gate drive circuit 30 is large (strong driving capability), even if there is a certain difference in the voltage values ​​of the scan signals of adjacent scan signal lines, it will not affect the normal operation of the pixel circuit. In this case, the following can be used: Figure 5 The connection line 40 is shown in the diagram.

[0104] In one example, such as Figure 8 As shown, the gate driving circuit 30 may include a first scan driving circuit (e.g., EM-GOA) and a second scan driving circuit (e.g., Gate-GOA). Each row of pixel circuits is electrically connected to two scan signal lines GL. Each shift register included in the first scan driving circuit is configured to transmit a first scan signal to two rows of pixel circuits, and each shift register included in the second scan driving circuit is configured to transmit a first scan signal to one row of pixel circuits. Within the main body region 11, a first scan signal line GL1 is provided for every two rows of pixel circuits, and one first scan signal line GL1 can be electrically connected to two rows of pixel circuits; a second scan signal line GL2 is provided for each row of pixel circuits, and one second scan signal line GL2 can be electrically connected to one row of pixel circuits.

[0105] In some embodiments, such as Figures 5-8 As shown, taking the straight line containing the first connecting line 41 closest to the plurality of second shift registers 32 as reference line L4, among two adjacent second connecting lines 42, the second segment 422 of the second connecting line electrically connected to the second shift register 32 closest to reference line L4 is closer to the main body region 11 than the second segment 422 of the other second connecting line 42. This facilitates the formation of a ramp at the corner of the plurality of second connecting lines 42 near the auxiliary region 12, thereby forming an arc-shaped corner at the corner of the auxiliary region 12. For example, as... Figures 5-8 As shown, a slope is formed on the upper right side of multiple second segments 422 of multiple second connecting lines 42.

[0106] Continue to refer to Figures 5-8In at least two adjacent second connection lines 42, the dimension of the first segment 421 of one second connection line 42 electrically connected to the second shift register 32 near the reference line L4 along the first direction X is greater than the dimension of the other second connection line 42 along the first direction X; that is, the length of the lower first segment 421 is longer than the length of the upper first segment. This facilitates the formation of a ramp at the corners of the multiple second connection lines 42 near the auxiliary area 12, thereby forming an arc-shaped corner at the corner of the auxiliary area 12.

[0107] like Figures 5-8 As shown, in some embodiments, in at least two adjacent rows of second pixel circuits 120, the distance D5 between the row of second pixel circuits furthest from the first pixel circuit row 110 (the upper row of second pixel circuits 120) and the auxiliary area 12 in the first direction X is greater than the distance D6 between the row of second pixel circuits furthest from the first pixel circuit row 110 and the auxiliary area 12 in the first direction X. In two second connection lines 42 electrically connected to the two cascaded second shift registers 32, the fourth segment 424 of the second connection line 42 electrically connected to the row of second pixel circuits furthest from the first pixel circuit row 110 (the upper row of second pixel circuits 120) is further away from the auxiliary area 12 than the fourth segment 424 of the other second connection line 42. In other words, the fourth sub-segment electrically connected to the upper second pixel circuit row 120 is farther away from the auxiliary area 12 than the fourth sub-segment electrically connected to the lower second pixel circuit row 120. This allows a slope to be formed at the corners of the multiple fourth sub-segments 424 of the multiple second connecting lines 42 near the main body area 11, which is beneficial for forming an arc-shaped corner at the corner of the main body area 11.

[0108] See Figure 6 , Figure 8 and Figure 9In some embodiments, the main body area 11 further includes a fan-out area A1, which is located on the side of the peripheral area BB away from the display area AA along the second direction Y. The fan-out area A1 can be used to lead out multiple data signal lines DL. The display panel also includes multiple data fan-out lines 50, each of which includes a first sub-fan-out line 51 and a second sub-fan-out line 52. The first sub-fan-out line 51 is disposed within the display area AA and extends along the first direction X. One end is electrically connected to the data line DL (first data line DL1) located at the edge of the display area AA along the first direction X, and the other end extends to the middle of the display area AA along the first direction X. The second sub-fan-out line 52 extends along the second direction Y, and one end is electrically connected to the first sub-fan-out line 51. The other end extends to the fan-out area A1. The data line DL (second data line DL2) located in the middle of the display area AA along the first direction X extends directly into the fan-out area A1 along the second direction Y. In other words, the display panel 1100 employs FIAA (Fanout In AA) or FIP (Fanout In Panel) technology. Specifically, the fourth segment 424 of the second connecting line 42 and the second sub-fanout line 52 are made of the same material and are disposed in the same layer; for example, the fourth segment 424 of the second connecting line 42 is formed using the second sub-fanout line 52. Furthermore, the portion of the third segment 423 of the second connecting line 42 located within the main body area 11 can be made of the same material and be disposed in the same layer as the first sub-fanout line 51; for example, the portion of the third segment 423 of the second connecting line 42 located within the main body area 11 is formed using the first sub-fanout line 51. This eliminates the need for an additional circuit layer to form the second connecting line 42, thus reducing the manufacturing cost of the display panel 1100.

[0109] In some embodiments, the orthographic projection of the fourth sub-segment 424 and the pixel circuit 100 along the thickness direction of the display panel 1100 at least partially overlaps. That is, the arrangement of the fourth sub-segment 424 does not need to avoid the position of the pixel circuit. In this way, the impact of the arrangement of the fourth sub-segment 424 on other structures of the display panel (such as the pixel circuit) can be greatly reduced.

[0110] See Figure 10In some embodiments, the plurality of pixel circuits 100 include multiple sets of first pixel circuit columns 130A and multiple sets of second pixel circuit columns 140, with the multiple sets of first pixel circuit columns 130A located on the side of the second pixel circuit columns 140 closer to the auxiliary area 12. Each set of first pixel circuit columns 130A includes at least two first pixel circuit columns 130; the distance D7 between two adjacent first pixel circuit columns 130 in a set is less than the distance D8 between two adjacent sets of first pixel circuit columns 130A, and the distance D8 between two adjacent sets of first pixel circuit columns 130A is greater than the distance D9 between two adjacent second pixel circuit columns. That is, D7 is less than D8, and D8 is greater than D9. In other words, the pixel circuits 100 in the display area AA near the auxiliary area 12 adopt a compressed pixel circuit spacing arrangement to form a larger spacing area between adjacent sets of first pixel circuit columns 130A. The fourth sub-segment 424 is disposed between two adjacent groups of first pixel circuit columns 130A, and the orthographic projection of the fourth sub-segment 424 and the pixel circuit 100 along the thickness direction of the display panel 1100 does not coincide. In other words, by placing the fourth sub-segment 424 of the second connecting line 42 within the interval formed between two adjacent groups of first pixel circuit columns 130A, the parasitic capacitance generated between the fourth sub-segment 424 and the pixel circuit 100 can be greatly reduced, thereby reducing the load of the fourth sub-segment 424 and reducing the impact of the fourth sub-segment 424 on the pixel circuit 100.

[0111] See Figure 3A , Figure 3B , Figure 11A and Figure 11B The main area 11 also includes a fan-out area A1, which is located on the side of the peripheral area BB away from the display area AA along the second direction Y. The display panel also includes multiple drive signal lines 25, which extend from the fan-out area AA into the auxiliary area 12 and are electrically connected to the gate drive circuit 30. That is, the aforementioned multiple drive signal lines 25 are signal lines used to drive the gate drive circuit, and these multiple drive signal lines 25 may include, but are not limited to, clock signal lines and start signal lines. For example, Figure 11A and Figure 11B As shown, at least one drive signal line 25 is electrically connected to the gate drive circuit 30 along the second direction Y near the fan-out region A1, and the drive signal line 25 can drive the gate drive circuit 30 from the bottom. And / or, as... Figure 3A and Figure 3B As shown, at least one drive signal line 25 is located on the side of the gate drive circuit 30 away from the main body region 11, extends along the second direction Y to the side of the gate drive circuit 30 away from the fan-out region A1, and is electrically connected to the part of the gate drive circuit 30 away from the fan-out region A1. The drive signal line 25 can be wound around the outside of the gate drive circuit 30 to the upper side and drive the gate drive circuit 30 from the upper side.

[0112] In some embodiments, such as Figure 11A As shown, multiple drive signal lines 25 extend from the fan-out area A1 along the peripheral area BB into the auxiliary area 12. This reduces the impact of the drive signal lines 25 on the sub-pixels P within the display area AA. Alternatively, as... Figure 11B As shown, multiple drive signal lines 25 include interconnected first portions 251 and second portions 252. The first portion 251 extends from the fan-out area A1 along the second direction Y through the peripheral area BB on one side (lower side) of the display area AA and extends to the display area AA. The second portion 252 extends from the display area AA along the first direction X into the auxiliary area 12. In this way, the routing length of the drive signal lines 25 can be greatly reduced, and the load on the drive signal lines 25 can be reduced.

[0113] See Figure 12 The display panel 1100 also includes a first power line VSS1, a second power line VSS2, and multiple third power lines VSS3. The first power line VSS1 is located in the peripheral area BB and at least partially surrounds the display area AA. The second power line VSS2 is located in the auxiliary area 12 and on the side of the gate drive circuit 30 closest to the main area 11, extending along the second direction Y. The multiple third power lines VSS3 are spaced apart along the second direction Y and extend along the first direction X. The two ends of each third power line VSS3 are electrically connected to the first power line VSS1 and the second power line VSS2, respectively. In other words, the first power line VSS1 and the second power line VSS2 are connected in parallel. The presence of the second power line VSS2 in the auxiliary area 12, connected in parallel with the first power line VSS1, reduces the load on the first power line VSS1. This helps to reduce the linewidth of the first power line VSS1, thereby reducing the width of the peripheral area BB and facilitating a narrow bezel in the display device.

[0114] The line width D10 of the second power trace VSS2 is greater than the line width D11 of the first power trace VSS1. This can further reduce the line width of the first power trace VSS1, thereby reducing the width of the peripheral area BB, which is beneficial for the display device to achieve a narrow bezel.

[0115] The dimension D12 of the second power trace VSS2 along the second direction Y is less than or equal to the dimension D1 of the first boundary L1 along the second direction Y. The two outermost third power traces VSS3 along the second direction Y are respectively connected to the ends of the second power trace VSS2 along the second direction Y.

[0116] In some embodiments, the second power supply trace VSS2 is disposed on the side of the gate drive circuit 30 near the main body region 11. This reduces the length of the third power supply trace VSS3 and reduces interference between the third power supply trace VSS3 and the gate drive circuit 30.

[0117] In some embodiments, the portions of the multiple connection lines 40 and the multiple third power supply lines VSS3 within the main body region 11 do not overlap in their orthographic projection along the thickness direction of the display panel 1100. This can greatly reduce the parasitic capacitance between the connection lines 40 and the third power supply lines VSS3, thereby reducing the load on the connection lines 40.

[0118] like Figure 13 As shown, multiple connecting lines 40 are divided into multiple groups along the second direction Y. Each group includes multiple connecting lines 40. At least one connecting line 40 located in the central region of a group of connecting lines along the second direction Y is the target connecting line 40A. The target connecting line 40A extends from the bending area 13 to the display area AA along the first direction X.

[0119] A set of connecting lines 40 located on both sides of the target connecting line 40A includes a straight line segment 43 and an oblique line segment 44 that are connected to each other. The straight line segment 43 extends from the bending area 13 to the peripheral area BB along the first direction X, and the oblique line segment 44 extends obliquely away from the target connecting line 40A along the direction from the peripheral area BB to the display area AA.

[0120] There is a first interval D13 between two adjacent straight segments 43 belonging to two adjacent sets of connecting lines 40, and a second interval D14 between two adjacent straight segments 43 in a set of connecting lines; the first interval D13 is greater than the second interval D14. At least a portion of the third power supply trace VSS3 is disposed within the first interval D13, which can greatly reduce the parasitic capacitance between the third power supply trace VSS3 and the connecting line 40, thereby reducing the load on the connecting line 40.

[0121] Continue reading Figure 13 The display panel 1100 may further include multiple virtual signal lines 45, which are disposed in the auxiliary area 12 and within a first interval D13. Within the first interval D13, they extend along a first direction X and are arranged along a second direction Y. The virtual signal lines 45 are electrically insulated from the gate drive circuit 30 and the scan signal line GL, respectively. The intervals between adjacent virtual signal lines 45, between adjacent virtual signal lines 45 and straight line segments 43, and between adjacent straight line segments 43 are equal. The portions of the virtual signal lines 45, the straight line segments 43 of the connecting lines 40, and the target signal line 40A located within the auxiliary area 12 can be located on the same film layer and disposed in the same layer. The virtual signal lines 45 help improve the wiring uniformity of the connecting lines 40 and the virtual signal lines 45.

[0122] In some embodiments, when the multiple connecting lines 40 include multiple first connecting lines 41 and multiple second connecting lines 42, a group of connecting lines that simultaneously includes first connecting lines 41 and second connecting lines 42 includes a first number of connecting lines 40. A group of connecting lines 40A that only includes first connecting lines 41 includes a second number of connecting lines 40. The first number is less than the second number, which is beneficial for optimizing the arrangement space of the first connecting lines 41 and the multiple second connecting lines 42.

[0123] In some embodiments, the interval D5 between the display area AA and the auxiliary area BB is less than or equal to 0.6 mm. That is, through the above-described structural design of the display panel, the width of the peripheral area BB of the display panel can be less than or equal to 0.6 mm. This greatly reduces the width of the peripheral area BB, thereby reducing the bezel width of the display device. For example, the interval D5 between the display area AA and the auxiliary area BB can be 0.6 mm, 0.55 mm, 0.5 mm, or 0.4 mm, etc., and these embodiments will not be listed individually in this disclosure.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, The system has a main area and an auxiliary area located on at least one side of the main area along a first direction. The main area includes a display area and a peripheral area surrounding the display area. At least a portion of the auxiliary area is configured to bend to the backlight side of the main area. The boundary between the main area and the auxiliary area is a first boundary, and the dimension of the first boundary along a second direction is smaller than the maximum dimension of the display area and the auxiliary area along the second direction. The display panel includes: Multiple pixel circuits are disposed in the display area, and the multiple pixel circuits are arranged in an array; the first direction is the row direction of the multiple pixel circuits, and the second direction is the column direction of the multiple pixel circuits. Multiple scanning signal lines are disposed in the main body area and distributed at intervals along the second direction; a row of pixel circuits is electrically connected to at least one of the scanning signal lines. A gate driving circuit is disposed in the auxiliary region, and the size of the arrangement area of ​​the gate driving circuit in the auxiliary region along the second direction is larger than the size of the first boundary along the second direction; Multiple connecting lines are provided, with both ends of the connecting lines extending into the main body area and the auxiliary area, respectively. One end of one connecting line is electrically connected to the gate driving circuit, and the other end is electrically connected to one of the scanning signal lines.

2. The display panel according to claim 1, characterized in that, The first boundary includes a trace segment and non-trace segments located on both sides of the trace segment. The plurality of connecting lines intersect with the trace segment of the first boundary but do not intersect with the non-trace segments. The gate drive circuit includes a plurality of first shift registers and a plurality of second shift registers, wherein the first shift registers and the trace segment are disposed opposite to each other along the first direction, and the second shift registers and the trace segment are disposed offset along the second direction; The plurality of connection lines include a plurality of first connection lines and a plurality of second connection lines. The plurality of first connection lines extend along the first direction in their entirety and are electrically connected to the first shift register, with the other end electrically connected to one of the scan signal lines. The plurality of second connection lines are electrically connected to the second shift register, and each of the second connection lines includes a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment connected in sequence. The first sub-segment is disposed in the auxiliary area, extends along the first direction, and is electrically connected at one end to the second shift register; the second sub-segment is disposed in the auxiliary area and extends along the second direction; the third sub-segment extends along the first direction in its entirety, with one end extending to the auxiliary area and the other end extending to the display area; the fourth sub-segment extends along the second direction, and the end away from the third sub-segment is electrically connected to the scan signal line.

3. The display panel of claim 2, wherein, The first sub-segment, the third sub-segment, and the first connecting line are made of the same material and are disposed in the same layer; and / or, the second sub-segment and the first sub-segment are located in different film layers.

4. The display panel according to claim 2, characterized in that, In two adjacent second connection lines, the first and third segments of the first connection line are closer to the reference line than the first and third segments of the second connection line, respectively; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

5. The display panel according to claim 2, characterized in that, In two adjacent second connection lines, the first segment of the first connection line is closer to the reference line than the first segment of the second connection line, and the third segment of the first connection line is farther away from the reference line than the third segment of the second connection line; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

6. The display panel according to claim 2, characterized in that, Of two adjacent second connection lines, the second segment of one second connection line electrically connected to the second shift register closest to the reference line is closer to the main body region than the second segment of the other second connection line; the reference line is the straight line containing the first connection line closest to the plurality of second shift registers.

7. The display panel according to claim 6, characterized in that, In at least two adjacent second connection lines, the dimension of the first segment of one second connection line electrically connected to the second shift register near the reference line along the first direction is greater than the dimension of the other second connection line along the first direction.

8. The display panel according to claim 2, characterized in that, The plurality of pixel circuits include a plurality of first pixel circuit rows and a plurality of second pixel circuit rows, wherein the first pixel circuit rows are electrically connected to the first connection line and the second pixel circuit rows are electrically connected to the second connection line; In at least two adjacent rows of second pixel circuits, the number of pixel circuits included in the row farther from the first pixel circuit row is less than the number of pixel circuits included in the row farther from the first pixel circuit row, and the distance between the row farther from the first pixel circuit row and the auxiliary area in the first direction is greater than the distance between the row farther from the first pixel circuit row and the auxiliary area in the first direction. Of the two second connection lines electrically connected to the two cascaded second shift registers, the fourth segment of the second connection line electrically connected to a row of second pixel circuits that is farther from the first pixel circuit is farther from the auxiliary area than the fourth segment of the other second connection line.

9. The display panel of claim 2, wherein, The main body area further includes a fan-out area, which is located on the side of the peripheral area away from the display area along the second direction; the display panel further includes: Multiple data lines are arranged within the display area, with each data line electrically connected to a column of pixel circuits. Multiple data fan-out lines, each of which includes a first sub-fan-out line and a second sub-fan-out line; the first sub-fan-out line is disposed within the display area and extends along the first direction, one end of which is electrically connected to the data line located at the edge of the display area along the first direction, and the other end extends to the middle of the display area along the first direction; the second sub-fan-out line extends along the second direction, one end of which is electrically connected to the first sub-fan-out line, and the other end extends to the fan-out area; The fourth sub-segment and the second sub-fan-outline are made of the same material and are arranged in the same layer.

10. The display panel according to claim 9, characterized in that, The fourth sub-segment and the pixel circuit have at least partial overlap in their orthographic projections along the thickness direction of the display panel.

11. The display panel according to claim 2, characterized in that, The plurality of pixel circuits includes a plurality of first pixel circuit columns and a plurality of second pixel circuit columns. The plurality of first pixel circuit columns are located on the side of the second pixel circuit columns closer to the auxiliary area. A group of first pixel circuit columns includes at least two first pixel circuit columns. The distance between two adjacent first pixel circuit columns in a group is less than the distance between two adjacent groups of first pixel circuit columns, and the distance between two adjacent groups of first pixel circuit columns is greater than the distance between two adjacent second pixel circuit columns. The fourth sub-segment is disposed between two adjacent groups of the first pixel circuit columns, and the orthographic projection of the fourth sub-segment and the pixel circuit along the thickness direction of the display panel does not overlap.

12. The display panel of any one of claims 1-11, wherein, The main body area further includes a fan-out area, which is located on the side of the peripheral area away from the display area along the second direction; the display panel further includes: Multiple drive signal lines extend from the fan-out region into the auxiliary region and are electrically connected to the gate drive circuit. Wherein, at least one of the drive signal lines is electrically connected to the gate drive circuit along the second direction near the fan-out region; and / or, a portion of at least one of the drive signal lines is located on the side of the gate drive circuit away from the main body region, extends along the second direction to the side of the gate drive circuit away from the fan-out region, and is electrically connected to the portion of the gate drive circuit away from the fan-out region.

13. The display panel according to claim 12, characterized in that, Multiple drive signal lines extend from the fan-out area along the peripheral area into the auxiliary area; or, The multiple drive signal lines include a first part and a second part that are interconnected. The first part extends from the fan-out area through the peripheral area on one side of the display area along the second direction and extends to the display area. The second part extends from the display area along the first direction into the auxiliary area.

14. The display panel of any one of claims 1-11, wherein, The display panel also includes: The first power supply trace is located in the peripheral area and at least partially surrounds the display area; The second power supply trace is disposed in the auxiliary area and located on the side of the gate drive circuit closer to the main body area, and the second power supply trace extends along the second direction; Multiple third power supply traces are distributed at intervals along the second direction and extend along the first direction. The two ends of each third power supply trace are electrically connected to the first power supply trace and the second power supply trace, respectively.

15. The display panel according to claim 14, characterized in that, The width of the second power trace is greater than the width of the first power trace.

16. The display panel according to claim 14, characterized in that, The dimension of the second power trace along the second direction is less than or equal to the dimension of the first boundary along the second direction; The two outermost third power traces along the second direction are respectively connected to the ends of the second power traces along the second direction.

17. The display panel according to claim 14, characterized in that, The orthographic projections of the plurality of connecting lines and the plurality of third power supply lines along the thickness direction of the display panel do not overlap at least partially.

18. The display panel according to claim 17, characterized in that, The auxiliary area includes a bend area adjacent to the first boundary; The plurality of connecting lines are divided into multiple groups along the second direction, and each group includes multiple connecting lines. At least one of the connecting lines located in the central region of a group of connecting lines along the second direction is a target connecting line. The target connecting line extends from the bending area to the display area along the first direction. The connecting lines located on both sides of the target connecting line in a set of connecting lines include straight segments and oblique segments that are connected to each other; the straight segments extend from the bending area to the peripheral area along the first direction, and the oblique segments extend obliquely away from the target connecting line along the direction from the peripheral area to the display area. There is a first interval between two adjacent straight line segments belonging to two adjacent groups of the connecting lines, and there is a second interval between two adjacent straight line segments in a group of the connecting lines; the first interval is greater than the second interval. At least a portion of the third power supply trace is located within the first interval.

19. The display panel according to claim 18, characterized in that, The display panel also includes: Multiple virtual signal lines are disposed in the auxiliary area and within the first interval, extending along the first direction and arranged along the second direction within the first interval, and the virtual signal lines are electrically insulated from the gate driving circuit and the scan signal lines respectively. The intervals between two adjacent virtual signal lines, the intervals between adjacent virtual signal lines and the straight line segments, and the intervals between two adjacent straight line segments are all equal.

20. The display panel according to claim 18, characterized in that, The display panel also includes: The multiple connecting lines include multiple first connecting lines and multiple second connecting lines; A set of connecting lines that simultaneously includes both the first connecting line and the second connecting line, comprising a first number of connecting lines; a set of connecting lines that includes only the first connecting line, comprising a second number of connecting lines; the first number being less than the second number.

21. The display panel according to any one of claims 1 to 11, characterized in that, The main body area and the auxiliary area have the same dimensions along the second direction, and the ends of the main body area and the auxiliary area on the same side along the second direction are approximately flush.

22. The display panel according to claim 21, characterized in that, The corner of the main body area near the first boundary and located in the second direction is arc-shaped; and / or, The corner of the auxiliary area near the first boundary and located at the end in the second direction is arc-shaped.

23. The display panel according to claim 21, characterized in that, The auxiliary area includes a bend area adjacent to the first boundary; The auxiliary area includes at least one inorganic material layer stacked together, and the inorganic material layer includes a plurality of grooves disposed in the bending area.

24. The display panel according to claim 23, characterized in that, The bending axis of the bending area is located on the side of the bending area close to the main body area along the center line of the bending area in the first direction.

25. The display panel according to claim 24, characterized in that, The bending radius of the bending area is 0.06 mm to 1.6 mm.

26. The display panel according to any one of claims 1 to 11, characterized in that, The display panel has one of the aforementioned auxiliary areas; or... The display panel has two auxiliary areas.

27. The display panel according to any one of claims 1 to 11, characterized in that, The interval between the display area and the auxiliary area is less than or equal to 0.6 mm.

28. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 27; The driver circuit board is electrically connected to the display panel.

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