Drive backplane and display substrate

Abstract

This application discloses a driving backplane and a display substrate. The driving backplane includes: a substrate, a first metal driving layer, a light-absorbing layer, a first insulating layer, and a second insulating layer. The second insulating layer has a second via, and the first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via onto the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via onto the substrate, and the orthographic projection of the third via onto the substrate is located inside the orthographic projection of the corresponding second via onto the substrate. That is, the inner wall of the second via and the inner wall of the third via are at a certain distance in a direction parallel to the substrate, and at least a portion of the first insulating layer is exposed through the second via. In this embodiment, the second insulating layer is not used as a mask for etching the first insulating layer, which avoids direct reaction between the dry etching gas and the second insulating layer, thereby preventing reaction products from remaining on the surface of the conductive pads and improving the reliability of the driving backplane.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving backplane and a display substrate. Background Technology

[0002] A driving backplane is a structure used to drive light-emitting devices.

[0003] In the field of display technology, light-emitting diode (LED) chips have been widely used in display substrates due to their advantages such as pure color, wide dynamic range, high brightness, high definition, low operating voltage, low power consumption, long life, impact resistance, wide viewing angle, and stable and reliable operation.

[0004] However, when the driving backplane is used to drive the aforementioned light-emitting diodes, the reliability of the driving backplane is poor due to the presence of residual organic film on the surface of the conductive pads. Utility Model Content

[0005] This application provides a driving backplane and a display substrate. The technical solution is as follows:

[0006] According to one aspect of this application, a drive backplane is provided, the drive backplane comprising:

[0007] Base;

[0008] A first metal driving layer located on one side of the substrate, the first metal driving layer having conductive pads;

[0009] A light-absorbing layer is located on the side of the first metal driving layer away from the substrate. The orthographic projection of the light-absorbing layer on the substrate overlaps with the orthographic projection of the first metal driving layer on the substrate. The light-absorbing layer has a first via corresponding to the conductive pad. The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the conductive pad on the substrate.

[0010] A first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first metal driving layer and the light absorbing layer, and the second insulating layer is located on the side of the light absorbing layer opposite to the first metal driving layer, and the second insulating layer has a second via corresponding to the first via, and at least a portion of the second via is located inside the first via.

[0011] The first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via on the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via on the substrate, and the orthographic projection of the third via on the substrate is located inside the orthographic projection of the corresponding second via on the substrate.

[0012] Optionally, the orthographic projection of the second via on the substrate lies within the orthographic projection of the corresponding first via on the substrate.

[0013] Optionally, the second insulating layer covers the side of the light-absorbing layer away from the substrate and encloses the inner wall of the first via.

[0014] Optionally, the second insulating layer is in contact with the portion of the first insulating layer near the first via inside the first via; the first insulating layer has a first annular region, which is a region of the first insulating layer that protrudes relative to the second insulating layer and is close to the second via, and the first annular region is distributed around the third via.

[0015] Optionally, the second insulating layer is in contact with the portion of the first insulating layer near the first via inside the first via; the first insulating layer has a second annular region, which is the area where the first insulating layer and the second insulating layer are in contact.

[0016] Optionally, the surfaces of the conductive pads facing away from the substrate are all smooth surfaces, and / or,

[0017] The surface of the second insulating layer facing away from the substrate and the inner wall of the second via are both smooth surfaces.

[0018] Optionally, the angle between the inner wall of the second via and the substrate is an acute angle.

[0019] Optionally, the angle between the inner wall of the second via and the substrate ranges from 30 degrees to 60 degrees.

[0020] Optionally, the drive backplate further includes: a reflective layer located between the first metal drive layer and the light-absorbing layer; the reflective layer has a fourth via corresponding to the first via, the area of ​​the orthographic projection of the fourth via on the substrate being less than or equal to the area of ​​the orthographic projection of the corresponding first via on the substrate.

[0021] Optionally, the reflective layer is located between the light-absorbing layer and the first insulating layer, and the orthographic projection of the fourth via on the substrate covers the orthographic projection of the third via on the substrate;

[0022] Alternatively, the reflective layer is located between the first insulating layer and the first metal driving layer, and the orthogonal projection of the third via on the substrate covers the orthogonal projection of the fourth via on the substrate.

[0023] Optionally, the material of the reflective layer includes at least one of amorphous silicon, low-temperature polycrystalline silicon, and white ink.

[0024] Optionally, the edge region of the side of the substrate facing away from the first metal driving layer includes a bonding area, and the driving backplate further includes a plurality of signal leads located in the bonding area, at least a portion of the plurality of signal leads being electrically connected to the conductive pads;

[0025] The area between two adjacent signal leads is a gap region, and the orthographic projection of the gap region on the substrate overlaps with the orthographic projection of the reflective layer on the substrate.

[0026] Optionally, the drive backplane further includes: a second metal drive layer and a third insulating layer; the second metal drive layer is located on the side of the first metal drive layer near the substrate, and the third insulating layer is located between the first metal drive layer and the second metal drive layer;

[0027] The first metal driving layer further includes a first driving signal line, and the second metal driving layer includes a second driving signal line. The extension direction of the first driving signal line intersects with the extension direction of the second driving signal line. There are multiple conductive pads, at least some of which are electrically connected to the second driving signal line, and at least some of which are electrically connected to the first driving signal line.

[0028] On the other hand, a display substrate is provided, comprising: a driving backplate, and a light-emitting chip electrically connected to conductive pads of the driving backplate, wherein the driving backplate is the driving backplate of any of the above claims.

[0029] Optionally, the number of light-emitting chips is multiple, and the display substrate further includes an auxiliary light-absorbing layer located on the side of the light-emitting chips facing away from the substrate; the auxiliary light-absorbing layer is a continuous film layer covering the multiple light-emitting chips; the transmittance of the auxiliary light-absorbing layer to the light emitted by the light-emitting chips is greater than or equal to 50%.

[0030] The beneficial effects of the technical solutions provided in this application include at least the following:

[0031] In the driving backplane provided in this application embodiment, the second insulating layer has a second via, and the first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via on the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via on the substrate, and the orthographic projection of the third via on the substrate is located inside the orthographic projection of the corresponding second via on the substrate. That is, there is a certain distance between the inner wall of the second via and the inner wall of the third via in a direction parallel to the substrate, and at least a portion of the first insulating layer is exposed through the second via. Therefore, this application embodiment does not use the second insulating layer as a mask for etching the first insulating layer, which avoids direct reaction between the dry etching gas and the second insulating layer, thereby preventing reaction products from remaining on the surface of the conductive pads. This ensures effective electrical connection between the conductive pads and structures such as the light-emitting chip, thereby improving the reliability of the driving backplane. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a partial top view schematic diagram of a drive backplane provided by related technologies;

[0034] Figure 2 yes Figure 1 A schematic cross-sectional view of the provided drive backplane at point D1-D1;

[0035] Figure 3 yes Figure 1 A schematic diagram of the topography of the provided drive backplate at the second via;

[0036] Figure 4 This is a partial top view of a drive backplate provided in an embodiment of this application;

[0037] Figure 5 yes Figure 4 A schematic cross-sectional view of the provided drive backplane at point D2-D2;

[0038] Figure 6 This is a schematic diagram of the manufacturing process of a drive backplane provided in an embodiment of this application;

[0039] Figure 7 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application;

[0040] Figure 8 This is a partial top view of a first insulating layer provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the back of a drive backplate provided in an embodiment of this application;

[0042] Figure 10 This is a partial side view of a drive backplate provided in an embodiment of this application;

[0043] Figure 11 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application;

[0044] Figure 12 This is a partial enlarged view of the back of a drive backplate provided in an embodiment of this application;

[0045] Figure 13 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application;

[0046] Figure 14 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application;

[0047] Figure 15 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application;

[0048] Figure 16 This is a partial top view of another drive backplate provided in an embodiment of this application;

[0049] Figure 17 This is a partial top view of another drive backplate provided in an embodiment of this application;

[0050] Figure 18 yes Figure 17 A schematic cross-sectional view of the provided drive backplane at point D3-D3;

[0051] Figure 19 yes Figure 17 A schematic cross-sectional view of the provided drive backplane at point D4-D4;

[0052] Figure 20 This is a partial top view of another drive backplate provided in an embodiment of this application;

[0053] Figure 21 yes Figure 20 A schematic cross-sectional view of the provided drive backplane at point D5-D5;

[0054] Figure 22 This is a partial top view of a display substrate provided in an embodiment of this application;

[0055] Figure 23 yes Figure 22 A schematic cross-sectional view of the provided display substrate at point D6-D6;

[0056] Figure 24 This is a schematic diagram of another display substrate provided in an embodiment of this application.

[0057] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0059] Please refer to the relevant technologies. Figures 1 to 3 , Figure 1 This is a partial top view schematic diagram of a drive backplane provided by related technologies. Figure 2 yes Figure 1 A schematic cross-sectional view of the provided drive backplane at point D1-D1. Figure 3 yes Figure 1 A schematic diagram of the topology of the provided driving backplane at the second via is shown. The driving backplane A includes: a substrate A1, a first metal driving layer A2, a light-absorbing layer A3, a first insulating layer A4, a second insulating layer A5, a second metal driving layer A6, and a third insulating layer A7. In related technologies, the second insulating layer A5 with the second via V2 is used as a mask for etching the third via V3; therefore, the inner wall of the second via V2 is substantially flush with the inner wall of the third via V3.

[0060] However, the dry etching gas etches the second insulating layer A5 along with the first insulating layer A4. On one hand, this results in etching damage to the surface of the second insulating layer A5 facing away from the substrate A1 and the inner wall of the second opening V2, leading to poor flatness. Furthermore, in the area of ​​the inner wall of the second opening V2 closest to the substrate A1, because this area is closer to the interface between the first and second insulating layers A4 and A5, the dry etching gas can more easily penetrate the gap at the interface and cause over-etching in this area, resulting in pits being more easily etched into the inner wall of the second opening V2 closest to the substrate A1.

[0061] On the other hand, because the dry etching gas etches the second insulating layer A5 at a relatively fast rate, the reaction product C between the dry etching gas and the second insulating layer A5 cannot be carried away in time, resulting in the reaction product C remaining on the surface of the conductive pad S, such as... Figure 3As shown, the residual reaction product C mostly accumulates on the surface of the conductive pad S near the inner wall of the second opening V2. Since the second insulating layer A5 is an organic film layer, the reaction product C will affect the conductivity of the conductive pad S surface, resulting in poor reliability of the electrical connection between the conductive pad S and structures such as the light-emitting chip. For example, the residual reaction product C may prevent the light-emitting chip from effectively connecting to the conductive pad S, which in turn will prevent the driving backplane A from effectively driving the light-emitting chip to emit light, thus leading to poor reliability of the driving backplane A.

[0062] This application provides a driving backplane, please refer to... Figure 4 and Figure 5 , Figure 4 This is a partial top view of a drive backplate provided in an embodiment of this application. Figure 5 yes Figure 4 A schematic cross-sectional view of the provided drive backplane along line D2-D2. The drive backplane 10 includes: a substrate 11, a first metal drive layer 12, a light-absorbing layer 13, a first insulating layer 14, and a second insulating layer 15.

[0063] The substrate 11 is used to carry the film layer in the drive backplate 10. For example, the substrate 11 can be a glass substrate.

[0064] The first metal driving layer 12 can be located on one side of the substrate 11. Here, the first metal driving layer 12 is a metal layer with high reflectivity. Exemplarily, the material of the first metal driving layer 12 includes metallic copper. For example, the first metal driving layer 12 can be a molybdenum-niobium / copper / molybdenum-niobium (MoNb / Cu / MoNb) stacked structure. The first metal driving layer 12 has conductive pads S, which can be used for electrical connection with structures such as light-emitting chips. There can be multiple conductive pads S. Figure 4 and Figure 5 This example only uses the structure of a single conductive pad S.

[0065] The light-absorbing layer 13 can be located on the side of the first metal driving layer 12 facing away from the substrate 11. The orthographic projection of the light-absorbing layer 13 on the substrate 11 overlaps with the orthographic projection of the first metal driving layer 12 on the substrate 11. In this way, the light-absorbing layer 13 can absorb ambient light incident on the driving backplate 10, resulting in a lower degree of reflection of ambient light incident on the driving backplate 10 by the first metal driving layer 12, thereby ensuring that the reflectivity of the driving backplate 10 to ambient light is low. Furthermore, the light-absorbing layer 13 has a first via V1 corresponding to the conductive pad S. The orthographic projection of the first via V1 on the substrate 11 overlaps with the orthographic projection of the conductive pad S on the substrate 11. This ensures that the light-absorbing layer 13 does not block the conductive pad S, allowing the conductive pad S to be electrically connected to structures such as light-emitting chips.

[0066] For example, within the display area of ​​the driving backplate 10, the orthographic projection of the light-absorbing layer 13 in the driving backplate 10 onto the substrate 11 can cover the orthographic projection of the portion of the first metal driving layer 12, excluding the conductive pads S, onto the substrate 11. That is, within the display area of ​​the driving backplate 10, the portion of the first metal driving layer 12, excluding the conductive pads S, is blocked by the light-absorbing layer 13. It should be noted that the display area of ​​the driving backplate 10 refers to the area on the front of the driving backplate 10 capable of displaying an image. Typically, the front of the driving backplate 10 also includes a non-display area distributed around the display area. In one possible embodiment, the light-absorbing layer 13 in the driving backplate 10 can also be distributed within the non-display area of ​​the driving backplate 10.

[0067] Since the conductive pads S in the first metal driving layer 12 need to be connected to the light-emitting chip, and these conductive pads S can be blocked by the light-emitting chip, while the parts of the first metal driving layer 12 other than the conductive pads S are all metal parts with high reflectivity and will not be blocked by the light-emitting chip, when the light-absorbing layer 13 covers the parts of the first metal driving layer 12 other than the conductive pads S, the overall reflectivity of the light-absorbing layer 13 can be further reduced.

[0068] In this application, the driving backplane 10 may further include a driving structure layer distributed on the side of the first metal driving layer 12 facing the substrate 11, and this driving structure layer may be electrically connected to the first metal driving layer 12. Thus, under the combined action of the driving structure layer and the first metal driving layer 12, the light-emitting chip can be driven to emit light through the conductive pads S. For example, the driving structure layer may be... Figure 5 The second metal driving layer 17 is shown.

[0069] The first insulating layer 14 is located between the first metal driving layer 12 and the light-absorbing layer 13. Here, the first insulating layer 14 can provide insulation and protection for the first metal driving layer 12. When the first insulating layer 14 is in direct contact with the side of the first metal driving layer 12 away from the substrate 11, the first insulating layer 14 can prevent water and oxygen in the external environment from corroding the first metal driving layer 12 from the side away from the substrate 11, thereby effectively reducing the probability of oxidation and corrosion of the first metal driving layer 12. For example, the first insulating layer 14 can be an inorganic insulating layer. For example, the material of the first insulating layer 14 can include, but is not limited to, silicon nitride.

[0070] The second insulating layer 15 is located on the side of the light-absorbing layer 13 facing away from the first metal driving layer 12. Here, the second insulating layer 15 can protect the light-absorbing layer 13 in the driving backplate 10 to ensure that the light-absorbing layer 13 is not scratched, thus preventing a decrease in its shielding effect on the first metal driving layer 12 and the second metal driving layer 17. For example, the second insulating layer 15 can be an organic insulating layer; for example, the material of the second insulating layer 15 can include, but is not limited to, resin.

[0071] The second insulating layer 15 has a second via V2 corresponding to the first via V1, and at least a portion of the second via V2 is located inside the first via V1. For example, the portion of the second via V2 near the first insulating layer 14 is located inside the first via V1. This indicates that if the dimension of the second via V2 facing the substrate 11 is smaller than the dimension of the first via V1 facing the substrate 11, then at least a portion of the second insulating layer 15 extends into the first via V1.

[0072] The first insulating layer 14 has a third via V3 corresponding to the second via V2. Here, the second via V2 is connected to the corresponding third via V3, so that the light-emitting chip can be electrically connected to the conductive pad S through the connected second via V2 and third via V3.

[0073] Furthermore, the area of ​​the orthographic projection of the third via V3 onto the substrate 11 is smaller than the area of ​​the orthographic projection of the corresponding second via V2 onto the substrate 11, and the orthographic projection of the third via V3 onto the substrate 11 is located inside the orthographic projection of the corresponding second via V2 onto the substrate 11. That is, the outer contour of the orthographic projection of the third via V3 onto the substrate 11 does not coincide with the outer contour of the orthographic projection of the second via V2 onto the substrate 11. Therefore, there is a certain distance between the inner wall of the second via V2 and the inner wall of the third via V3 in a direction parallel to the substrate 11, and at least a portion of the first insulating layer 14 is exposed through the second via V2. This indicates that the embodiments of this application do not use the second insulating layer 15 with the second via V2 as a mask for etching the first insulating layer 14, which can avoid the direct reaction between the dry etching gas and the second insulating layer 15, thereby avoiding reaction products remaining on the surface of the conductive pad S, and thus improving the reliability of the drive backplane 10.

[0074] It should be noted that the first via V1, the second via V2, and the third via V3 all have an upper opening facing the substrate 11 and a lower opening away from the substrate 11, and the size of the upper opening is larger than the size of the lower opening. In some possible implementations, the area of ​​the orthographic projection of the second via V2 onto the substrate 11 can be the area of ​​the orthographic projection of the lower opening of the second via V2 onto the substrate 11. Similarly, when referring to the dimensions of the first via V1, the second via V2, and the third via V3 in the embodiments of this application, the size of the lower opening of each of them shall be taken as the standard.

[0075] In summary, this application provides a driving backplane, wherein a second insulating layer has a second via, and a first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via onto the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via onto the substrate, and the orthographic projection of the third via onto the substrate is located inside the orthographic projection of the corresponding second via onto the substrate. That is, the inner wall of the second via and the inner wall of the third via are at a certain distance in a direction parallel to the substrate, and at least a portion of the first insulating layer is exposed through the second via. Therefore, this application does not use the second insulating layer as a mask for etching the first insulating layer, which avoids direct reaction between the dry etching gas and the second insulating layer, thereby preventing reaction products from remaining on the surface of the conductive pads. This ensures effective electrical connection between the conductive pads and structures such as the light-emitting chip, thereby improving the reliability of the driving backplane.

[0076] In some possible implementations, at least a portion of the first insulating layer exposed through the second via is covered and protected by the intermediate layer; therefore, this exposed portion is not etched by dry etching gas. For a manufacturing process of a drive backplane based on the intermediate layer, please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of a manufacturing process for a drive backplane provided in an embodiment of this application. The manufacturing process includes:

[0077] 1. Please refer to Figure 6 In step S601, an intermediate layer P is formed on the side of the second insulating layer 15 away from the substrate 11.

[0078] In this embodiment, photoresist can be coated on the side of the second insulating layer 15 facing away from the substrate 11, and the photoresist can be patterned by an exposure and development process to form an intermediate layer P. Here, the intermediate layer P has a fifth via V5 corresponding to the second via V2. Furthermore, the intermediate layer P covers the side of the second insulating layer 15 facing away from the substrate 11 and the inner wall of the second via V5, and the intermediate layer P also covers a portion of the area where the first insulating layer 14 and the second via V2 overlap by orthographic projection.

[0079] 2. Please refer to Figure 6 In step S602, the first insulating layer 14 is etched to form the third via V3.

[0080] In this embodiment, the first insulating layer 14 can be etched using dry etching gas. The intermediate layer P protects the side of the second insulating layer 15 away from the substrate 11 and the inner wall of the second via V2, preventing the dry etching gas from reacting with the first insulating layer 14 and avoiding the problem of reaction products remaining on the surface of the conductive pad S. The intermediate layer P can also protect a portion of the overlapping area of ​​the orthographic projections of the first insulating layer 14 and the second via V2, preventing this portion of the first insulating layer 14 from being etched by the dry etching gas. This allows the area of ​​the orthographic projection of the third via V3 on the substrate 11 to be smaller than the area of ​​the orthographic projection of the corresponding second via V2 on the substrate 11, and the orthographic projection of the third via V3 on the substrate 11 to be located inside the orthographic projection of the corresponding second via V2 on the substrate 11.

[0081] 3. Please refer to Figure 6 In step S603, the intermediate layer P is removed to obtain the drive backplane.

[0082] In this embodiment, the intermediate layer P can be photoresist, which can then be removed using a photoresist stripping solution to obtain the driving backplane. Here, the patterning process for the film typically includes: photoresist coating, exposure, development, etching, and photoresist stripping. Figure 6 The manufacturing process shown involves reusing the photoresist pattern as an intermediate layer P to protect the second insulating layer 15, which can reduce manufacturing difficulty and simplify the manufacturing process.

[0083] Alternatively, please refer to Figure 4 , Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application. Figure 8 This is a partial top view of a first insulating layer provided in an embodiment of this application. The orthographic projection of the second via V2 on the substrate 11 lies within the orthographic projection of the corresponding first via V1 on the substrate 11. Since at least a portion of the second via V2 is located inside the first via V1, the area of ​​the orthographic projection of the second via V2 on the substrate 11 is less than or equal to the area of ​​the orthographic projection of the corresponding first via V1 on the substrate 11.

[0084] Optionally, the second insulating layer 15 covers the side of the light-absorbing layer 13 facing away from the substrate 11 and also covers the inner wall of the first via V1. Here, the portion of the second insulating layer 15 extending into the first via V1 covers the inner wall of the first via V1. In this case, the second insulating layer 15 can cover the light-absorbing layer 13 at various locations to ensure that the light-absorbing layer 13 is not exposed, thereby achieving a better protection effect for the light-absorbing layer 13 in the drive backplate 10.

[0085] In this application, the light-absorbing layer 13 in the drive backplane 10 includes an organic film layer made of an organic material with light-absorbing properties. For example, this organic material can be a black matrix (BM) material. That is, the light-absorbing layer 13 can be made of BM material. Because BM material has good light absorption properties, when the light-absorbing layer 13 is made of BM material, the light-absorbing layer 13 has a high degree of absorption of ambient light incident on the drive backplane 10, thereby effectively reducing the reflectivity of the drive backplane 10 to ambient light.

[0086] In some possible implementations, the BM material may include: chromium oxide (CrO) x The material may also include: organic material and a plurality of carbon particles dispersed within the organic material, wherein the carbon particles enable the light-absorbing layer 13 to have light-absorbing function. Since the drive backplate 10 needs to be immersed in an electroless gold bath during its fabrication, the solution in the electroless gold bath (usually an acidic or alkaline solution) may precipitate the carbon particles in the light-absorbing layer 13, thereby contaminating the electroless gold bath. Therefore, in this embodiment, the light-absorbing layer 13 is covered at various locations by the second insulating layer 15, ensuring that the light-absorbing layer 13 is not exposed. This also ensures that when the drive backplate 10 is immersed in the electroless gold bath, the solution in the electroless gold bath will not precipitate the carbon particles in the light-absorbing layer 13, thus preventing contamination of the electroless gold bath.

[0087] Optionally, the second insulating layer 15 is in contact with the portion of the first insulating layer 14 near the first via V1 inside the first via V1. The first insulating layer 14 has a first annular region Q1, which is a region of the first insulating layer 14 that protrudes relative to the second insulating layer 15 and is close to the second via V2. The first annular region Q1 is distributed around the third via V3. For example, as shown... Figure 4 and Figure 8 As shown, the orthographic projection of the first annular region Q1 onto the substrate 11 lies between the outer contour of the orthographic projection of the second via V2 onto the substrate 11 and the outer contour of the orthographic projection of the third via V3 onto the substrate 11, and the first annular region Q1 can be exposed through the second via V2. Here, during the etching of the third via V3, the first annular region Q1 is covered and protected by the intermediate layer P, and therefore is not etched.

[0088] In this application, both manufacturing deviations and alignment deviations may cause differences in the annular width E at various locations within the first annular region Q1. Therefore, embodiments of this application can facilitate manufacturing by limiting the minimum theoretical value of the annular width E of the first annular region Q1. Optionally, in the direction parallel to the substrate 11, the minimum theoretical value of the annular width E of the first annular region Q1 is greater than or equal to 14 micrometers. Here, as... Figures 6 to 8 As shown, the annular width E of the first annular region Q1 is related to the critical dimension bias F1 (CD bias) of the second via V2, the critical dimension bias F2 of the fifth via V5, and the overlay accuracy F3 between the intermediate layer P and the second insulating layer 15. For example, the minimum theoretical value of the annular width E of the first annular region Q1 can satisfy:

[0089] E≥1 / 2*F1+1 / 2*F2+F3;

[0090] Specifically, the critical dimensional deviation F1 of the second via V2 is the diameter deviation of the second via V2 before and after etching, and it reflects the manufacturing precision of the second via V2. For example, the critical dimensional deviation F1 of the second via V2 can be 10 ± 4 micrometers. The critical dimensional deviation F2 of the fifth via V5 is the diameter deviation of the fifth via V5 before and after etching, and it reflects the manufacturing precision of the fifth via V5. For example, the critical dimensional deviation F2 of the fifth via V5 can be 0 ± 4 micrometers. The alignment accuracy F3 between the intermediate layer P and the second insulating layer 15 reflects the alignment accuracy between the intermediate layer P and the second insulating layer 15. For example, the alignment accuracy F3 between the intermediate layer P and the second insulating layer 15 can be 5 micrometers. Based on this, it can be determined that the minimum theoretical value of the annular width E of the first annular region Q1 is greater than or equal to 14 micrometers, thereby ensuring that the first insulating layer 14 has the first annular region Q1 even in the presence of manufacturing deviations.

[0091] Optionally, the second insulating layer 15 is in contact with the portion of the first insulating layer 14 near the first via V1 inside the first via V1. The first insulating layer 14 has a second annular region Q2, which is the area where the first insulating layer 14 and the second insulating layer 15 are in contact. For example, as shown... Figure 4 and Figure 8 As shown, the orthographic projection of the second annular region Q2 on the substrate 11 is located between the outer contour of the orthographic projection of the second via V2 on the substrate 11 and the outer contour of the orthographic projection of the first via V1 on the substrate 11, and the second annular region Q2 is covered by the second insulating layer 15.

[0092] Optionally, the surface of the second insulating layer 15 facing away from the substrate 11 and the inner wall of the second via V2 are both smooth surfaces. Here, as... Figure 6As shown, during the etching process of the first insulating layer 14, an intermediate layer P can be used to cover and protect the side of the second insulating layer 15 away from the substrate 11 and the inner wall of the second via V2. In this way, the surface of the second insulating layer 15 away from the substrate 11 and the inner wall of the second via V2 will not react with the dry etching gas, thereby avoiding etching pits caused by the dry etching gas.

[0093] And / or, the surface of the conductive pad S facing away from the substrate 11 is a smooth surface. Here, since the surface of the second insulating layer 15 facing away from the substrate 11 and the inner wall of the second via V2 will not react with the dry etching gas, no reaction products will be generated, thereby ensuring that there are no residual reaction products on the surface of the conductive pad S, which can be a smooth surface, and thus ensuring effective electrical connection with structures such as light-emitting chips.

[0094] Optionally, the included angle α1 between the inner wall of the second via V2 and the substrate 11 is an acute angle. Here, since the intermediate layer P can cover and protect the inner wall of the second via V2, the dry etching gas will not cause the inner wall of the second via V2 to be etched into a pit, thereby ensuring that the included angle α1 will not change due to the etched pit and will remain an acute angle.

[0095] Optionally, the angle α1 between the inner wall of the second via V2 and the substrate 11 ranges from 30 degrees to 60 degrees. Here, in... Figure 2 In the related technologies shown, the dry etching gas tends to sink, making it easier to etch pits into the inner wall of the second aperture V2 near the substrate A1. This results in an obtuse angle between the inner wall of the second via V2 and the substrate A1 in the related technologies. However, the inner wall of the second via V2 provided in this application embodiment is smoother, and the angle α1 can be maintained in the range of 30 degrees to 60 degrees.

[0096] For some possible implementations, please refer to Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of the back of a drive backplate provided in an embodiment of this application. Figure 10This is a partial side view of a driving backplane provided in an embodiment of this application. The edge region of the substrate 11 facing away from the first metal driving layer 12 includes a bonding area B1. The driving backplane 10 also includes multiple signal leads L3 located within the bonding area B1. At least a portion of the signal leads L3 are electrically connected to conductive pads S. Here, the signal leads L3 can be directly or indirectly electrically connected to the conductive pads S. The multiple signal leads L3 within the bonding area B1 are used for bonding with driving components, enabling the driving components to be bonded to the driving backplane 10. Thus, the driving components can send driving signals to the first metal driving layer 12 through the signal leads L3, causing the corresponding light-emitting chips to be illuminated. When the driving components are bonded to the back of the driving backplane 10, the driving components do not occupy the space on the front of the driving backplane 10, resulting in a narrower frame width for the driving backplane 10.

[0097] Optionally, the drive backplane 10 may further include: a plurality of connection traces L4 electrically connected to a plurality of signal leads L3, a portion of which is located on the side of the substrate 11 near the first metal drive layer 12, and this portion of the connection traces L4 may be electrically connected to the drive structure layer in the drive backplane 10. Another portion of the connection traces L4 is located on the side of the substrate 11, and the end of this portion of the connection traces L4 facing the back of the drive backplane 10 may be electrically connected to the corresponding signal lead L3.

[0098] In this process, multiple connection traces L4 and multiple signal leads L3 are formed in the same step. For example, a laser etching process can be used to simultaneously form multiple connection traces L4 and multiple signal leads L3. For instance, after the driver backplane is fabricated, a conductive layer can be sputtered into the edge region on the front side of the driver backplane, the side surface of the driver backplane, and the bonding area on the back side of the driver backplane. Then, a single laser etching process can be performed on this conductive layer to simultaneously form multiple connection traces L4 and multiple signal leads L3.

[0099] It should be noted that during the laser etching process to form multiple signal leads L3 located within the bonding region B1, laser irradiation of the bonding region B1 is required. During this process, the laser may penetrate the substrate 11 and irradiate portions of the light-absorbing layer 13 distributed within the bonding region B1. Furthermore, the light-absorbing layer 13 is made of a light-absorbing organic material. Consequently, the light-absorbing layer 13 may exhibit bubbling under laser irradiation, resulting in low flatness.

[0100] Therefore, please refer to Figure 11 , Figure 11This is a schematic diagram of another drive backplane structure provided in this application embodiment. The drive backplane 10 may further include a reflective layer 16 located between the substrate 11 and the light-absorbing layer 13. The orthographic projection of the reflective layer 16 onto the substrate 11 may overlap with the orthographic projection of the light-absorbing layer 13 onto the substrate 11. The reflective layer 16 can reflect laser light that passes through the substrate 11 and illuminates the light-absorbing layer 13, ensuring that the laser light does not illuminate the light-absorbing layer 13. This effectively avoids the defective phenomenon of bulging in the light-absorbing layer 13, resulting in higher flatness of the light-absorbing layer 13 and thus higher reliability of the drive backplane 10.

[0101] Optionally, the reflective layer 16 may be made of at least one of amorphous silicon, low-temperature polycrystalline silicon, or white ink.

[0102] When the material in the reflective layer 16 includes amorphous silicon, which is an inorganic insulating material with a high refractive index, laser light incident on the amorphous silicon (e.g., laser light with a wavelength between 350 nm and 390 nm) is easily reflected. Furthermore, the thickness of the reflective layer 16 ranges from 500 angstroms to 2000 angstroms, ensuring that laser light incident on the reflective layer 16 is reflected and does not strike the light-absorbing layer 13.

[0103] When the material in the reflective layer 16 includes low-temperature polycrystalline silicon, which is a semiconductor material and also has a high refractive index, laser light incident on the low-temperature polycrystalline silicon (e.g., laser light with a wavelength between 350 nm and 390 nm) is easily reflected by it. Furthermore, the thickness of the reflective layer 16 ranges from 500 angstroms to 2000 angstroms, so that laser light incident on the reflective layer 16 can be reflected by the reflective layer 16, preventing the laser light from illuminating the light-absorbing layer 13.

[0104] When the material of the reflective layer 16 includes white ink, the white ink is an organic insulating material with scattering properties, and the thickness of the reflective layer 16 ranges from 0.5 micrometers to 3 micrometers, the laser light irradiated on the reflective layer 16 can be reflected by the reflective layer 16, and the reflected laser light is emitted in a scattered form, so that the laser light will not irradiate the light-absorbing layer 13.

[0105] Alternatively, please refer to Figure 12 , Figure 12This is a partially enlarged view of the back of a drive backplane provided in an embodiment of this application. The area between two adjacent signal leads L3 is the spacer region B2. During the process of forming multiple signal leads D1 located in the bonding region B1 using laser etching, the laser needs to irradiate the spacer region C so that the metal portion in the spacer region C can be etched away under the irradiation of the laser. Here, the orthographic projection of the spacer region B2 on the substrate 11 overlaps with the orthographic projection of the reflective layer 16 on the substrate 11, which also avoids the influence of the laser on the light-absorbing layer 13.

[0106] In this application, the reflective layer 16, located between the substrate 11 and the light-absorbing layer 13, can be positioned in various ways. Several optional implementation methods are illustrated below:

[0107] In the first optional implementation, please refer to... Figure 11 and Figure 13 , Figure 13 This is a schematic diagram of another drive backplane provided in an embodiment of this application. The reflective layer 16 is located between the first metal drive layer 12 and the light-absorbing layer 13. The reflective layer 16 has a fourth via V4 corresponding to the first via V1. The area of ​​the orthographic projection of the fourth via V4 onto the substrate 11 is less than or equal to the area of ​​the orthographic projection of the corresponding first via V1 onto the substrate 11.

[0108] Here, by setting the dimensions of the first via V1 and the corresponding fourth via V4, it is ensured that the orthogonal projection of the light-absorbing layer 13 on the substrate 11 is within the orthogonal projection of the reflective layer 16 on the substrate 11. During the process of forming multiple signal leads D1 located in the bonding region B1 using laser etching, the laser irradiating the bonding region B1, after passing through the substrate 11 and the first metal driving layer 12, can be completely reflected by the reflective layer 16 to ensure that the laser does not irradiate the light-absorbing layer 13.

[0109] Optionally, the reflective layer 16 is located between the light-absorbing layer 13 and the first insulating layer 14, and the orthographic projection of the fourth via V4 on the substrate 11 covers the orthographic projection of the third via V3 on the substrate 11. This includes the following two cases:

[0110] One situation is as follows Figure 11As shown, the size of the fourth via V4 is larger than the size of the third via V3. In this case, the fourth via V4 in the reflective layer 16 and the first via V1 in the light-absorbing layer 13 can be formed simultaneously in the same patterning process. Therefore, the area of ​​the orthographic projection of the fourth via V4 onto the substrate 11 is equal to the area of ​​the orthographic projection of the corresponding first via V1 onto the substrate 11, and the second via V2 is also located inside the fourth via V4, meaning the second insulating layer 15 also covers the inner wall of the fourth via V4. Here, the patterning process can include photoresist coating, exposure, development, etching, and photoresist stripping. In this case, the reflective layer 16 and the light-absorbing layer 13 can be formed sequentially, and then the first via V1 can be formed in the light-absorbing layer 13 using a single patterning process, and the fourth via V4, which communicates with the first via V1, can be formed in the reflective layer 16. This effectively simplifies the process.

[0111] Another case is as follows Figure 13 As shown, the size of the fourth via V4 is equal to the size of the third via V3. In this case, the fourth via V4 in the reflective layer 16 and the third via V3 in the first insulating layer 14 can be formed simultaneously in the same patterning process. Therefore, the area of ​​the orthographic projection of the fourth via V4 onto the substrate 11 is smaller than the area of ​​the orthographic projection of the corresponding first via V1 onto the substrate 11. This effectively simplifies the manufacturing process. It should be noted that when the fourth via V4 in the reflective layer 16 and the third via V3 in the first insulating layer 14 are formed simultaneously in the same patterning process, the material of the reflective layer 16 can be amorphous silicon and / or low-temperature polycrystalline silicon to ensure that all etched layers are inorganic.

[0112] Alternatively, please refer to Figure 14 , Figure 14 This is a schematic diagram of another drive backplane structure provided in an embodiment of this application. The reflective layer 16 is located between the first insulating layer 14 and the first metal drive layer 12. The orthographic projection of the third via V3 on the substrate 11 covers the orthographic projection of the fourth via V4 on the substrate 11. That is, the size of the third via V3 can be greater than or equal to the size of the fourth via V4.

[0113] When the size of the fourth via V4 is equal to the size of the third via V3, the fourth via V4 in the reflective layer 16 and the third via V3 in the first insulating layer 14 can also be formed simultaneously by the same patterning process. Similarly, in this case, the material of the reflective layer 16 can be amorphous silicon and / or low-temperature polycrystalline silicon to ensure that the etched films are all inorganic films.

[0114] For the second optional implementation, please refer to... Figure 15 , Figure 15This is a schematic diagram of another driving backplate provided in an embodiment of this application. The reflective layer 16 can be located on the side of the first metal driving layer 12 near the substrate 11.

[0115] The drive backplane 10 may further include a second metal drive layer 17 located on the side of the first metal drive layer 12 near the substrate 11. A reflective layer 16 may be located between the second metal drive layer 17 and the substrate 11. In this way, the laser light irradiating the bonding area B1, after passing through the substrate 11, can be reflected by the reflective layer 16 without passing through the first metal drive layer 12, resulting in high efficiency of the reflective layer 16 in reflecting the laser light.

[0116] In some possible implementations, such as Figure 15 As shown, the drive backplane 10 also includes a second metal drive layer 17, a third insulating layer 18, and a passivation layer 19.

[0117] The second metal driving layer 17 is located on the side of the first metal driving layer 12 closest to the substrate 11. The second metal driving layer 17 and the first metal driving layer 12 can be electrically connected through vias provided in the third insulating layer 18. In this case, the first metal driving layer 12 and the second metal driving layer 17 work together to drive the light-emitting chip to emit light, and the display substrate using this type of driving backplate 10 must simultaneously include both the light-emitting chip and the driving chip.

[0118] The third insulating layer 18 is located between the first metal driving layer 12 and the second metal driving layer 17, and provides insulation between the first metal driving layer 12 and the second metal driving layer 17. The third insulating layer 18 may include: a first inorganic insulating layer 181, an organic insulating layer 182, and a second inorganic insulating layer 183 stacked in a direction opposite to the substrate 11. For example, the materials of the first inorganic insulating layer 181 and the second inorganic insulating layer 183 include, but are not limited to, silicon nitride. The materials of the organic insulating layer 182 include, but are not limited to, resin.

[0119] For example, the third insulating layer 18 may have a sixth via V6, such that a portion of the structure in the first metal driving layer 12 can be electrically connected to a portion of the structure in the second metal driving layer 17 through the fifth via V6.

[0120] The passivation layer 19 is located between the second metal driving layer 17 and the substrate 11. Here, the passivation layer 19 ensures that water and oxygen from the external environment do not corrode the first metal driving layer 12 and the second metal driving layer 17 from the side of the second metal driving layer 17 closest to the substrate 11, thereby further reducing the probability of oxidation and corrosion of the first metal driving layer 12 and the second metal driving layer 17. For example, the material of the passivation layer 19 includes, but is not limited to, silicon nitride.

[0121] Alternatively, please refer to Figure 16 , Figure 16 This is a partial top view of another driving backplane provided in this application embodiment. The first metal driving layer 12 further includes a first driving signal line L1, and the second metal driving layer 17 includes a second driving signal line L2. The extension direction of the first driving signal line L1 intersects the extension direction of the second driving signal line L2.

[0122] There can be multiple conductive pads S. At least some of the conductive pads S are electrically connected to the second drive signal line L2, and at least some of the conductive pads S are electrically connected to the first drive signal line L1.

[0123] When the driving backplate 10 is applied to a display substrate, the light-emitting units in the display substrate can be arranged in multiple rows and columns. Correspondingly, there are multiple first driving signal lines L1 and multiple second driving signal lines L2. The multiple second driving signal lines L2 in the second metal driving layer 17 can include multiple sets of second driving signal lines L2 corresponding to multiple columns of light-emitting units. Each set of second driving signal lines L2 can be electrically connected to a corresponding column of light-emitting units in the display substrate. The multiple first driving signal lines L1 in the first metal driving layer 12 can correspond to multiple rows of light-emitting units, and each first driving signal line L1 can be electrically connected to a corresponding row of light-emitting units. The orthographic projection of a column of light-emitting units on the substrate 11 can overlap with the orthographic projection of a corresponding set of second driving signal lines L2 on the substrate 11, and a row of light-emitting units can be distributed between two adjacent first driving signal lines L1.

[0124] For example, a set of second driving signal lines L2 connected to a row of light-emitting units in the display substrate may include: an anode driving signal line L21, a data signal line L22, and a ground line L23, and a first driving signal line L1 connected to a row of light-emitting units may be a power signal line.

[0125] The light-emitting unit in the display substrate may include a driver chip and at least one light-emitting chip. In this case, the plurality of conductive pads S distributed within the first metal driving layer 12 of the display substrate may include a first pad group S10 for fixed connection with the light-emitting chip, a second pad group S20 for fixed connection with the driver chip, and a third pad group S30 for electrical connection with the driving component. Here, at least some of the conductive pads S can satisfy the following condition: the area of ​​the orthographic projection of the third via V3 on the substrate 11 is smaller than the area of ​​the orthographic projection of the corresponding second via V2 on the substrate 11, and the orthographic projection of the third via V3 on the substrate 11 is located inside the orthographic projection of the corresponding second via V2 on the substrate 11. This can prevent reaction products from remaining on the surface of at least some of the conductive pads S, thereby improving the reliability of the driving backplane 10.

[0126] Optionally, the orthographic projection of the first pad group S10 on the substrate 11 may lie within the orthographic projection of the anode drive signal line L21 on the substrate 11; the orthographic projection of the second pad group S20 on the substrate 11 may lie within the orthographic projection of the ground line L23 on the substrate 11. Here, the first pad group S10 may include: a first conductive pad S1 and a second conductive pad S2. The second pad group S20 may include: a third conductive pad S3, a fourth conductive pad S4, and a fifth conductive pad S5.

[0127] A portion of the second driving signal lines L2, which are electrically connected to the light-emitting unit, are used to electrically connect with the first conductive pad S1 in the first pad group S10. For example, the first metal driving layer 12 may further include a first adapter electrode R1. The anode driving signal line L21 in this set of second driving signal lines L2 can be electrically connected to the first conductive pad S1 through the first adapter electrode R1.

[0128] The second conductive pad S2 in the first pad group S10 is electrically connected to the third conductive pad S3 in the second pad group S20. For example, the first metal driving layer 12 may further include a second transition electrode R2. The first conductive pad S1 can be electrically connected to the third conductive pad S3 through the second transition electrode R2.

[0129] Another portion of the second driving signal lines L2 in a set electrically connected to the light-emitting unit is used for electrical connection to the fourth conductive pad S4 in the second pad group S20. For example, the first metal driving layer 12 may also include a third transition electrode R3. The data signal line L22 in this set of second driving signal lines L2 can be electrically connected to a fourth conductive pad S4 through a third transition electrode R3; the ground line L23 in this set of second driving signal lines L2 can be electrically connected to another fourth conductive pad S4 through another third transition electrode R3.

[0130] The first driving signal line L1, which is electrically connected to the light-emitting unit, is used for electrical connection to the fifth conductive pad S5 in the second pad group S20. For example, the first metal driving layer 12 may further include a fourth transition electrode R4. The first driving signal line L1 can be electrically connected to the fifth conductive pad S5 through the fourth transition electrode R4.

[0131] Please refer to the following in this application: Figures 17 to 19 , Figure 17 This is a partial top view of another drive backplate provided in an embodiment of this application. Figure 18 yes Figure 17 A schematic cross-sectional view of the provided drive backplane at point D3-D3. Figure 19 yes Figure 17 A schematic cross-sectional view of the provided drive backplane at point D4-D4, here, Figure 17 The drive backplane 10 shown is a drive backplane 10 treated with a chemical gold plating process. The chemical gold plating process involves plating a layer of nickel-gold alloy N onto the surface of the conductive pads to enhance their oxidation resistance and conductivity. Furthermore, this embodiment of the application also conducted an adhesion test on the drive backplane 10 using cross-cut adhesive tape. Figures 17 to 19 It can be seen that after the chemical gold process and adhesion test, there is no obvious difference on the surface of the conductive pad, there are no gaps between the film layers, and the thickness and shape of each film layer are normal. This shows that the driving backplate 10 provided in the embodiment of this application has good chemical resistance and film adhesion.

[0132] In some possible implementations, this application can also remove residual reaction products on the surface of the conductive pads by increasing the etching time. Please refer to [reference needed]. Figure 20 and Figure 21 , Figure 20 This is a partial top view of another drive backplate provided in an embodiment of this application. Figure 21 yes Figure 20 A cross-sectional schematic diagram of the provided drive backplane at point D5-D5 is shown. The drive backplane 10 includes: a substrate 11, a first metal drive layer 12, a light-absorbing layer 13, a first insulating layer 14, and a second insulating layer 15. A second via V2 in the second insulating layer 15 communicates with a third via V3 in the first insulating layer 14, and the inner wall of the second via V2 is substantially flush with the inner wall of the third via V3.

[0133] Increasing the etching time can effectively remove residual reaction products on the surface of the conductive pad S, but it also leads to over-etching of the second insulating layer 15 and the surface of the conductive pad S. Therefore, Figure 21 In the illustrated embodiment, the thickness of the second insulating layer 15 is less than that in the above embodiments, and Figure 21 In the illustrated embodiment, the roughness of the conductive pad S is greater than that of the conductive pad S in the above embodiments. Furthermore, Figure 21 In the illustrated embodiment, the production cycle of the drive backplane 10 is greater than that of the drive backplane 10 in the above embodiments.

[0134] For example, in this embodiment of the application, the etching time can range from 100 seconds to 200 seconds during the etching of the first insulating layer 14 to form the third via V3. In contrast, the etching time in related technologies is generally 60 seconds to 70 seconds.

[0135] In summary, this application provides a driving backplane, wherein a second insulating layer has a second via, and a first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via onto the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via onto the substrate, and the orthographic projection of the third via onto the substrate is located inside the orthographic projection of the corresponding second via onto the substrate. That is, the inner wall of the second via and the inner wall of the third via are at a certain distance in a direction parallel to the substrate, and at least a portion of the first insulating layer is exposed through the second via. Therefore, this application does not use the second insulating layer as a mask for etching the first insulating layer, which avoids direct reaction between the dry etching gas and the second insulating layer, thereby preventing reaction products from remaining on the surface of the conductive pads. This ensures effective electrical connection between the conductive pads and structures such as the light-emitting chip, thereby improving the reliability of the driving backplane.

[0136] On the other hand, this application provides a display substrate as an embodiment; please refer to [reference needed]. Figure 22 and Figure 23 , Figure 22 This is a partial top view of a display substrate provided in an embodiment of this application. Figure 23 yes Figure 22 A schematic cross-sectional view of the provided display substrate at point D6-D6. The display substrate 00 includes: a driving backplate 10, and a light-emitting chip 20 electrically connected to the conductive pads of the driving backplate 10. The driving backplate 10 is any of the driving backplates provided in the above embodiments.

[0137] In one possible implementation, the light-emitting chip 20 may include an LED, and the driving backplane 10 may directly drive the LED to emit light. It should be noted that the LED may be a regular-sized LED, a mini-LED, or a micro-LED.

[0138] In another possible implementation, the display substrate 00 further includes a driver chip 30. Here, both the light-emitting chip 20 and the driver chip 30 need to be electrically connected to the first metal driving layer 12 in the driving backplane 10 via conductive pads S. In this case, the light-emitting chip 20 needs to be driven to emit light simultaneously through the driving backplane 10 and the driver chip 30.

[0139] For example, such as Figure 16 and Figure 22As shown, the light-emitting unit in the display substrate may include a driving chip 30 and at least one light-emitting chip 20. For example, the number of light-emitting chips 20 in the light-emitting unit may be three, which may be a red light-emitting chip 20a for emitting red light, a green light-emitting chip 20b for emitting green light, and a blue light-emitting chip 20c for emitting blue light. In this case, the number of first pad groups S10 is also three, and these three first pad groups S10 may be electrically connected to the red light-emitting chip 20a, the green light-emitting chip 20b, and the blue light-emitting chip 20c, respectively.

[0140] Here, the red light-emitting chip 20a, the green light-emitting chip 20b, and the blue light-emitting chip 20c in the light-emitting unit each have two solder feet, which are the positive solder foot and the negative solder foot, respectively.

[0141] The positive terminal of the red light-emitting chip 20a can be soldered to the first conductive pad S1 in the corresponding first pad group S10, so that the positive terminal of the red light-emitting chip 20a can be connected to the corresponding anode drive signal line L21 through the first conductive pad S1. The negative terminal of the red light-emitting chip 20a can be soldered to the second conductive pad S2 in the corresponding first pad group S10.

[0142] The positive terminal of the green light-emitting chip 20b can be soldered to the first conductive pad S1 in the corresponding first pad group S10, so that the positive terminal of the green light-emitting chip 20b can be connected to the corresponding anode drive signal line L21 through this first conductive pad S1. The negative terminal of the green light-emitting chip 20b can be soldered to the second conductive pad S2 in the corresponding first pad group S10.

[0143] The positive terminal of the blue LED chip 20c can be soldered to the first conductive pad S1 in the corresponding first pad group S10, so that the positive terminal of the blue LED chip 20c can be connected to the corresponding anode drive signal line L21 through this first conductive pad S1. The negative terminal of the blue LED chip 20c can be soldered to the second conductive pad S2 in the corresponding first pad group S10.

[0144] The driver chip 30 in the light-emitting unit has six solder pins, which are: power signal input pin, data signal input pin, ground pin, and three signal output pins corresponding to the three light-emitting chips 20.

[0145] The three signal output pins of the driver chip 30 can be soldered to the three third conductive pads S3 in the second pad group S20, respectively. Since the three third conductive pads S3 are electrically connected to the three second conductive pads S2 in the three first pad groups S10, the three signal output pins of the driver chip 30 can be electrically connected to the negative electrode pins of the three light-emitting chips 20, respectively.

[0146] The power signal input pin of the driver chip 30 can be soldered to a fifth conductive pad S5 in the second pad group S20, so that the power signal input pin can be connected to the power signal line (i.e. the first drive signal line L1) through this fifth conductive pad S5.

[0147] The data signal input pin of the driver chip 30 can be soldered to a fourth conductive pad S4 in the second pad group S20, so that the data signal input pin can be connected to the data signal line L22 through this fourth conductive pad S4.

[0148] The grounding pin of the driver chip 30 can be soldered to another fourth conductive pad S4 in the second pad group S20, so that the grounding pin can be connected to the grounding line L23 through this fourth conductive pad S4.

[0149] In this configuration, when the display substrate 00 needs to control the light-emitting unit to emit light, a power drive signal can be applied to the power signal line electrically connected to the light-emitting unit within the display substrate 00, and a data drive signal can be applied to the data signal line L22 electrically connected to the light-emitting unit. Thus, after the driver chip 30 in the light-emitting unit receives the power drive signal through its power signal input pin, the driver chip 30 can be in a working state. Furthermore, after the driver chip 30 receives the data signal through its data signal input pin, it can generate three cathode signals corresponding to the three light-emitting chips 20 based on the data signal. These three cathode signals can be transmitted to the negative electrode pins of the three light-emitting chips 20 through three signal output pins, respectively. Since the positive electrode of the light-emitting chip 20 is always connected to the anode signal applied by the anode drive signal line L21, after the light-emitting chip 20 receives both the anode and cathode signals, it can emit light of a corresponding intensity.

[0150] It should be noted that, in order to simplify the wiring structure within the display substrate 00, at least two of the positive electrode pins of the red light-emitting chip 20a, the green light-emitting chip 20b, and the blue light-emitting chip 20c can be connected to the same anode drive signal line L21. Since the light-emitting characteristics of the red light-emitting chip 20a differ significantly from those of the green light-emitting chip 20b and the blue light-emitting chip 20c, while the light-emitting characteristics of the green light-emitting chip 20b are relatively similar to those of the blue light-emitting chip 20c, the positive electrode pins of the green and blue light-emitting chips 20b can be connected to the same anode drive signal line L21, while the positive electrode pin of the red light-emitting chip 20a can be connected to different anode drive signal lines L21. In this case, the first conductive pad S1 soldered to the positive electrode pin of the green light-emitting chip 20b and the first conductive pad S1 soldered to the positive electrode pin of the blue light-emitting chip 20c can be a single integrated structure. That is, the positive electrode pin of the green light-emitting chip 20b and the positive electrode pin of the blue light-emitting chip 20c can be soldered to the same first conductive pad S1, while the positive electrode pin of the red light-emitting chip 20a can be soldered to another first conductive pad S1.

[0151] In the embodiments of this application, the colors of the outer surfaces of different light-emitting chips 20 may vary greatly, and there is also a significant difference between the colors of the outer surfaces of the light-emitting chips 20 and the outer surfaces of the driving chips 30.

[0152] Therefore, please refer to Figure 24 , Figure 24 This is a schematic diagram of another display substrate structure provided in this application embodiment. The number of light-emitting chips 20 is multiple, and the display substrate 00 also includes an auxiliary light-absorbing layer 40 located on the side of the light-emitting chips 20 facing away from the substrate 11. The auxiliary light-absorbing layer 40 is a continuous film layer covering the multiple light-emitting chips 20. Here, the auxiliary light-absorbing layer 40 is often also referred to as a black film. When the auxiliary light-absorbing layer 40 covers multiple light-emitting chips 20, it can make the outer surfaces of the multiple light-emitting chips 20 appear black, thereby effectively eliminating color differences on the outer surfaces of different light-emitting chips 20.

[0153] In some examples, the auxiliary light-absorbing layer 40 is located between adjacent light-emitting chips 20 and on the surface of the light-emitting chips 20 away from the driving backplate 10. In implementation, the orthographic projection of each light-emitting chip 20 onto the auxiliary light-absorbing layer 40 is located inside the auxiliary light-absorbing layer 40, thereby protecting the surface of the light-emitting chip 20 and stably fixing the light-emitting chip 20 onto the driving backplate 10.

[0154] It should be noted that the auxiliary light-absorbing layer 40 can also cover both the light-emitting chip 20 and the driving chip 30, which can effectively eliminate the color difference between the outer surfaces of the light-emitting chip 20 and the driving chip 30.

[0155] Optionally, the auxiliary light-absorbing layer 40 is made of black resin, for example, silicone doped with black particles.

[0156] Optionally, the transmittance of the auxiliary light-absorbing layer 40 to the light emitted by the light-emitting chip 20 is greater than or equal to 10%, for example, greater than or equal to 50%. The transmittance of the auxiliary light-absorbing layer 40 can be determined according to the luminous intensity of the light-emitting chip and the performance requirements of the display panel.

[0157] In practical applications, the transmittance of the auxiliary light-absorbing layer 40 can be determined as follows: First, without the auxiliary light-absorbing layer 40, the light-emitting chips of the display substrate are controlled to emit light, and the luminance of the display substrate is detected by a luminance meter to obtain a first luminance. Then, the auxiliary light-absorbing layer 40 is disposed on the display substrate, and the light-emitting chips of the display substrate are controlled to emit light, and the luminance of the display substrate is detected again by a luminance meter to obtain a second luminance. The ratio of the second luminance to the first luminance is determined as the transmittance of the auxiliary light-absorbing layer 40. The display substrate without the auxiliary light-absorbing layer 40 and the display substrate with the auxiliary light-absorbing layer 40 emit light under the same driving conditions (e.g., driving voltage or driving current). The unit of luminance can be nits, etc.

[0158] Optionally, the display substrate 00 can be used in a display device. This display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The display device may further include a driving component. The driving component is electrically connected to the second metal driving layer 17 and the first metal driving layer 12 in the display substrate 00, and is used to provide driving signals through the second metal driving layer 17 and the first metal driving layer 12.

[0159] In summary, this application provides a display substrate in which a second insulating layer has a second via, and a first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via on the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via on the substrate, and the orthographic projection of the third via on the substrate is located inside the orthographic projection of the corresponding second via on the substrate. That is, the inner wall of the second via and the inner wall of the third via are at a certain distance in a direction parallel to the substrate, and at least a portion of the first insulating layer is exposed through the second via. Therefore, this application does not use the second insulating layer as a mask for etching the first insulating layer, which avoids direct reaction between the dry etching gas and the second insulating layer, thereby preventing reaction products from remaining on the surface of the conductive pads. This ensures effective electrical connection between the conductive pads and structures such as the light-emitting chip, thereby improving the reliability of the display substrate.

[0160] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0161] In this application, the term "at least one of A and B" merely describes the relationship between related objects, indicating that three relationships can exist. For example, "at least one of A and B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. Similarly, "at least one of A, B, and C" indicates that seven relationships can exist, representing: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, A and C existing simultaneously, C and B existing simultaneously, and A, B, and C existing simultaneously. Likewise, "at least one of A, B, C, and D" indicates that fifteen relationships can exist, representing: A existing alone, B existing alone, C existing alone, D existing alone, A and B existing simultaneously, A and C existing simultaneously, A and D existing simultaneously, C and B existing simultaneously, D and B existing simultaneously, C and D existing simultaneously, A, B, and C existing simultaneously, A, B, and D existing simultaneously, A, C, and D existing simultaneously, and A, B, C, and D existing simultaneously.

[0162] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0163] In this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" means two or more, unless otherwise expressly defined.

[0164] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A drive backplane, characterized by, The drive backplate includes: Base; A first metal driving layer located on one side of the substrate, the first metal driving layer having conductive pads; A light-absorbing layer is located on the side of the first metal driving layer away from the substrate. The orthographic projection of the light-absorbing layer on the substrate overlaps with the orthographic projection of the first metal driving layer on the substrate. The light-absorbing layer has a first via corresponding to the conductive pad. The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the conductive pad on the substrate. A first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first metal driving layer and the light absorbing layer, and the second insulating layer is located on the side of the light absorbing layer opposite to the first metal driving layer, and the second insulating layer has a second via corresponding to the first via, and at least a portion of the second via is located inside the first via. The first insulating layer has a third via corresponding to the second via. The area of ​​the orthographic projection of the third via on the substrate is smaller than the area of ​​the orthographic projection of the corresponding second via on the substrate, and the orthographic projection of the third via on the substrate is located inside the orthographic projection of the corresponding second via on the substrate.

2. The drive backplane of claim 1, wherein, The orthographic projection of the second via on the substrate lies within the orthographic projection of the corresponding first via on the substrate.

3. The drive backplane of claim 2, wherein, The second insulating layer covers the side of the light-absorbing layer away from the substrate and encloses the inner wall of the first via.

4. The drive backplane of claim 1, wherein, The second insulating layer is in contact with the portion of the first insulating layer near the first via inside the first via; the first insulating layer has a first annular region, which is a region of the first insulating layer that protrudes relative to the second insulating layer and is close to the second via, and the first annular region is distributed around the third via.

5. The drive backplane of claim 1, wherein, The second insulating layer is in contact with the portion of the first insulating layer near the first via inside the first via; the first insulating layer has a second annular region, which is the area where the first insulating layer and the second insulating layer are in contact.

6. The drive backplane of any of claims 1-5, wherein, The surfaces of the conductive pads facing away from the substrate are all smooth surfaces, and / or, The surface of the second insulating layer facing away from the substrate and the inner wall of the second via are both smooth surfaces.

7. The drive backplane of claim 6, wherein, The angle between the inner wall of the second via and the substrate is an acute angle.

8. The drive backplane of claim 7, wherein, The angle between the inner wall of the second via and the substrate ranges from 30 degrees to 60 degrees.

9. The drive backplane of any of claims 1-5, 7-8, wherein, The drive backplate further includes a reflective layer located between the first metal drive layer and the light-absorbing layer; the reflective layer has a fourth via corresponding to the first via, and the area of ​​the orthographic projection of the fourth via on the substrate is less than or equal to the area of ​​the orthographic projection of the corresponding first via on the substrate.

10. The drive backplane of claim 9, wherein, The reflective layer is located between the light-absorbing layer and the first insulating layer, and the orthographic projection of the fourth via on the substrate covers the orthographic projection of the third via on the substrate; Alternatively, the reflective layer is located between the first insulating layer and the first metal driving layer, and the orthogonal projection of the third via on the substrate covers the orthogonal projection of the fourth via on the substrate.

11. The drive backplane according to claim 9, characterized in that, The reflective layer is made of at least one of the following materials: amorphous silicon, low-temperature polycrystalline silicon, and white ink.

12. The drive backplane according to claim 9, characterized in that, The edge region of the side of the substrate facing away from the first metal driving layer includes a bonding area, and the driving backplate also includes a plurality of signal leads located in the bonding area, at least a portion of the plurality of signal leads being electrically connected to the conductive pads; The area between two adjacent signal leads is a gap region, and the orthographic projection of the gap region on the substrate overlaps with the orthographic projection of the reflective layer on the substrate.

13. The drive backplate according to any one of claims 1-5, 7-8, 10-12, characterized in that, The drive backplane further includes: a second metal drive layer and a third insulating layer; the second metal drive layer is located on the side of the first metal drive layer near the substrate, and the third insulating layer is located between the first metal drive layer and the second metal drive layer; The first metal driving layer further includes a first driving signal line, and the second metal driving layer includes a second driving signal line. The extension direction of the first driving signal line intersects with the extension direction of the second driving signal line. There are multiple conductive pads, at least some of which are electrically connected to the second driving signal line, and at least some of which are electrically connected to the first driving signal line.

14. A display substrate, characterized in that, include: A driving backplane and a light-emitting chip electrically connected to the conductive pads of the driving backplane, wherein the driving backplane is the driving backplane according to any one of claims 1 to 13.

15. The display substrate according to claim 14, characterized in that, The number of light-emitting chips is multiple, and the display substrate further includes an auxiliary light-absorbing layer located on the side of the light-emitting chips away from the substrate; the auxiliary light-absorbing layer is a continuous film layer covering the multiple light-emitting chips; the transmittance of the auxiliary light-absorbing layer to the light emitted by the light-emitting chips is greater than or equal to 50%.

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