Dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding and cochlear implant body

Abstract

This invention provides a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding and a cochlear implant. By designing a detector and filter circuit to first rectify and filter the radio frequency signal and extract the envelope voltage of the radio frequency signal, a voltage divider circuit divides the voltage to obtain the threshold voltage. Finally, a comparator is used to determine the magnitude of the radio frequency signal amplitude and the threshold voltage and output the corresponding clock signal and data signal. This allows the clock threshold voltage and data threshold voltage to adaptively adjust with the amplitude change of the radio frequency signal to adapt to the amplitude fluctuation of the radio frequency signal, thereby ensuring normal decoding and overcoming the "threshold dead zone" problem of fixed threshold when the radio frequency signal fluctuates, thus improving the speech recognition rate.

Description

Technical Field

[0001] This utility model relates to the field of biomedical electronic technology, and in particular to a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding and a cochlear implant. Background Technology

[0002] Cochlear implants, as implantable hearing restoration devices, are primarily used to reconstruct hearing function in patients with severe or profound sensorineural hearing loss. The system consists of two parts: an external sound processor and an implant. The sound processor transmits energy and stimulation parameters (such as time-domain, frequency-domain, and electrode position information) to the implant via radio frequency (RF) signals. The implant then needs to precisely demodulate the RF signals to generate neural electrical stimulation signals; this process is the core of speech recognition.

[0003] Current cochlear implants generally use a fixed threshold demodulation scheme:

[0004] Clock (CLK) signal extraction: When the amplitude of the RF signal is higher than the preset fixed CLK threshold level, the CLK signal is set to high level (logic "1"), otherwise it is set to low level (logic "0").

[0005] Data signal extraction: When the RF signal amplitude is higher than the fixed Data threshold level, the Data signal is set to "1", otherwise it is set to "0";

[0006] Data demodulation: The final demodulated data is determined by the timing relationship between the CLK signal and the Data signal (such as rising edge / falling edge synchronization).

[0007] like Figure 1 As shown, this demodulation scheme can achieve normal decoding when the RF signal is stable. However, when the patient's head moves or is subjected to electromagnetic interference, the RF signal amplitude will fluctuate, such as... Figure 2 As shown, this leads to the following chain of failures:

[0008] CLK signal missing: When the amplitude of the RF signal is lower than the CLK threshold level, the CLK signal remains "0", which disrupts clock synchronization;

[0009] Data signal missing: When the RF signal amplitude is lower than the Data threshold level, the Data signal cannot be correctly identified;

[0010] Decoding error: Missing signals cause data bit loss or demodulation errors, directly reducing speech recognition rate.

[0011] The root cause is that the fixed threshold cannot adapt to the dynamic fluctuations of the RF signal. In particular, when the instantaneous amplitude of the signal falls into the "threshold dead zone" (i.e., between the CLK threshold level and the Data threshold level), the system cannot compensate autonomously, which ultimately affects the quality of auditory reconstruction. Utility Model Content

[0012] The purpose of this invention is to provide a dynamic threshold adaptive adjustment circuit and a cochlear implant for decoding cochlear signals, so as to solve the problem that existing cochlear implants have fixed thresholds that cannot adapt to the dynamic fluctuations of RF signals, resulting in decoding errors.

[0013] To achieve the above objectives, this invention provides a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding, comprising:

[0014] The clock signal extraction circuit includes a first detection and filtering circuit, a first voltage divider circuit, and a first comparator. The first detection and filtering circuit is used to filter the radio frequency signal and obtain the first envelope voltage of the radio frequency signal. The first voltage divider circuit is used to divide the first envelope voltage and output a clock threshold voltage to the inverting input terminal of the first comparator. The non-inverting input terminal of the first comparator is connected to the radio frequency signal. The output terminal of the first comparator is used to output a clock signal.

[0015] The data signal extraction circuit includes a second detection and filtering circuit, a second voltage divider circuit, and a second comparator. The second detection and filtering circuit is used to filter the radio frequency signal and obtain the second envelope voltage of the radio frequency signal. The second voltage divider circuit is used to divide the second envelope voltage and output a data threshold voltage to the inverting input terminal of the second comparator. The non-inverting input terminal of the second comparator is connected to the radio frequency signal, and the output terminal of the second comparator is used to output a data signal.

[0016] Optionally, the first detection and filtering circuit includes a first diode, a first resistor, and a first capacitor connected in sequence, with the input terminal of the first diode connected to the radio frequency signal and the output terminal of the first capacitor grounded.

[0017] Optionally, the first voltage divider circuit includes a second resistor and a third resistor connected in series, the second resistor and the third resistor being connected in parallel across the first capacitor, and the inverting input of the first comparator being connected between the second resistor and the third resistor.

[0018] Optionally, the second detection and filtering circuit includes a second diode, a fourth resistor, and a second capacitor connected in sequence. The input terminal of the second diode is connected to the radio frequency signal, and the output terminal of the second capacitor is grounded.

[0019] Optionally, the second voltage divider circuit includes a fifth resistor and a sixth resistor connected in series, the fifth resistor and the sixth resistor are connected in parallel across the two ends of the second capacitor, and the inverting input of the second comparator is connected between the fifth resistor and the sixth resistor.

[0020] Optionally, the time constants of the first detection and filtering circuit and the second detection and filtering circuit are different.

[0021] Optionally, the time constant of the first detection and filtering circuit is greater than the time constant of the second detection and filtering circuit.

[0022] Optionally, the clock threshold voltage is less than the data threshold voltage.

[0023] Based on this, the present invention also provides a cochlear implant with a built-in dynamic threshold adaptive adjustment circuit based on the cochlear implant signal decoding as described above.

[0024] This invention provides a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding and a cochlear implant. By designing a detector and filter circuit to first rectify and filter the radio frequency signal and extract the envelope voltage of the radio frequency signal, a voltage divider circuit divides the voltage to obtain the threshold voltage. Finally, a comparator is used to determine the magnitude of the radio frequency signal amplitude and the threshold voltage and output the corresponding clock signal and data signal. This allows the clock threshold voltage and data threshold voltage to adaptively adjust with the amplitude change of the radio frequency signal to adapt to the amplitude fluctuation of the radio frequency signal, thereby ensuring normal decoding and overcoming the "threshold dead zone" problem of fixed threshold when the radio frequency signal fluctuates, thus improving the speech recognition rate. Attached Figure Description

[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

[0026] Figure 1 This is a schematic diagram of normal demodulation of radio frequency signals in the prior art;

[0027] Figure 2 This is a schematic diagram of a radio frequency signal demodulation error in the prior art.

[0028] Figure 3 A circuit diagram of a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding provided in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of signal repair provided in an embodiment of the present invention.

[0030] in:

[0031] U1 - First comparator; U2 - Second comparator; D1 - First diode; D2 - Second diode; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; C1 - First capacitor; C2 - Second capacitor. Detailed Implementation

[0032] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used in this invention, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used in this invention, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used in this invention, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0034] Please refer to Figure 3 This embodiment provides a dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding, including:

[0035] The clock signal extraction circuit includes a first detection and filtering circuit, a first voltage divider circuit, and a first comparator U1. The first detection and filtering circuit is used to filter the radio frequency (RF) signal and obtain the first envelope voltage of the RF signal. The first voltage divider circuit is used to divide the first envelope voltage and output a clock (CLK) threshold voltage to the inverting input terminal of the first comparator U1. The non-inverting input terminal of the first comparator U1 is connected to the RF signal. The output terminal of the first comparator U1 is used to output a clock (CLK) signal.

[0036] The data signal extraction circuit includes a second detection and filtering circuit, a second voltage divider circuit, and a second comparator U2. The second detection and filtering circuit is used to filter the radio frequency signal and obtain the second envelope voltage of the radio frequency signal. The second voltage divider circuit is used to divide the second envelope voltage and output a data threshold voltage to the inverting input terminal of the second comparator U2. The non-inverting input terminal of the second comparator U2 is connected to the radio frequency signal. The output terminal of the second comparator U2 is used to output a data signal.

[0037] By designing a detection and filtering circuit, the radio frequency (RF) signal is first rectified and filtered to extract the envelope voltage of the RF signal. Then, a voltage divider circuit divides the voltage to obtain the threshold voltage. Finally, a comparator is used to determine the magnitude of the RF signal amplitude and the threshold voltage, and outputs the corresponding clock and data signals. This allows the clock and data threshold voltages to adaptively adjust with the amplitude changes of the RF signal to adapt to amplitude fluctuations, thereby ensuring normal decoding and overcoming the "threshold dead zone" problem of fixed thresholds when the RF signal fluctuates, thus improving the speech recognition rate.

[0038] Specifically, in this embodiment, the first detection and filtering circuit includes a first diode D1, a first resistor R1, and a first capacitor C1 connected in sequence. The input terminal of the first diode D1 is connected to the radio frequency signal, and the output terminal of the first capacitor C1 is grounded. The function of the first diode D1 is to intercept the positive half-cycle of the radio frequency signal, converting the high-frequency sinusoidal radio frequency signal into a unidirectional pulsating DC. The first resistor R1 and the first capacitor C1 form an RC filter to filter out the high-frequency carrier in the radio frequency signal, while retaining the slow response of the capacitor voltage to amplitude changes. Its time constant determines the ability to track signal amplitude changes. The voltage across the first capacitor C1 is the envelope voltage, which is the amplitude change curve extracted from the radio frequency signal, reflecting the instantaneous amplitude of the radio frequency signal.

[0039] In this embodiment, the first voltage divider circuit includes a second resistor R2 and a third resistor R3 connected in series. The second resistor R2 and the third resistor R3 are connected in parallel across the first capacitor C1. The inverting input of the first comparator U1 is connected between the second resistor R2 and the third resistor R3. Since directly taking the envelope voltage as the threshold voltage may be too high or unstable, a voltage divider circuit is designed to divide it.

[0040] In this embodiment, the data signal extraction circuit and the clock signal extraction circuit are dual-path symmetrical structures. Similarly, the second detection and filtering circuit includes a second diode D2, a fourth resistor R4 and a second capacitor C2 connected in sequence. The input terminal of the second diode D2 is connected to the radio frequency signal, the output terminal of the second capacitor C2 is grounded, and the voltage across the second capacitor C2 is the envelope voltage.

[0041] The second voltage divider circuit includes a fifth resistor R5 and a sixth resistor R6 connected in series. The fifth resistor R5 and the sixth resistor R6 are connected in parallel across the two ends of the second capacitor C2. The inverting input of the second comparator U2 is connected between the fifth resistor R5 and the sixth resistor R6.

[0042] In this embodiment, the time constants of the first detection and filtering circuit and the second detection and filtering circuit are different. The time constant determines the charging and discharging speed of the capacitor, directly affecting the settling time of the envelope voltage (response speed from zero to steady state), smoothness (suppression capability for noise), and tracking capability for RF amplitude changes. The time constant of the first detection and filtering circuit is denoted as τ1, τ1 = R1×C1, and the time constant of the second detection and filtering circuit is denoted as τ2, τ2 = R4×C2, and τ1 ≠ τ2.

[0043] In this circuit, the time constant τ1 of the first detection and filtering circuit is determined by the first resistor R1 and the first capacitor C1, while the time constant τ2 of the second detection and filtering circuit is determined by the fourth resistor R4 and the second capacitor C2. By changing the values ​​of R1 / C1 (τ1) or R4 / C2 (τ2), the tracking speed of the clock threshold voltage and data threshold voltage to amplitude changes can be independently controlled. Generally, a larger time constant results in slower charging and discharging, a smoother envelope, and a delayed response; a smaller time constant results in faster charging and discharging, a sharper envelope, and a rapid response. Therefore, depending on the requirements, the two detection and filtering circuits can use different charging loop time constants to adjust the phase of the clock threshold voltage and data threshold voltage as the RF signal amplitude changes, thereby adapting to the amplitude fluctuations of the RF signal.

[0044] Preferably, the time constant of the first detection and filtering circuit is greater than the time constant of the second detection and filtering circuit. The larger time constant of the first detection and filtering circuit prevents the radio frequency signal from momentarily dropping below the threshold, thereby preventing clock signal loss (ensuring clock synchronization). The smaller time constant of the second detection and filtering circuit lowers the threshold to accommodate the decline in radio frequency signal, thereby preventing misjudgment of data signals (avoiding code errors).

[0045] In this embodiment, the first comparator U1 is used to compare the clock threshold voltage with the amplitude of the RF signal and output a corresponding clock signal. The second comparator U2 is used to compare the data threshold voltage with the amplitude of the RF signal and output a corresponding data signal, and the demodulated data is obtained after processing.

[0046] In this embodiment, when the amplitude of the RF signal is greater than the clock threshold voltage, a clock high level is output; otherwise, a clock low level is output.

[0047] On the premise of the clock high level, when the amplitude of the RF signal is greater than the data threshold voltage, a data high level is output and there is demodulated data; otherwise, a data low level is output and there is no demodulated data, as Figure 4 shown.

[0048] Preferably, the clock threshold voltage is less than the data threshold voltage. The clock signal is a timing reference. Once lost (i.e., RF amplitude < CLK threshold), the demodulation of the entire data frame fails, and the consequence is more serious than the error of the Data signal. Therefore, the clock threshold voltage is designed to be smaller so that the clock signal is not easily lost.

[0049] Based on this, the present invention also provides a cochlear implant, which is internally provided with a dynamic threshold adaptive adjustment circuit for decoding cochlear signals as described above.

[0050] Since the cochlear implant provided by the present invention and the dynamic threshold adaptive adjustment circuit for decoding cochlear signals described above belong to the same technical concept, the cochlear implant provided by the present invention has all the advantages of the dynamic threshold adaptive adjustment circuit for decoding cochlear signals described above. Therefore, the beneficial effects of the cochlear implant provided by the present invention will not be elaborated one by one here.

[0051] In summary, the embodiment of the present invention provides a dynamic threshold adaptive adjustment circuit for decoding cochlear signals and a cochlear implant. By designing a detection and filtering circuit to first rectify and filter the RF signal, extract the envelope voltage of the RF signal, then divide the voltage by a voltage dividing circuit as the threshold voltage, and finally use a comparator to determine the magnitude of the RF signal and the threshold voltage and output corresponding clock signals and data signals, the clock threshold voltage and the data threshold voltage can be adaptively adjusted according to the amplitude change of the RF signal to adapt to the amplitude fluctuation of the RF signal, so as to ensure normal decoding, overcome the "threshold dead zone" problem of the fixed threshold when the RF signal fluctuates, and improve the speech recognition rate.

[0052] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.

Claims

1. A dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding, characterized by, include: The clock signal extraction circuit includes a first detection and filtering circuit, a first voltage divider circuit, and a first comparator. The first detection and filtering circuit is used to filter the radio frequency signal and obtain the first envelope voltage of the radio frequency signal. The first voltage divider circuit is used to divide the first envelope voltage and output a clock threshold voltage to the inverting input terminal of the first comparator. The non-inverting input terminal of the first comparator is connected to the radio frequency signal. The output terminal of the first comparator is used to output a clock signal. The data signal extraction circuit includes a second detection and filtering circuit, a second voltage divider circuit, and a second comparator. The second detection and filtering circuit is used to filter the radio frequency signal and obtain the second envelope voltage of the radio frequency signal. The second voltage divider circuit is used to divide the second envelope voltage and output a data threshold voltage to the inverting input terminal of the second comparator. The non-inverting input terminal of the second comparator is connected to the radio frequency signal, and the output terminal of the second comparator is used to output a data signal.

2. A dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding as defined in claim 1, wherein, The first detection and filtering circuit includes a first diode, a first resistor, and a first capacitor connected in sequence. The input terminal of the first diode is connected to the radio frequency signal, and the output terminal of the first capacitor is grounded.

3. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 2, wherein, The first voltage divider circuit includes a second resistor and a third resistor connected in series. The second resistor and the third resistor are connected in parallel across the first capacitor. The inverting input of the first comparator is connected between the second resistor and the third resistor.

4. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 1, wherein, The second detection and filtering circuit includes a second diode, a fourth resistor, and a second capacitor connected in sequence. The input terminal of the second diode is connected to the radio frequency signal, and the output terminal of the second capacitor is grounded.

5. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 4, wherein, The second voltage divider circuit includes a fifth resistor and a sixth resistor connected in series. The fifth resistor and the sixth resistor are connected in parallel across the two ends of the second capacitor. The inverting input of the second comparator is connected between the fifth resistor and the sixth resistor.

6. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 1, wherein, The time constants of the first detection and filtering circuit and the second detection and filtering circuit are different.

7. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 6, wherein, The time constant of the first detection and filtering circuit is greater than the time constant of the second detection and filtering circuit.

8. The dynamic threshold adaptive adjustment circuit for cochlear implant signal decoding of claim 1, wherein, The clock threshold voltage is less than the data threshold voltage.

9. A cochlear implant system comprising: It incorporates a dynamic threshold adaptive adjustment circuit for decoding cochlear implant signals according to any one of claims 1-8.

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