Test board, test carrier board and aging test equipment

Abstract

This application discloses a test board, a test carrier board, and an aging test device. The test board includes: a control circuit; a memory chip limiting plate having N memory chip limiting slots for loading the N memory chips, wherein the N memory chips are electrically connected to the control circuit, and N is a positive integer greater than 1; and a current plate electrically connected to the control circuit and the N memory chips; wherein the control circuit controls the current plate to simultaneously output test electrical signals to the N memory chips; the N memory chips operate simultaneously under the test electrical signals to be subjected to aging tests simultaneously. This application enables aging tests on individual memory chips.

Description

Technical Field

[0001] The embodiments disclosed in this application relate to the field of storage device technology, and more specifically, to a test board, a test carrier board, and an aging test device. Background Technology

[0002] Currently, with the rapid development of DRAM (Dynamic Random Access Memory) technology, DRAM chips have become the mainstream in the market due to their high density and high performance. However, ARM-based controllers typically only support testing of memory modules in bulk and are not compatible with testing individual memory chips. Summary of the Invention

[0003] According to embodiments of this application, this application proposes a test board, a test carrier board, and an aging test device to solve the above-mentioned problems.

[0004] The first aspect of this application discloses a test board, comprising: a control circuit; a memory chip limiting plate having N memory chip limiting slots for loading the N memory chips, wherein the N memory chips are electrically connected to the control circuit, and N is a positive integer greater than 1; and a current plate electrically connected to the control circuit and the N memory chips; wherein the control circuit controls the current plate to simultaneously output test electrical signals to the N memory chips; and the N memory chips operate simultaneously under the test electrical signals to be subjected to aging tests simultaneously.

[0005] In some embodiments, the N memory chips include two first-type memory chips, and the control circuit integrates a first memory channel and a second memory channel; through either the first memory channel or the second memory channel, the two first-type memory chips operate simultaneously under the test electrical signal to be subjected to the aging test simultaneously.

[0006] In some embodiments, the N memory chips include two second-type memory chips, the bit width of which is different from that of the first-type memory chips; through the first memory channel and the second memory channel, the two second-type memory chips operate simultaneously under the test electrical signal so as to be subjected to the aging test simultaneously.

[0007] In some embodiments, the control circuit, the memory chip limiting plate, and the current plate are disposed on the first side of the test board; the BTB connector is disposed on the second side of the test board, and the BTB connector is used to implement a USB interface and a power supply interface.

[0008] In some embodiments, the test board further includes at least three temperature sensors disposed around the control circuit, the memory chip limiting plate, and the current plate, respectively.

[0009] In some embodiments, the memory chip limiting plate and the current plate are spaced apart by a preset distance.

[0010] The second aspect of this application discloses a test carrier plate, comprising: a BIB carrier plate; M test plates as described in the first aspect; wherein the M test plates are arranged on the BIB carrier plate in a preset manner, and M is a positive integer greater than 1.

[0011] In some embodiments, the test carrier board further includes at least one of a communication board, a near-field communication board, and a hub circuit board, which is electrically connected to an external test host.

[0012] In some embodiments, the M test boards are arranged in a row of X adjacent boards and in a column of Y adjacent boards to form a test board array, wherein X and Y are both positive integers greater than 1; at least one of the communication board, the near-field communication board, and the hub circuit board is disposed on one side of the test board array.

[0013] The third aspect of this application discloses an aging test device, including the test plate described in the first aspect or the test carrier plate described in the second aspect.

[0014] The beneficial effects of this application are as follows: The test board includes a control circuit, a memory chip limiting plate, and a current plate. The memory chip limiting plate has N memory chip limiting slots for loading N memory chips. The control circuit is electrically connected to the current plate, and the N memory chips are electrically connected to the control circuit and the current plate respectively. The control circuit controls the current plate to simultaneously output test electrical signals to the N memory chips. The N memory chips work simultaneously under the test electrical signals, so that the N memory chips can be subjected to aging tests at the same time, that is, aging tests can be performed on individual chips. Attached Figure Description

[0015] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings:

[0016] Figure 1 This is a schematic diagram of the structure of the test board according to an embodiment of this application;

[0017] Figure 2 This is a test schematic diagram of the first type of memory chip according to an embodiment of this application;

[0018] Figure 3 This is a test schematic diagram of the second type of memory chip according to an embodiment of this application;

[0019] Figure 4This is a schematic diagram of the structure of a test board according to an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the first side of a test board according to an embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the second side of a test board according to an embodiment of this application;

[0022] Figure 7 This is a schematic diagram of the structure of the test support plate according to an embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the structure of a test support plate according to an embodiment of this application;

[0024] Figure 9 This is a schematic diagram of the structure of a test support plate according to another embodiment of this application;

[0025] Figure 10 This is a schematic diagram of the topology of a test system according to an embodiment of this application;

[0026] Figure 11 This is a schematic diagram of the aging test equipment according to an embodiment of this application. Detailed Implementation

[0027] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0029] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Please see Figure 1 , Figure 1 This is a schematic diagram of the test board according to an embodiment of this application. The test board 100 includes a control circuit 110, a memory chip limiting plate 120, and a current plate 130. Figure 1 As shown, the memory chip limiting plate 120 has N memory chip limiting slots 1200 for loading N memory chips P. The N memory chips P are electrically connected to the control circuit 110, where N is a positive integer greater than 1. The current plate 130 is electrically connected to the control circuit 110 and the N memory chips P. For example, if the memory chip limiting plate 120 is a dual in-line memory module (Socket DIMM), it can be used to load two memory chips simultaneously, i.e., N = 2.

[0031] In some embodiments, the control circuit 110 can acquire test parameters to control the current board 130 to simultaneously output test electrical signals to N memory chips P. Further, the N memory chips P operate simultaneously under the test electrical signals to simultaneously perform aging tests on the N memory chips P. The test parameters include temperature, humidity, voltage, and current, and the test electrical signals include voltage signals, current signals, timing signals, and clock signals. For example, if the test parameters include applying a rated or over-rated voltage, the control circuit 110 controls the current board 130 to simultaneously output corresponding voltage signals to the N memory chips P, and controls the N memory chips P to operate under these voltage signals, thereby acquiring aging test data for the N memory chips P.

[0032] In this embodiment, the test board 100 includes a control circuit 110, a memory chip limiting plate 120, and a current plate 130. The memory chip limiting plate 120 has N memory chip limiting slots 1200 for loading N memory chips P. The control circuit 110 is electrically connected to the current plate 130, and the N memory chips P are electrically connected to both the control circuit 110 and the current plate 130. The control circuit 110 controls the current plate 130 to simultaneously output test electrical signals to the N memory chips P. The N memory chips P operate simultaneously under the test electrical signals, thus undergoing aging tests on all N memory chips P at the same time, achieving aging tests on individual chips. Furthermore, by testing and screening individual chips, the yield rate of chips can be improved, and the maintenance cost of later memory modules can be reduced.

[0033] In some embodiments, such as Figure 2 As shown, Figure 2This is a test schematic diagram of a first type of memory chip according to an embodiment of this application. The N memory chips include two first type memory chips P1. The control circuit 110 integrates a first memory channel CH0 and a second memory channel CH1. Through either the first memory channel CH0 or the second memory channel CH1, the two first type memory chips P1 operate simultaneously under a test electrical signal to undergo aging tests concurrently.

[0034] The N memory chips include two first-type memory chips P1, i.e., N=2. The first-type memory chips P1 can be 8-bit memory chips, such as ×8 DRAM chips. That is, on the test board 100, the memory chip limiting board 120 has two memory chip limiting slots 1200, which can be used to load two ×8 DRAM chips. The control circuit 110 integrates a first memory channel CH0 and a second memory channel CH1. In some examples, the data bit width of the first memory channel CH0 and the second memory channel CH1 is 16 bits. Each memory channel is an independent data transmission path between the memory controller and the physical memory (e.g., DRAM), and each memory channel can contain independent address lines.

[0035] During the aging test of the first type of memory chip P1, the control circuit 110 can control either the first memory channel CH0 or the second memory channel CH1 to be in a closed state, such as... Figure 2 As shown, the second memory channel CH1 is controlled to be in the off state, and data is transmitted to two first-type memory chips P1 through the first memory channel CH0. For example, data is transmitted to one first-type memory chip P1 through CH0<7:0> and data is transmitted to the other first-type memory chip P1 through CH0<15:8>. Furthermore, the two first-type memory chips P1 operate simultaneously under a test electrical signal to perform an aging test on the first-type memory chips P1, meaning the test board 100 can directly support the testing of ×8 DRAM chips. In other examples, the first memory channel CH0 can also be controlled to be in the off state, and data is transmitted to two first-type memory chips P1 through the second memory channel CH1. For example, data is transmitted to one first-type memory chip P1 through CH1<7:0> and data is transmitted to the other first-type memory chip P1 through CH1<15:8>.

[0036] In this embodiment, two first-type memory chips P1 operate simultaneously under a test electrical signal through either the first memory channel CH0 or the second memory channel CH1 to perform aging tests on the first-type memory chips P1. This enables aging tests on individual ×8 DRAM chips. Furthermore, by testing and screening individual chips, the yield rate of chips can be improved and the maintenance cost of memory modules can be reduced.

[0037] In some embodiments, such as Figure 3 As shown, Figure 3 This is a test schematic diagram of the second type of memory chip according to an embodiment of this application. The N memory chips include two second type memory chips P2, whose bit width differs from that of the first type memory chip P1. The two second type memory chips operate simultaneously under a test electrical signal via a first memory channel CH0 and a second memory channel CH1, so that they are simultaneously subjected to aging tests.

[0038] The N memory chips include two first-type memory chips P2, i.e., N=2. The second-type memory chips P2 can be 16-bit memory chips, such as ×16 DRAM chips. That is, on the test board 100, the memory chip limiting board 120 has two memory chip limiting slots 1200, which can be used to load two ×16 DRAM chips. The control circuit 110 integrates a first memory channel CH0 and a second memory channel CH1. In some examples, the data bit width of the first memory channel CH0 and the second memory channel CH1 is 16 bits. Each memory channel is an independent data transmission path between the memory controller and the physical memory (e.g., DRAM), and each memory channel can contain independent address lines.

[0039] During the aging test of the second type of memory chip P2, the control circuit 110 can control both the first memory channel CH0 and the second memory channel CH1-0 to be in the conducting state, such as... Figure 3 As shown, data is transmitted to two second-type memory chips P2 via the first memory channel CH0 and the second memory channel CH1. For example, data is transmitted to one second-type memory chip P2 via CH0<15:0> and to the other second-type memory chip P2 via CH1<15:0>. Furthermore, the two second-type memory chips P2 operate simultaneously under a test electrical signal to perform an aging test on the second-type memory chips P2. That is, the test board 100 can directly support the testing of ×16 DRAM chips.

[0040] In this embodiment, two second-type memory chips work simultaneously under a test electrical signal through the first memory channel CH0 and the second memory channel CH1 to perform aging tests on the second-type memory chip P2. This allows for aging tests on individual ×16 DRAM chips. Furthermore, by testing and screening individual chips, the yield rate of chips can be improved and the maintenance cost of memory modules can be reduced.

[0041] In some embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of a test board according to an embodiment of this application, as shown below. Figure 4As shown in (a), the control circuit 110, the memory chip limiting plate 120, and the current plate 130 are disposed on the first surface 1001 of the test board 100. The first surface 1001 of the test board 100 can be the front surface (Top) of the test board 100, for example, the control circuit 110, the memory chip limiting plate 120, and the current plate 130 are integrated on the front surface of the test board 100; Figure 4 As shown in (b), the BTB (Board-to-Board Connector) 140 is disposed on the second side 1002 of the test board 100. The BTB connector 140 is used to implement the USB interface and the power supply interface. The second side 1002 of the test board 100 can be the bottom of the test board 100. For example, the BTB connector 140 adapted to the BIB carrier board is integrated on the bottom of the test board 100 to bring out the USB interface and the power supply interface.

[0042] In some embodiments, you may continue to refer to Figure 4 The test board 100 also includes at least three temperature sensors 150, which are respectively disposed around the control circuit 110, the memory chip limiting plate 120 and the current plate 130. That is, the temperature sensors 150 are also disposed on the first surface 1001 of the test board 100 for monitoring temperature. The specific position of the temperature sensors 150 can be adjusted according to the actual layout.

[0043] In some embodiments, the memory chip limiting plate 120 and the current plate 130 are spaced apart by a preset distance d to allow space for heat insulation. In some examples, the preset distance d can be 0.5cm-3.0cm, such as 1.0cm, 1.5cm, 2.0cm, etc.

[0044] In some examples, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the first side of a test board according to an embodiment of this application. A control circuit 110, a memory chip limiting plate 120, a current plate 130, and temperature sensors 150 can be disposed on the first side 1001 of the test board 100. The memory chip limiting plate 120 and the current plate 130 are disposed at a preset distance apart. The three temperature sensors 150 are respectively located close to the edge of the board, and the control circuit 110 and memory chip limiting plate 120 are also present. Figure 6 As shown, Figure 6 This is a schematic diagram of the second side of a test board according to an embodiment of this application. The BTB connector 140 can be disposed on the second side 1002 of the test board 100. The BTB connector 140 can be used to bring out USB interface and power supply interface, etc.

[0045] Please see Figure 7 , Figure 7This is a schematic diagram of the structure of the test carrier board according to an embodiment of this application. The test carrier board 700 includes a BIB (Burn-in Board) carrier board 710 and M test boards 100 as described above. Each test board 100 includes a circuit 110, a memory chip limiting plate 120, and a current plate 130. The memory chip limiting plate 120 has N memory chip limiting slots 1200 for loading N memory chips P, and the N memory chips P are electrically connected to the control circuit 110 and the current plate 130. In some examples, the memory chip limiting plate 120 is a dual in-line memory module, used to load two memory chips simultaneously, i.e., N=2. Accordingly, the test carrier board 700 may include M control circuits 110, M memory chip limiting plates 120, and M current plates 130, which can be used to simultaneously perform aging tests on 2M memory chips P. Furthermore, the M test boards 100 are arranged on the BIB carrier board 710 according to a preset arrangement, where M is a positive integer greater than 1.

[0046] In this embodiment, the test carrier board 700 includes a BIB carrier board 710 and M test boards 100. The M test boards 100 are arranged on the BIB carrier board 710 in a preset manner, where M is a positive integer greater than 1. This allows for simultaneous aging tests on multiple memory chips. Furthermore, by testing and screening individual chips, the yield rate of chips can be improved, and the maintenance cost of memory modules can be reduced in the later stages.

[0047] In some embodiments, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a test carrier board according to an embodiment of this application. The test carrier board 700 also includes at least one of a communication board 720, a hub circuit board 730, and a near field communication (NFC) board 740, which is electrically connected to an external test host. The communication board 720 may be a 3720 communication board.

[0048] In some examples, an external test host sends test signals / parameters, which are transmitted to M test boards 100 via communication board 720 and hub circuit board 730. On test board 100, control circuit 110 responds to the test signals and controls current board 130 to simultaneously output test electrical signals to N memory chips P, such as for voltage / current adjustment and heating control. This controls the N memory chips P to operate simultaneously under the test electrical signals, achieving simultaneous aging tests on the N memory chips P. In other examples, an external test host implements an adaptive test algorithm to dynamically adjust test parameters, adapting to the characteristics and requirements of different DRAM chips. Through host computer software control, the test board can automatically load programs, perform tests, and provide result feedback and output.

[0049] In this embodiment, the test carrier board 700 also includes at least one of a communication board 720, a hub circuit board 730, and a near-field communication board 740, which is electrically connected to an external test host. The external test host is used to implement customized test algorithms, dynamically adjust test parameters, and realize independent functional testing of individual DRAM chips. This provides an efficient and stable test solution for individual DRAM chips, making it convenient for memory module manufacturers to conduct initial screening tests on incoming chips.

[0050] In some embodiments, M test boards are arranged in a row of X adjacent boards and in a column of Y adjacent boards to form a test board array, where X and Y are both positive integers greater than 1; at least one of the communication board 720, the hub circuit board 730 and the near-field communication board 740 is disposed on one side of the test board array.

[0051] In some examples, M=20, X=4, Y=5, meaning 20 test boards can be arranged in rows of 4 adjacent to each other and columns of 5 adjacent to each other to form a test board array. In other examples, M=12, X=4, Y=3, meaning 12 test boards can be arranged in rows of 4 adjacent to each other and columns of 3 adjacent to each other to form a test board array. Correspondingly, at least one of the communication board 720, the hub circuit board 730, and the near-field communication board 740 is disposed on one side of the test board array; for example, the communication board 720 and the near-field communication board 740 can be uniformly disposed above the test board array.

[0052] Taking M=20, X=4, Y=5 as an example, Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of a test support plate according to another embodiment of this application. Figure 9 The carrier board shown includes 20 test boards, a communication board (3720 communication board), a BIB carrier board, an NFC board, a HUB board, etc. The 20 test boards are arranged in a row of 4 adjacent to each other and in a column of 5 adjacent to each other to form a test board array. The communication board and the near-field communication board are uniformly arranged above the test board array.

[0053] For ease of understanding, the test system of this application embodiment is illustrated with examples, such as... Figure 10 As shown, Figure 10 This is a topology diagram of a test system according to an embodiment of this application. Figure 10 The testing system includes a test board and a test carrier board. The control circuit can be a DM1268. The test board structure is adapted to the BIB carrier board, forming a 1-to-12 or 1-to-20 test carrier board, etc. The current board supports current measurement and voltage adjustment, and can also control the memory chip limit board (e.g., ...). Figure 10The high-temperature socket shown in the figure is heated; the test data can be uploaded to the test terminal through the communication board (e.g., a 3720 communication board); the test system can simultaneously heat two memory chips (e.g., high-temperature socket) through the control circuit. Figure 10 The DRAM1 and DRAM2 shown in the figure are subjected to aging tests, wherein DRAM1 and DRAM2 can be DDR3.

[0054] Please see Figure 11 , Figure 11 This is a schematic diagram of the aging test equipment according to an embodiment of this application, as shown below. Figure 11 As shown in (a), the aging test equipment 1100 may include a plurality of the above-described test plates 100, or, as... Figure 11 As shown in (b), the aging test equipment 1100 may include multiple test carrier boards 700 as described above. Each test carrier board 700 may include a BIB carrier board 710 and M test boards 100 arranged in a preset manner on the BIB carrier board 710. Each test board 100 includes a control circuit 110, a memory chip limiting plate 120, and a current plate 130. The memory chip limiting plate 120 has N memory chip limiting slots 1200 for loading N memory chips P, and the N memory chips P are electrically connected to the control circuit 110 and the current plate 130. In some examples, the memory chip limiting plate 120 is a dual in-line memory module, which can be used to load two memory chips simultaneously. In this case, the test carrier board 700 may include M control circuits 110, M memory chip limiting plates 120, and M current plates 130, which can be used to perform aging tests on 2M memory chips.

[0055] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0056] In the several embodiments provided in this application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the related device implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication disconnection shown or discussed may be indirect coupling or communication disconnection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0057] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.

Claims

1. A test board, characterized in that, include: Control circuit; A memory chip limiting plate has N memory chip limiting slots for loading the N memory chips, wherein the N memory chips are electrically connected to the control circuit, and N is a positive integer greater than 1; A current board is electrically connected to the control circuit and the N memory chips; The control circuit controls the current board to simultaneously output test electrical signals to the N memory chips; The N memory chips operate simultaneously under the test electrical signal to undergo aging tests concurrently.

2. The test board according to claim 1, characterized in that, The N memory chips include two first-type memory chips, and the control circuit integrates a first memory channel and a second memory channel; The two first-type memory chips operate simultaneously under the test electrical signal through either the first memory channel or the second memory channel, so as to be subjected to the aging test at the same time.

3. The test board according to claim 2, characterized in that, The N memory chips include two second-type memory chips, and the bit width of the second-type memory chips is different from that of the first-type memory chips. Through the first memory channel and the second memory channel, the two second-type memory chips operate simultaneously under the test electrical signal so as to be subjected to the aging test at the same time.

4. The test board according to claim 1, characterized in that, The control circuit, the memory chip limiting plate, and the current plate are disposed on the first side of the test board; The BTB connector is located on the second side of the test board and is used to implement the USB interface and the power supply interface.

5. The test board according to claim 4, characterized in that, The test board also includes at least three temperature sensors, which are respectively disposed around the control circuit, the memory chip limiting plate, and the current plate.

6. The test board according to claim 4, characterized in that, The memory chip limiting plate and the current plate are set at a preset distance apart.

7. A test support plate, characterized in that, include: BI B bearing plate; M test boards as described in any one of claims 1-6; The M test boards are arranged on the BIB carrier board in a preset manner, where M is a positive integer greater than 1.

8. The test support plate according to claim 7, characterized in that, The test carrier board also includes at least one of a communication board, a near-field communication board, and a hub circuit board, which is electrically connected to an external test host.

9. The test support plate according to claim 8, characterized in that, The M test boards are arranged in a row of X adjacent boards and in a column of Y adjacent boards to form a test board array, where X and Y are both positive integers greater than 1; At least one of the communication board, near-field communication board, and hub circuit board is disposed on one side of the test board array.

10. An aging test device, characterized in that, It includes the test board according to any one of claims 1-6 or the test carrier board according to any one of claims 7-9.

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