A single line voltage input relay recovery feedback circuit

Abstract

This application provides a single-line voltage input relay feedback circuit, including: an isolation chip U3, a relay U1, and a status feedback circuit; the first input terminal of the relay U1 is electrically connected to the CPU to receive control signals output by the CPU, and the second input terminal of the relay U1 is electrically connected to the first input power supply to receive a test voltage; the output terminal of the relay U1 is electrically connected to the input terminal of the status feedback circuit, so that when the relay U1 is closed, the first input power supply can output an electrical signal to the status feedback circuit through the relay U1; the output power supply terminal of the isolation chip U3 is short-circuited to the first input power supply; the status feedback circuit includes: a PMOS transistor Q2, the gate of the PMOS transistor Q2 is electrically connected to the output terminal of the relay U1, the source of the PMOS transistor Q2 is electrically connected to the output power supply terminal of the isolation chip U3, and the drain of the PMOS transistor Q2 is electrically connected to the input terminal of the CPU to output the operating state of the relay U1 to the CPU, and the isolation chip U3 is used as a reference for the status feedback circuit to determine the operating state of the relay.

Description

Technical Field

[0001] This utility model belongs to the field of relay status feedback technology, specifically, it relates to a relay feedback circuit with single-line voltage input. Background Technology

[0002] Relays are key components in electrical control, widely used in industrial automation, smart homes, and other fields. Ensuring the safe and reliable operation of a system is often achieved through relay status feedback. Current methods for relay status feedback include electrical parameter detection, Hall effect detection, optocoupler isolation detection, microcontroller sampling combined with algorithm optimization, wireless sensing and IoT technology, and current transformer detection. All of these methods rely on two-wire acquisition: one input power line and the other serving as a reference ground plane. When the power line passes through the relay and outputs an electrical signal, the output signal can be determined by referencing the power line's reference ground plane to determine whether the output signal is high or low. The relay status feedback circuit then determines the relay's operating state based on the high or low level of the output signal, thus completing the relay status feedback.

[0003] In practical applications, there is often only a single voltage input, that is, only one input power line without a reference ground plane. In this case, the electrical signal output by the relay through the input power has no reference point and cannot form a complete circuit. This causes the measured voltage at the relay output terminal to be in a floating state, making it impossible to determine the level of the output electrical signal. As a result, there is a problem that the relay status cannot be collected.

[0004] Therefore, this application provides a relay feedback circuit with a single-line voltage input, mainly for acquiring the relay status when there is only one input power line. Utility Model Content

[0005] The technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide a relay feedback circuit with single-line voltage input, including: isolation chip U3, relay U1, and status feedback circuit; The first input terminal of relay U1 is electrically connected to the CPU to receive the control signal output by the CPU. The second input terminal of relay U1 is electrically connected to the first input power supply to receive the test voltage. The output terminal of relay U1 is electrically connected to the input terminal of the status retrieval circuit so that when relay U1 is closed, the first input power supply can output an electrical signal to the status retrieval circuit through relay U1. The output power terminal of isolation chip U3 is shorted to the first input power supply. The status feedback circuit includes: a PMOS transistor Q2, the gate of which is electrically connected to the output terminal of relay U1, the source of which is electrically connected to the output power supply terminal of isolation chip U3, and the drain of which is electrically connected to the input terminal of the CPU to output the operating status of relay U1 to the CPU.

[0006] One possible implementation also includes control circuitry; The output terminal of the control circuit is electrically connected to the first input terminal of the relay U1. The input terminal of the control circuit is suitable for being electrically connected to the output terminal of the CPU. The CPU is suitable for outputting control signals to the relay U1 through the control circuit.

[0007] In one possible implementation, the control circuit also includes an NMOS transistor Q1; The gate of NMOS transistor Q1 is electrically connected to the output terminal of the CPU, the source of NMOS transistor Q1 is grounded, and the drain of NMOS transistor Q1 is electrically connected to the first input terminal of relay U1.

[0008] In one possible implementation, a second input power source is also included; The second input power supply is electrically connected to the third input terminal of relay U1 and is suitable for supplying power to relay U1.

[0009] In one possible implementation, the drain of PMOS transistor Q2 is also suitable for electrical connection to the ground terminal of isolation chip U3.

[0010] In one possible implementation, an optocoupler U2 is also included; The drain of PMOS transistor Q2 is electrically connected to the ground terminal of isolation chip U3 and the input terminal of CPU through optocoupler U2.

[0011] In one possible implementation, a transient voltage suppressor D1 is also included, which is suitable for protecting the relay U1; The transient voltage suppressor D1 is electrically connected to the second input terminal and the output terminal of relay U1, respectively.

[0012] Beneficial effects: This application introduces an isolation chip U3 into the status retrieval circuit of a relay U1 with single-line voltage input. Specifically, the input terminal of the status retrieval circuit is electrically connected to the output terminal of the relay U1 and the output power terminal of the isolation chip U3, respectively. When the relay U1 outputs an electrical signal to the status retrieval circuit, the output power terminal of the isolation chip U3 is used as a reference point to quickly determine the level of the electrical signal output by the relay U1. The status retrieval circuit then determines the working state of the relay U1 based on the input high or low level signal and feeds it back to the CPU, thereby realizing the status acquisition of the relay U1 under single-line input voltage.

[0013] The specific embodiments of this utility model will be described in further detail below with reference to the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings described below are merely some embodiments. Those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of a relay feedback circuit for wire voltage input according to an embodiment of the present invention; Figure 2 This is an embodiment of the present utility model. Figure 1 A schematic diagram of the isolation chip; Figure 3 This is an embodiment of the present utility model. Figure 1 A schematic diagram of relay connections; Figure 4 This is an embodiment of the present utility model. Figure 1 Schematic diagram of state recovery circuit It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but rather to illustrate the concept of the present invention to those skilled in the art by referring to specific embodiments. Detailed Implementation

[0015] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0016] It should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application or to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0017] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0018] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0019] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0020] Figure 1 This invention provides a schematic diagram of a relay feedback circuit with a single-line voltage input. (See attached diagram.) Figure 1 As shown, the single-line voltage input relay feedback circuit of this application includes an isolation chip U3, a relay U1, and a status feedback circuit. The first input terminal of the relay U1 is electrically connected to the CPU to receive the control signal output by the CPU. The second input terminal of the relay U1 is electrically connected to the first input power supply 110V_IN to access the test voltage. The output terminal of the relay U1 is electrically connected to the input terminal of the status feedback circuit so that when the relay U1 is closed, the first input power supply 110V_IN can output an electrical signal to the status feedback circuit through the relay U1. The output power terminal ISO_VCC_5V of the isolation chip U3 is shorted to the first input power supply 110V_IN. The status feedback circuit includes a PMOS transistor Q2, the gate of the PMOS transistor Q2 (i.e., Figure 1 The G terminal of the PMOS transistor Q2 is electrically connected to the output terminal of the relay, and the source terminal of the PMOS transistor Q2 (i.e., Figures 1 to 3 The S terminal of the PMOS transistor Q2 is electrically connected to the output power supply terminal of the isolation chip U3, and the drain of the PMOS transistor Q2 (i.e., Figures 1 to 3 The D terminal of Q2 is suitable for electrical connection with the input terminal of the CPU to output the operating status of relay U1 to the CPU.

[0021] This application introduces an isolation chip U3 into the relay feedback circuit with a single-line voltage input. Specifically, the input terminal of the status feedback circuit is electrically connected to the output terminal of the relay U1 and the output power terminal ISO_VCC_5V of the isolation chip U3, respectively. When the relay outputs an electrical signal to the status feedback circuit, the output power terminal ISO_VCC_5V of the isolation chip U3 is used as a reference point to quickly determine the level of the electrical signal output by the relay U1. The status feedback circuit then determines the working state of the relay U1 based on the input high or low level signal and feeds it back to the CPU, thereby realizing the relay status acquisition under single-line input voltage.

[0022] In one possible implementation, the isolation chip U3 includes an isolation power module suitable for performing 5V voltage isolation conversion, and the isolation power module is model PDL02-05S05.

[0023] In one possible implementation, see [link to relevant documentation] Figures 1 to 2 As shown, pin 2 (+VIN) of the isolated power supply module is connected to the 5V power supply (i.e., Figure 2 The VCC_5V pin is connected to the isolation power supply module to input a 5V voltage. Pin 1 (-VIN) of the isolation power supply module is grounded, and pin 2 (+VIN) is also electrically connected to pin 1 (-VIN). The corresponding isolation chip U3 module U3 outputs a 5V voltage at pin 6 (+VOUT). Figure 2 (ISO_VCC_5V), pin 7 (-VOUT terminal) of isolation chip U3 module U3 is also grounded (i.e., Figure 2 The isolation power supply module's pins 6 (+VOUT) and 7 (-VOUT) are also electrically connected to isolate and convert the 5V voltage through the isolation chip U3. Pin 6 (+VOUT) serves as the output power supply terminal of the isolation chip U3, suitable for outputting 5V voltage, while pin 7 (-VOUT) serves as the ground terminal of the isolation chip U3.

[0024] In one possible implementation, a first capacitor C2 is connected between pin 2 (+VIN) and pin 1 (-VIN) of the isolated power supply module, and a second capacitor C3 is connected between pin 6 (+VOUT) and pin 7 (-VOUT).

[0025] In one possible implementation, the output power terminal of isolation chip U3, namely pin 6 (+VOUT), is shorted to the first input power supply 110V_IN, and the first input power supply 110V_IN is electrically connected to the second input terminal of relay U1. Relay U1 is a solid-state relay, and its model number is G3VM-201G2TR.

[0026] In one possible implementation, the first input terminal of relay U1 is electrically connected to the CPU. The CPU is electrically connected to the first input terminal of relay U1 via a control circuit. That is, the output terminal of the control circuit is electrically connected to the first input terminal of relay U1, the input terminal of the control circuit is electrically connected to the output terminal of the CPU, and the CPU is adapted to output control signals to relay U1 via the control circuit. Specifically, pin 2 (LED- terminal) of relay U1 serves as the first input terminal, pin 3 (LOAD- terminal) serves as the second input terminal, pin 1 (LED+ terminal) serves as the third input terminal, and pin 4 (LOAD+ terminal) serves as the output terminal.

[0027] In one possible implementation, see [link to relevant documentation] Figure 3 As shown, the control circuit also includes an NMOS transistor Q1. The gate of the NMOS transistor Q1 is electrically connected to the output terminal of the CPU, the source of the NMOS transistor Q1 is grounded, and the drain of the NMOS transistor Q1 is electrically connected to the first input terminal of the relay U1.

[0028] In one possible implementation, the first input terminal of relay U1, pin 2 (LED-), is electrically connected to pin 3 (D) of NMOS transistor Q1. The CPU output terminal is electrically connected to pin 1 (G) of NMOS transistor Q1, and pin 2 (S) of NMOS transistor Q1 is grounded. The second input terminal of relay U1, pin 3 (LOAD-), is electrically connected to a 110V input power supply. The output terminal of relay U1, pin 4 (LOAD+), is electrically connected to the input terminal of the state feedback circuit, pin 1 (G) of the PMOS transistor, so that the CPU outputs a control signal to relay U1 through NMOS transistor Q1. Simultaneously, the control circuit also includes a first resistor R2 and a third capacitor C1. The first resistor R2 and the third capacitor C1 are connected in parallel, with one end of each connected to the CPU output terminal and the other end grounded.

[0029] In one possible implementation, relay U1 is also connected to a second input power supply, which is electrically connected to the third input terminal of relay U1. That is, pin 1 (LED+ terminal) of relay U1 is connected to the second input power supply (i.e.,... Figure 2 Connect VCC (3.3V) to supply power to relay U1.

[0030] In one possible implementation, a second resistor R1 is also included, which is electrically connected to both the second input power supply and the third input terminal of the relay U1. See [link to relevant documentation]. Figure 3 As shown, pin 1 (LED+ terminal) of relay U1 is electrically connected to the second resistor R1 and then to the second input power supply ( Figure 3Connect to VCC (3.3V).

[0031] In one possible implementation, the output terminal of relay U1 is electrically connected to the input terminal of the state feedback circuit to receive the electrical signal output by relay U1. The output terminal of the state feedback circuit is electrically connected to the input terminal of the CPU to determine the operating state of the relay based on the received electrical signal and feed it back to the CPU. A transient voltage suppressor D1 is also connected between the second input terminal and the output terminal of relay U1 to protect relay U1; that is, the transient voltage suppressor D1 is electrically connected to pin 3 (LOAD-) and pin 4 (LOAD+) of relay U1, respectively.

[0032] In one possible implementation, see [link to relevant documentation] Figure 4 As shown, the status retrieval circuit includes a PMOS transistor Q2. The gate of the PMOS transistor Q2 is electrically connected to the output terminal of the relay U1, the source of the PMOS transistor Q2 is electrically connected to the output power terminal of the isolation chip U3, and the drain of the PMOS transistor is electrically connected to the input terminal of the CPU.

[0033] In one possible implementation, pin 1 (G terminal) of PMOS transistor Q2 is electrically connected to pin 4 (LOAD+ terminal) of relay U1. Pin 2 (S terminal) of PMOS transistor Q2 is electrically connected to ISO_VCC_5V, and pin 3 (D terminal) of PMOS transistor Q2 is electrically connected to the input terminal of the CPU.

[0034] In one possible implementation, the drain of PMOS transistor Q2 is also suitable for electrical connection to the ground terminal of isolation chip U3, that is, pin 3 (D terminal) of PMOS transistor Q2 is electrically connected to ISO_VCC_GND.

[0035] In one possible implementation, an optocoupler U2 is also included, through which the drain of the PMOS transistor Q2 is electrically connected to the ground terminal of the isolation chip U3 and the input terminal of the CPU, respectively. See [link to relevant documentation]. Figure 4 As shown, pin 1 of optocoupler U2 is electrically connected to pin 3 (D terminal) of PMOS transistor Q2, pin 2 of optocoupler U2 is electrically connected to ISO_VCC_GND, pin 3 of optocoupler U2 is grounded, and pin 4 of optocoupler U2 is electrically connected to the output terminal of the CPU. The CPU's input terminal is also electrically connected to an external power supply. Figure 4 (VCC_3.3V) to continuously output a high-level signal to the CPU.

[0036] In one possible implementation, the state acquisition circuit further includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The third resistor R3 and the sixth resistor R6 are connected in series. One end of the sixth resistor R6 is electrically connected to pin 4 (LOAD+) of relay U1, and the other end is electrically connected to one end of the third resistor R3 and pin 1 (G) of PMOS transistor Q2. The other end of the third resistor R3 is electrically connected to ISO_VCC_5V. The fifth resistor R5 is electrically connected to pin 3 (D) of the PMOS transistor and pin 1 of optocoupler U2. The fourth resistor R4 is electrically connected to the CPU input and the external power supply. Preferably, the third resistor R3 is a 1M ohm resistor, and the sixth resistor R6 is preferably a 10M ohm resistor.

[0037] Test procedure for relay U1 status retrieval circuit: In one possible implementation, when the CPU outputs a high-level signal to relay U1, VGS > 0 for NMOS transistor Q1, causing Q1 to conduct. At this time, the diode inside relay U1 illuminates, and pins 3 and 4 of relay U1 conduct. The first input power supply 110V can then be output through the output terminal of relay U1. Simultaneously, the status feedback circuit receives the 110V electrical signal (i.e., ...). Figure 4 (110V_OUT is 110V). Referencing the ISO_VCC_5V output power supply terminal of the connected isolation chip U3, since the output power supply terminal of the isolation power module, i.e., pin 6 (+VOUT terminal), is shorted to the 110V first input power supply 110V_IN, the voltage at the ISO_VCC_5V terminal connected to the status feedback circuit is equivalent to 110V. In other words, Figure 4 When ISO_VCC_5V and 110V_OUT are both 110V, and VG and VS of the PMOS transistor are both 110V, the PMOS transistor Q2 is not conducting, the optocoupler U2 is also not conducting, and the CPU input can only receive the high-level signal provided by the VCC_3.3V power supply. The CPU then obtains the working state of the relay U1 being open.

[0038] When the CPU outputs a low-level signal to relay U1, the VGS of NMOS transistor Q1 is less than 0, and NMOS transistor Q1 is not turned on. At this time, pins 3 and 4 of relay U1 will not be turned on. Relay U1 outputs an electrical signal to the status feedback circuit. The electrical signal received by the status feedback circuit is a low-level signal compared to the 110V voltage of ISO_VCC_5V, that is, 110V_OUT is 0V at this time. Since the third resistor R3 and the sixth resistor R6 divide the actual 110V voltage of ISO_VCC_5V, the VGS of PMOS transistor is less than 0, that is, PMOS transistor Q2 is turned on, and optocoupler U2 is also turned on. At this time, the CPU input terminal is grounded, and the status feedback circuit outputs a low-level signal to the CPU input terminal. The CPU obtains the working state of relay U1 being off.

[0039] Therefore, this application provides a relay status feedback circuit for single-line voltage input, enabling relay status feedback when the relay has only one input power line. Specifically, this application introduces an isolation chip U3 into the relay status feedback circuit to form a complete loop. This allows the electrical signal output from the relay output to the status feedback circuit to use the output power terminal and ground terminal of the isolation chip U3 as reference points, creating a potential difference between the relay output and the reference points. This allows the circuit to determine whether the output signal is high or low, and then uses this high or low signal to determine the relay's operating state, thus achieving relay status feedback even with only one power line. Furthermore, this application's feedback circuit has a simple structure, requiring no complex circuit design, significantly reducing hardware costs. Additionally, this application uses reasonable grounding and isolation design to avoid the risk of electric shock to operators and damage to equipment, thereby extending the service life of the feedback circuit.

[0040] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A relay feedback circuit with single-line voltage input, characterized in that, include: Isolation chip U3, relay U1, status feedback circuit; The first input terminal of the relay U1 is electrically connected to the CPU to receive the control signal output by the CPU; the second input terminal of the relay U1 is electrically connected to the first input power supply to receive the test voltage; the output terminal of the relay U1 is electrically connected to the input terminal of the state acquisition circuit so that when the relay U1 is closed, the first input power supply can output an electrical signal to the state acquisition circuit through the relay U1. The output power terminal of the isolation chip U3 is short-circuited with the first input power. The status feedback circuit includes: a PMOS transistor Q2, the gate of which is electrically connected to the output terminal of the relay U1, the source of which is electrically connected to the output power terminal of the isolation chip U3, and the drain of which is suitable for being electrically connected to the input terminal of the CPU to output the operating status of the relay U1 to the CPU.

2. The relay feedback circuit with single-line voltage input according to claim 1, characterized in that, It also includes control circuitry; The output terminal of the control circuit is electrically connected to the first input terminal of the relay U1, and the input terminal of the control circuit is adapted to be electrically connected to the output terminal of the CPU. The CPU is adapted to output control signals to the relay U1 through the control circuit.

3. The relay feedback circuit with single-line voltage input according to claim 2, characterized in that, The control circuit also includes an NMOS transistor Q1; The gate of the NMOS transistor Q1 is electrically connected to the output terminal of the CPU, the source of the NMOS transistor Q1 is grounded, and the drain of the NMOS transistor Q1 is electrically connected to the first input terminal of the relay U1.

4. The relay feedback circuit with single-line voltage input according to claim 1, characterized in that, It also includes a second input power supply; The second input power supply is electrically connected to the third input terminal of the relay U1, and is suitable for supplying power to the relay U1.

5. A relay feedback circuit with single-line voltage input according to claim 1, characterized in that, The drain of the PMOS transistor Q2 is also suitable for electrical connection to the ground terminal of the isolation chip U3.

6. The relay feedback circuit with single-line voltage input according to claim 1, characterized in that, It also includes optocoupler U2; The drain of the PMOS transistor Q2 is electrically connected to the ground terminal of the isolation chip U3 and the input terminal of the CPU through the optocoupler U2.

7. A relay feedback circuit with single-line voltage input according to claim 1, characterized in that, It also includes a transient voltage suppressor D1, suitable for protecting the relay U1; The transient voltage suppressor D1 is electrically connected to the second input terminal and the output terminal of the relay U1, respectively.

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