Battery synchronous data acquisition device, battery pack and vehicle

Abstract

This application relates to battery management technology and discloses a battery synchronous acquisition device, a battery pack, and a vehicle. The device includes: a controller and at least two front-end acquisition chips, wherein the front-end acquisition chips are connected in parallel; the controller connects to each front-end acquisition chip via a signal line and a communication bus, and distributes a synchronization signal to each front-end acquisition chip via the signal line; each front-end acquisition chip is connected to a corresponding cell group, and each front-end acquisition chip, in response to the received synchronization signal, acquires data from the connected cell group and sends the acquired data to the controller via the communication bus. Through this device, this application enables multiple front-end acquisition chips to synchronously acquire cell data.

Description

Technical Field

[0001] This application relates to the field of battery management technology, and in particular to a battery synchronization acquisition device, a battery pack, and a vehicle. Background Technology

[0002] Current battery synchronous acquisition devices generally adopt a synchronous acquisition scheme based on a serial communication link. This is implemented as follows: the main control unit (MCU) sequentially sends sampling commands to multiple front-end acquisition chips via a serial bus, configuring differentiated delay clock periods based on the physical location of each chip in the communication link. Specifically, the system sets a specific delay period value for each front-end acquisition chip based on parameters such as the number of chips, command transmission timing, and MCU command sending interval, thereby triggering the cell voltage acquisition operation of each chip at different time points. However, this synchronization mechanism based on communication delay period configuration has significant limitations: firstly, the system synchronization accuracy is difficult to guarantee; secondly, the synchronization stability is poor; and finally, this scheme has weak resistance to communication interference and is easily affected by the external environment. Utility Model Content

[0003] In view of this, embodiments of this application provide a battery synchronization acquisition device, a battery pack, and a vehicle, which can effectively improve the synchronization and stability of cell data acquisition.

[0004] In a first aspect, embodiments of this application provide a battery synchronous acquisition device, comprising: a controller and at least two front-end acquisition chips; wherein the front-end acquisition chips are connected in parallel.

[0005] The controller is connected to each of the front-end acquisition chips via a signal line and a communication bus.

[0006] The controller distributes a synchronization signal to each of the front-end acquisition chips via the signal line;

[0007] Each of the aforementioned front-end acquisition chips is connected to a battery cell group. In response to the received synchronization signal, each of the aforementioned front-end acquisition chips acquires data from the battery cell group connected to it and sends the acquired data to the controller via the communication bus.

[0008] In some embodiments, the system further includes a switch driving circuit, one end of which is connected to the controller and the other end of which is connected to each of the front-end acquisition chips. The synchronization signal output by the controller is amplified and enhanced by the switch driving circuit and then sent to each of the front-end acquisition chips.

[0009] In some embodiments, the switch driving circuit includes a transistor, a first current-limiting resistor, a pull-up resistor, and a first pull-down resistor;

[0010] The controller is connected to the base of the transistor through the first current-limiting resistor, so as to limit the current flowing into the base through the first current-limiting resistor;

[0011] The emitter of the transistor is connected to the supply voltage, and the pull-up resistor is connected between the base and the emitter of the transistor to pull up the base voltage of the transistor when the controller is in a high-impedance state.

[0012] The collectors of the transistors are connected to each of the front-end acquisition chips, and the collectors are also grounded through the first pull-down resistor.

[0013] In some embodiments, the switch driving circuit includes a field-effect transistor, a second current-limiting resistor, and a second pull-down resistor;

[0014] The controller is connected to the gate of the field-effect transistor via the second current-limiting resistor to limit the current flowing into the gate via the second current-limiting resistor;

[0015] The drain of the field-effect transistor is connected to the power supply voltage; the source of the field-effect transistor is connected to each of the front-end acquisition chips, and the source is also grounded through the second pull-down resistor.

[0016] In some implementations, each of the front-end acquisition chips triggers a single data acquisition operation on the connected battery cell group when it detects the rising or falling edge of the synchronization signal.

[0017] In some implementations, the synchronization signal is a high-low level pulse signal with a preset period, so that the front-end acquisition chip can detect the edge changes of the synchronization signal.

[0018] In some embodiments, the communication bus is a serial communication bus, which includes one of SPI, UART and ISO-SPI.

[0019] In some implementations, the controller sequentially reads data collected by each front-end acquisition chip via the serial communication bus.

[0020] Secondly, embodiments of this application provide a battery pack, including the aforementioned battery synchronization acquisition device and several battery cell groups.

[0021] Thirdly, embodiments of this application provide a vehicle including the aforementioned battery pack.

[0022] The embodiments of this application have the following beneficial effects: In this embodiment, the controller connects multiple parallel front-end acquisition chips through the same signal line, thereby enabling the unified and synchronous output of synchronization signals to multiple front-end acquisition chips. This allows each front-end acquisition chip to receive the synchronization signal simultaneously and thus synchronously start acquiring cell data from the connected cell group. The device has a simple structure and avoids the timing deviation problem caused by traditional methods that rely on communication delay configuration for acquisition synchronization, thereby improving the synchronization and consistency of acquisition operations among multiple front-end acquisition chips. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of a battery synchronization acquisition device according to an embodiment of this application is shown;

[0025] Figure 2 A schematic diagram of the first switch driving circuit according to an embodiment of this application is shown;

[0026] Figure 3 A schematic diagram of the second switch driving circuit according to an embodiment of this application is shown;

[0027] Figure 4 A schematic diagram of the synchronization signal according to an embodiment of this application is shown.

[0028] Key component symbols: 100-Controller; 200-Front-end acquisition chip; 300-Battery cell assembly; R1-First current-limiting resistor; R2-Pull-up resistor; R3-First pull-down resistor; Q1-Transistor; Q2-Field-effect transistor; R4-Second current-limiting resistor; R5-Second pull-down resistor. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0030] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0032] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0033] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] The battery synchronization acquisition device will be described below with reference to some specific embodiments.

[0035] Figure 1 A schematic diagram of a battery synchronous acquisition device according to an embodiment of this application is shown. Exemplarily, the battery synchronous acquisition device includes: a controller 100 and a plurality of front-end acquisition chips 200, wherein the various front-end acquisition chips 200 are connected in parallel.

[0036] For example, the controller 100 can be an MCU (microcontroller). In this battery synchronous acquisition device, the MCU acts as the main control unit, responsible for controlling the cell data acquisition operation of multiple front-end acquisition chips (AFE chips) 200. It controls the sampling through the synchronous signal output terminal and reads the cell data acquired by each front-end acquisition chip 200 through the communication line, so as to realize efficient and synchronous monitoring of the battery pack status.

[0037] It is understandable that an MCU can be connected to multiple parallel front-end acquisition chips 200 at the same time, and each front-end acquisition chip 200 is connected to a battery cell group 300. That is, each front-end acquisition chip 200 is used to collect the battery cell data of the corresponding battery cell group 300.

[0038] In this embodiment, the controller 100 is connected to multiple parallel front-end acquisition chips 200 via a signal line to output a synchronization signal to all front-end acquisition chips 200. The controller 100 is also connected to each front-end acquisition chip 200 via an independent communication bus to read the cell data collected by each front-end acquisition chip 200. That is, after the front-end acquisition chip 200 collects the cell data of the corresponding cell group 300, it sends the collected data to the controller 100 via the communication bus.

[0039] Exemplarily, the synchronization signal output terminal of the controller 100 can be a general purpose input / output interface (GPIO). When the GPIO driving capability of the controller 100 is sufficient to drive all connected front-end acquisition chips 200, the GPIO can be directly connected to the synchronization signal input terminal of each front-end acquisition chip 200 through a signal line to realize the transmission of synchronization signals. Since each front-end acquisition chip 200 in this application is connected to a corresponding battery cell group 300, and the front-end acquisition chips 200 are connected in parallel, there is no connection interference between the front-end acquisition chips 200. Furthermore, the controller 100 sends a synchronization signal to each front-end acquisition chip 200 through a synchronization signal line, so that each front-end acquisition chip 200 can simultaneously receive the synchronization signal and respond to the synchronization signal to synchronously start the data acquisition work of the corresponding battery cell group 300.

[0040] The synchronization signal is a high-low level pulse signal with a preset period output by the controller 100. Its edges (e.g., rising edge or falling edge) are used to trigger the front-end acquisition chip 200 to perform the cell data acquisition operation. Each front-end acquisition chip 200 responds to the edge change of the synchronization signal and immediately starts to acquire the voltage of the connected cell group 300, thereby realizing highly synchronized acquisition of multiple front-end acquisition chips 200 in time.

[0041] In addition, the controller 100 is connected to each front-end acquisition chip 200 via a communication line. This allows the controller 100 to read the cell data for the current cycle stored in the front-end acquisition chip 200 after the chip has acquired the cell data. The communication bus can be a serial communication bus, such as SPI, UART, or ISO-SPI. The controller 100 communicates sequentially with each front-end acquisition chip 200 to obtain the acquired cell data, thereby completing comprehensive monitoring of the entire battery pack's status.

[0042] This embodiment improves the pseudo-synchronous acquisition method, which originally relied on the sequential control of the communication link, into a hardware synchronization mechanism based on edge triggering by using the same signal line. This enables multiple front-end acquisition chips 200 to acquire data in a highly synchronized manner in time, thereby improving the accuracy and real-time performance of the battery synchronization acquisition device in monitoring the battery pack status.

[0043] In some embodiments, the battery synchronization acquisition device further includes a switch driving circuit, one end of which is connected to the controller 100 and the other end is connected to each front-end acquisition chip 200. The synchronization signal output by the controller 100 is sent to each front-end acquisition chip 200 via the switch driving circuit.

[0044] As an example, when the GPIO drive capability of the controller 100 is insufficient to directly drive the synchronization signal input terminals of multiple front-end acquisition chips 200, a switch drive circuit can be set between the controller 100 and the front-end acquisition chips 200 as a drive enhancement unit. The switch drive circuit is used to amplify and enhance the synchronization signal output by the controller 100 to ensure the integrity and stability of the signal and prevent acquisition asynchrony due to signal attenuation or excessive load.

[0045] The switching device in the switch driver circuit can be a transistor or a MOSFET. MOSFETs are suitable for high-frequency synchronization signal scenarios, offering lower conduction losses and higher response speeds; transistors, on the other hand, are less expensive and suitable for low-frequency or mid-frequency applications. Furthermore, the switch driver circuit also provides signal isolation, preventing excessive load on the GPIO of the controller 100 from multiple AFE chips, thereby improving the stability and anti-interference capability of the battery synchronization acquisition device. This design allows for flexible selection of the synchronization signal driving method according to actual needs, thus improving the reliability and applicability of synchronization acquisition.

[0046] like Figure 2 As shown, if the switching device in the switch driving circuit is a transistor, then the switch driving circuit includes a transistor Q1, a first current-limiting resistor R1, a pull-up resistor R2, and a first pull-down resistor R3.

[0047] The synchronization signal output terminal of the controller 100 is connected to the base of the transistor Q1 through the first current-limiting resistor R1 to limit the current flowing into the base and prevent damage to the controller 100 or the transistor Q1 due to excessive current. The transistor Q1 can be a PNP transistor, with its emitter connected to the power supply voltage VCC.

[0048] To further improve circuit stability, a pull-up resistor R2 is connected between the base of transistor Q1 and the supply voltage VCC. This resistor pulls up the base voltage of transistor Q1 when the controller 100 is in a high-impedance state (such as a reset or non-operation state), thereby ensuring that transistor Q1 is reliably cut off and avoiding false triggering due to floating input.

[0049] Furthermore, the collector of transistor Q1 is grounded through the first pull-down resistor R3, and the synchronization signal input terminals of multiple front-end acquisition chips 200 are connected to the connection line between the collector of transistor Q1 and the first pull-down resistor R3. When the controller 100 outputs a low level, transistor Q1 is turned on, its collector potential is pulled low, and the synchronization signal input terminal of the front-end acquisition chip 200 is pulled low to near ground potential; when the controller 100 outputs a high level, transistor Q1 is turned off, and the synchronization signal output node is kept at a low level through the pull-down resistor R3. Therefore, when using this transistor switching drive circuit to connect the controller and the front-end acquisition chip, the edge triggering mode of the front-end acquisition chip 200 needs to be configured so that rising edge triggering is invalid and falling edge triggering is valid, or the controller sends periodic low-level pulses (i.e., falling edges) to trigger the acquisition action of the AFE chip, so as to realize the synchronous acquisition of cell voltage by multiple front-end acquisition chips 200.

[0050] like Figure 3 As shown, if the switching device in the switch driving circuit is a field-effect transistor (MOS transistor), then the switch driving circuit includes a field-effect transistor Q2, a second current-limiting resistor R4, and a second pull-down resistor R5.

[0051] The synchronization signal output terminal of the controller 100 is connected to the gate of the field-effect transistor Q2 through the second current-limiting resistor R4 to limit the current flowing into the gate and prevent damage to the controller 100 or the field-effect transistor Q2 due to excessive current.

[0052] The field-effect transistor Q2 can be an N-channel enhancement-mode field-effect transistor (FET). Its drain is connected to the supply voltage VCC, and its source is grounded through a second pull-down resistor R5. The synchronization signal input terminals of multiple front-end acquisition chips 200 are connected to the node between the source of FET Q2 and the second pull-down resistor R5. When the controller 100 outputs a high level, the gate voltage of FET Q2 is higher than its threshold voltage, so FET Q2 is turned on, and the source potential is pulled down to near ground potential, and the synchronization signal input terminal of the front-end acquisition chip 200 is at a low level. When the controller 100 outputs a low level, FET Q2 is turned off, and the synchronization signal output terminal is kept at a low level through the pull-down resistor R5. Therefore, when using this FET switch drive circuit, since the controller 100 outputs a high level to trigger FET Q2 to turn on and generate a falling edge, the front-end acquisition chip 200 needs to be configured to a falling edge triggered single acquisition mode to achieve synchronous acquisition of the cell voltage by multiple front-end acquisition chips 200. Through this MOSFET switching drive circuit, the device can achieve stable signal transmission in high-frequency synchronization signal scenarios. It has advantages such as fast response speed and low on-state voltage, and is suitable for battery synchronization acquisition devices with high requirements for acquisition synchronization.

[0053] In some implementations, each front-end acquisition chip triggers a single data acquisition operation on the connected battery cell group when it detects the rising or falling edge of the synchronization signal.

[0054] Exemplary, the front-end acquisition chip 200 supports an edge-triggered single-acquisition mode and receives a synchronization signal via a pin to trigger a single data acquisition of the cell data for the corresponding cell group. The front-end acquisition chip 200 internally includes an edge detection component for detecting voltage changes at the synchronization signal input. When a predetermined edge transition (such as a rising or falling edge) is detected in the synchronization signal, the front-end acquisition chip 200 initiates a cell data acquisition operation.

[0055] In this single-data acquisition mode, the front-end acquisition chip 200 does not perform continuous acquisition. Instead, it performs only one cell data acquisition operation after receiving a trigger signal, and automatically stops after acquisition is completed without repetition. This method effectively avoids the acquisition asynchrony problems caused by inconsistent acquisition timing and communication delays in continuous acquisition mode. It enables the controller 100 to precisely control the acquisition time of each front-end acquisition chip 200, ensuring that all front-end acquisition chips 200 start acquisition at the same time, thereby significantly improving the overall acquisition accuracy and stability of the battery synchronous acquisition device.

[0056] Furthermore, the front-end acquisition chip has an internal register, which is configured by the controller to set the edge-triggered single acquisition mode.

[0057] Exemplary configuration involves configuring all front-end acquisition chips 200 before the controller 100 begins synchronous data acquisition. This configuration is achieved via the communication line between the controller 100 and the front-end acquisition chips 200. The controller 100 sequentially accesses each front-end acquisition chip 200 via the serial communication bus, writing a configuration bit to its register to set "edge-triggered single acquisition." This configuration bit activates the edge detection component inside the front-end acquisition chip 200 and sets its trigger edge type (e.g., rising edge or falling edge). Through this register configuration method, the controller 100 can flexibly control the acquisition behavior of each front-end acquisition chip 200, ensuring that all front-end acquisition chips 200 use a consistent triggering method in subsequent acquisition processes, thereby achieving synchronous acquisition of cell data by multiple front-end acquisition chips 200. This configuration method is simple in structure, low in implementation cost, and suitable for the application requirements of multi-cell battery pack management systems.

[0058] In some implementations, the controller reads the data collected by each front-end acquisition chip sequentially via a serial communication bus.

[0059] Exemplary, the controller 100 connects to each front-end acquisition chip 200 via a communication bus for configuring acquisition parameters and reading the acquired cell voltage data. In practical applications, the serial communication bus can use a daisy-chain connection or a star topology to achieve communication between the controller 100 and multiple front-end acquisition chips 200. The daisy-chain connection offers advantages such as simple wiring, unified communication timing, and ease of multi-chip cascading control, making it suitable for battery synchronous acquisition devices where multiple front-end acquisition chips 200 acquire data in parallel. The controller 100 can read data sequentially according to the physical order of the front-end acquisition chips 200 in the communication link, ensuring controllable communication timing and a unique data reading order, which helps improve the overall acquisition efficiency and synchronization. The star topology is suitable for scenarios with high requirements for communication latency. The controller 100 and each front-end acquisition chip 200 have independent communication channels, which improves the real-time performance and anti-interference capability of the communication. The use of a serial communication bus has advantages such as high communication speed, strong anti-interference ability and simple wiring. It is suitable for application scenarios of synchronous acquisition of voltage of multiple battery cells and can ensure that the controller can complete the data acquisition and configuration management tasks efficiently and stably.

[0060] In some implementations, such as Figure 4 As shown, the synchronization signal (a high-low level pulse signal with a preset period) is a periodic square wave signal; the period of the synchronization signal output by the controller is determined based on the single acquisition time of the front-end acquisition chip 200 and the reading time of the controller 100 to read all the cell data acquired by the front-end acquisition chip 200.

[0061] In this embodiment, the period T3 of the synchronization signal is set based on the single acquisition time of the front-end acquisition chip 200 and the time required for the controller 100 to read all the data acquired by the front-end acquisition chip 200, and the formula is as follows: Where T1 is the time required for the front-end acquisition chip 200 to complete one cell data acquisition, and T2 is the total time for the controller 100 to sequentially read the acquired data from the internal registers of all front-end acquisition chips 200. As a margin, the margin can be set to 10%-20% according to the needs to cope with uncertainties such as fluctuations in data acquisition time, delays in controller task scheduling, and communication interference, so as to ensure the integrity of data acquisition operations and the stability of operation.

[0062] The controller 100 generates a synchronization signal with a preset period T3 through its internal timer component and continuously outputs this signal through the synchronization signal output terminal. Upon detecting the rising or falling edge of the synchronization signal, all front-end acquisition chips 200 simultaneously initiate a cell data acquisition operation. Within the synchronization signal period, the controller 100 completes the reading of data collected by all front-end acquisition chips 200, thereby achieving highly synchronized acquisition across multiple front-end acquisition chips 200 in time. If T3 is set too short, some data from the front-end acquisition chips 200 may not be fully read, affecting the integrity of the acquisition; if T3 is set too long, the acquisition frequency will decrease, affecting the real-time performance of battery status monitoring. Therefore, by setting T3 appropriately, efficient, stable, and synchronized acquisition can be achieved.

[0063] It is understood that the data collected by the front-end acquisition chip 200 includes, but is not limited to, the voltage data of each individual cell in the corresponding cell group 300, the total voltage and current data of the cell group 300, and the cell temperature data. The acquisition results are temporarily stored in the data register inside the front-end acquisition chip 200 for the controller 100 to read.

[0064] In this embodiment, the controller 100 interacts with each front-end acquisition chip 200 via serial communication. As the master device, the controller 100 sequentially sends read commands to each front-end acquisition chip 200 and receives the acquired data returned by them. After reading, the controller 100 can perform unified processing on the acquired cell data, such as performing consistency analysis to identify cells with abnormal voltage; calculating key parameters such as the overall battery pack voltage, SOC, and SOH; and uploading the data to a host computer or BMS main control system for subsequent operations such as thermal management, equalization control, and fault warning.

[0065] In this embodiment, a controller connects multiple front-end acquisition chips 200 via the same signal line, enabling a unified output of a synchronization signal to these chips. Each chip 200 responds to edge changes of the synchronization signal and synchronously initiates data acquisition from the connected battery cell group. This acquisition device has a simple structure and avoids the timing deviation problems caused by traditional methods that rely on communication delay configuration for data acquisition synchronization. This improves the synchronization and consistency of data acquisition operations among the multiple front-end acquisition chips 200.

[0066] This application also proposes a battery pack, including the aforementioned battery synchronization acquisition device, multiple cell groups, and mechanical structural components for encapsulating and fixing the cell groups. The battery synchronization acquisition device is integrated inside the battery pack and is connected to each cell group through various front-end acquisition chips 200 in the battery synchronization acquisition device. It is used to collect data such as voltage, current, and temperature of each cell group to evaluate and manage the overall status of the battery pack.

[0067] This application also provides a vehicle including the aforementioned battery pack. The battery pack serves as the vehicle's power source, providing electrical energy to the vehicle's drive system. A battery synchronization acquisition device can be integrated into the vehicle's energy management system, communicating with the vehicle control unit (VCU) to provide cell status information (such as SOC, SOH, temperature distribution, etc.) for vehicle energy management, thermal management, equalization control, and fault diagnosis. This vehicle can be a battery electric vehicle (BEV), a plug-in hybrid electric vehicle (PHEV), or other transportation vehicles using a power battery as a power source. Through this configuration, the vehicle can achieve efficient monitoring and management of the power battery status, improving vehicle safety and range.

[0068] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A battery synchronous acquisition device, characterized in that, include: The controller (100) and at least two front-end acquisition chips (200) are provided; wherein the front-end acquisition chips (200) are connected in parallel. The controller (100) is connected to each of the front-end acquisition chips (200) by a signal line and a communication bus respectively. The controller (100) distributes a synchronization signal to each of the front-end acquisition chips (200) through the signal line. Each of the aforementioned front-end acquisition chips (200) is connected to a battery cell group (300). Each of the aforementioned front-end acquisition chips (200) responds to the received synchronization signal, acquires data from the battery cell group (300) connected to it, and sends the acquired data to the controller (100) via the communication bus.

2. The battery synchronous acquisition device according to claim 1, characterized in that, Also includes: A switch driving circuit is provided, one end of which is connected to the controller (100) and the other end is connected to each of the front-end acquisition chips (200). The synchronization signal output by the controller (100) is amplified and enhanced by the switch driving circuit and then sent to each of the front-end acquisition chips (200).

3. The battery synchronous acquisition device according to claim 2, characterized in that, The switch driving circuit includes a transistor (Q1), a first current-limiting resistor (R1), a pull-up resistor (R2), and a first pull-down resistor (R3). The controller (100) is connected to the base of the transistor (Q1) through the first current-limiting resistor (R1) to limit the current flowing into the base through the first current-limiting resistor (R1); The emitter of the transistor (Q1) is connected to the supply voltage, and the pull-up resistor (R2) is connected between the base of the transistor (Q1) and the emitter to pull up the base voltage of the transistor (Q1) when the controller (100) is in a high-resistance state. The collector of the transistor (Q1) is connected to each of the front-end acquisition chips (200), and the collector is also grounded through the first pull-down resistor (R3).

4. The battery synchronous acquisition device according to claim 2, characterized in that, The switch driving circuit includes a field-effect transistor (Q2), a second current-limiting resistor (R4), and a second pull-down resistor (R5). The controller (100) is connected to the gate of the field-effect transistor (Q2) via the second current-limiting resistor (R4) to limit the current flowing into the gate via the second current-limiting resistor (R4); The drain of the field-effect transistor (Q2) is connected to the power supply voltage; the source of the field-effect transistor (Q2) is connected to each of the front-end acquisition chips (200), and the source is also grounded through the second pull-down resistor (R5).

5. The battery synchronous acquisition device according to claim 1, characterized in that, Each of the front-end acquisition chips (200) triggers a single data acquisition operation on the connected battery cell group (300) when it detects the rising or falling edge of the synchronization signal.

6. The battery synchronous acquisition device according to claim 5, characterized in that, The synchronization signal is a high-low level pulse signal with a preset period, so that the front-end acquisition chip (200) can detect the edge change of the synchronization signal.

7. The battery synchronous acquisition device according to claim 1, characterized in that, The communication bus is a serial communication bus, which includes one of SPI, UART and ISO-SPI.

8. The battery synchronous acquisition device according to claim 7, characterized in that, The controller (100) reads the data collected by each front-end acquisition chip (200) sequentially through the serial communication bus.

9. A battery pack, characterized in that, Includes the battery synchronous acquisition device as described in any one of claims 1-8 and a plurality of battery cell groups (300).

10. A vehicle, characterized in that, include: The battery pack as described in claim 9.

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