Source driven buck pfc circuit

Abstract

This utility model relates to the field of power factor correction circuit technology, and particularly to a source-driven buck power factor correction circuit, including a main control chip U1, a power switch Q1, a rectifier module, a source drive module, a current sampling module, and a voltage sampling module; one end of the rectifier module is connected to a current input interface, and the other end is connected to a load output interface; the gate of the power switch Q1 is connected to the main control chip U1, and its drain is connected to the rectifier module and the load output interface respectively through the source drive module; the source of the power switch Q1 is connected to the main control chip U1 through the current sampling module, and the main control chip U1 is connected to the rectifier module through the voltage sampling module; this utility model provides a source-driven buck power factor correction circuit with simple circuit design, no need for high-voltage isolation and bootstrap circuits, low switching losses, high safety, high power factor, and high efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power factor correction circuit technology, and in particular to a source-driven buck power factor correction circuit. Background Technology

[0002] There are two types of power factor correction (PFC) circuits: passive power factor correction and active power factor correction. Passive power factor correction generally uses inductor compensation to reduce the phase difference between the fundamental current and voltage of the AC input, thereby improving the power factor. Active power factor correction consists of inductors, capacitors, and electronic components, and is smaller in size.

[0003] Existing active power factor correction circuits mostly employ gate-driven methods. The chip drive signal drives the gate of the MOSFET through a high-voltage isolation chip or isolation drive transformer, requiring high-voltage isolation and bootstrap circuits, resulting in complex circuit design. Furthermore, the MOSFET switch is connected in series on the high side, leading to problems such as high switching losses, low safety, and significant electromagnetic interference (EMI). In addition, existing active power factor correction circuits have low power factors (typically less than 0.9), high input current harmonic content (THD > 15%), making it difficult to meet energy efficiency standards, and they are also inefficient. Utility Model Content

[0004] The technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide a source-driven buck power factor correction circuit with simple circuit design, no need for high voltage isolation and bootstrap circuit, low switching loss, high safety, high power factor and high efficiency.

[0005] The technical solution adopted by this utility model to solve its technical problem is: a source-driven buck power factor correction circuit, including a main control chip U1, a power switch Q1, a rectifier module, a source drive module, a current sampling module, and a voltage sampling module; one end of the rectifier module is connected to a current input interface, and the other end is connected to a load output interface; the gate of the power switch Q1 is connected to the main control chip U1, and its drain is connected to the rectifier module and the load output interface respectively through the source drive module; the source of the power switch Q1 is connected to the main control chip U1 through the current sampling module, and the main control chip U1 is connected to the rectifier module through the voltage sampling module.

[0006] Furthermore, the source drive module includes an inductor L2 and a diode D7; one end of the inductor L2 is connected to one end of the diode D7, and the other end is connected to the load output interface; the other end of the diode D7 is connected to the rectifier module, and the common terminal of the inductor L2 and the diode D7 is connected to the drain of the power switch Q1.

[0007] Furthermore, the rectifier module includes a differential mode inductor L1, a rectifier bridge, and capacitors C1, C2, and C3; the differential mode inductor L1, the rectifier bridge, and capacitor C2 are connected in sequence to form a circuit; the rectifier bridge is connected to the current input interface; the common terminal of the differential mode inductor L1 and capacitor C2 is connected to the load output interface; both ends of capacitor C3 are connected to the load output interface; one end of capacitor C1 is connected to the common terminal of the differential mode inductor L1 and the rectifier bridge, and its other end is connected to the common terminal of the rectifier bridge and capacitor C2.

[0008] Further, the rectifier bridge includes diodes D1, D2, D3, D4, D5, and D6; one end of diode D1 is connected to differential mode inductor L1, and its other end is connected to capacitor C2 through diode D4; one end of diode D2 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D5; one end of diode D3 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D6; the common terminals of diodes D1 and D4, D2 and D5, and D3 and D6 are respectively connected to the current input interface.

[0009] Furthermore, the rectifier module also includes a capacitor C4, which is connected in parallel with capacitor C3.

[0010] Furthermore, the current sampling module includes a capacitor C11, resistors R2, R10, and R11; one end of the capacitor C11 is connected to pin 3 of the main control chip U1, and the other end is connected to the source of the power switch Q1 through resistors R11, R10, and R2 in sequence; the common terminal of resistors R10 and R11 is connected to pin 3 of the main control chip U1.

[0011] Furthermore, the voltage sampling module includes capacitors C8, C9, and C10, and resistors R5, R6, R7, R8, and R9; one end of capacitor C8 is connected to pin 5 of the main control chip U1, and its other end is connected to the rectifier module in sequence through resistors R8, R9, R5, R6, and R7; one end of capacitor C9 is connected to pin 5 of the main control chip U1, and its other end is connected to the common terminal of resistors R8 and R9; capacitor C10 is connected in parallel with resistor R9, and the common terminal of resistors R9 and R5 is connected to pin 6 of the main control chip U1.

[0012] Furthermore, it also includes a diode D8 and a resistor R1; one end of the diode D8 is connected to the gate of the power switch Q1, and the other end is connected to pin 8 of the main control chip U1; the resistor R1 is connected in parallel with the diode D8.

[0013] Furthermore, it also includes capacitors C5, C6, and C7, and resistors R3 and R4; one end of capacitor C5 is connected to pin 7 of the main control chip U1, and the other end is grounded; one end of capacitor C6 is connected to pin 2 of the main control chip U1, and the other end is grounded; one end of capacitor C7 is connected to pin 4 of the main control chip U1, and the other end is grounded; resistor R3 is connected in parallel with capacitor C7; one end of resistor R4 is connected to pin 4 of the main control chip U1, and the other end is connected to pin 7 of the main control chip U1.

[0014] Furthermore, the capacitor C3 is a ceramic capacitor.

[0015] The beneficial effects of this utility model are:

[0016] (1) This utility model realizes the source driving mode through the source driving module. The driving signal does not need to drive the gate of the power switch Q1 through the high voltage isolation chip or the isolation driving transformer. The power switch Q1 is directly driven on the low side. Compared with the gate driving mode, it simplifies the circuit design, eliminates the need for high voltage isolation and bootstrap circuit, improves the safety of the power switch Q1 when switching, eliminates the driving loss of the high voltage isolation chip or the isolation driving transformer, reduces the loss, improves the efficiency by 0.5%-1%, and the input current harmonic content is less than 10%, which complies with the IEC 61000-3-2BL class harmonic standard.

[0017] (2) This utility model realizes dual closed-loop control of the inner current loop and the outer voltage loop through the current sampling module and the voltage sampling module, thereby making the power factor reach 0.95 or above. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0020] The present invention will now be further described with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0021] like Figure 1As shown, a source-driven buck power factor correction circuit includes a main control chip U1, a power switch Q1, a rectifier module, a source drive module, a current sampling module, and a voltage sampling module. One end of the rectifier module is connected to a current input interface, and the other end is connected to a load output interface. The gate of the power switch Q1 is connected to the main control chip U1, and its drain is connected to both the rectifier module and the load output interface via the source drive module. The source of the power switch Q1 is connected to the main control chip U1 via the current sampling module, and the main control chip U1 is connected to the rectifier module via the voltage sampling module. Specifically, the main control chip U1 is used to generate PWM drive signals.

[0022] By implementing source-driven mode through a source-driven module, the drive signal does not need to drive the gate of power switch Q1 through a high-voltage isolation chip or isolation drive transformer. Power switch Q1 is directly driven on the low side. Compared with gate-driven mode, this simplifies circuit design, eliminates the need for high-voltage isolation and bootstrap circuits, improves the safety of power switch Q1 during switching, reduces drive losses due to the absence of high-voltage isolation chips or isolation drive transformers, improves efficiency by 0.5%-1%, and has an input current harmonic content of less than 10%, which complies with the IEC 61000-3-2BL class harmonic standard. The drive signal is also stable.

[0023] like Figure 1 As shown, the source drive module includes an inductor L2 and a diode D7; one end of the inductor L2 is connected to one end of the diode D7, and the other end is connected to the load output interface; the other end of the diode D7 is connected to the rectifier module, and the common terminal of the inductor L2 and the diode D7 is connected to the drain of the power switch Q1.

[0024] like Figure 1 As shown, the rectifier module includes a differential-mode inductor L1, a rectifier bridge, and capacitors C1, C2, C3, and C4. The differential-mode inductor L1, rectifier bridge, and capacitor C2 are connected sequentially to form a circuit. The rectifier bridge is connected to the current input interface. The common terminal of the differential-mode inductor L1 and capacitor C2 is connected to the load output interface. Both ends of capacitor C3 are connected to the load output interface. One end of capacitor C1 is connected to the common terminal of the differential-mode inductor L1 and the rectifier bridge, and its other end is connected to the common terminal of the rectifier bridge and capacitor C2. Capacitor C4 is connected in parallel with capacitor C3. Specifically, the other end of diode D7 is connected to the common terminal of the differential-mode inductor L1 and capacitor C2. Capacitor C3 is a ceramic capacitor to filter out high-frequency noise.

[0025] like Figure 1As shown, the rectifier bridge includes diodes D1, D2, D3, D4, D5, and D6; one end of diode D1 is connected to differential mode inductor L1, and its other end is connected to capacitor C2 through diode D4; one end of diode D2 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D5; one end of diode D3 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D6; the common terminals of diodes D1 and D4, D2 and D5, and D3 and D6 are respectively connected to the current input interface.

[0026] like Figure 1 As shown, the current sampling module includes capacitor C11 and resistors R2, R10, and R11. One end of capacitor C11 is connected to pin 3 of the main control chip U1, and the other end is connected to the source of power switch Q1 through resistors R11, R10, and R2 in sequence. The common terminal of resistors R10 and R11 is connected to pin 3 of the main control chip U1. The current sampling module is used to collect current signals and feed them back to the main control chip U1. Specifically, the common terminal of resistors R2 and R10 is grounded.

[0027] like Figure 1 As shown, the voltage sampling module includes capacitors C8, C9, and C10, and resistors R5, R6, R7, R8, and R9. One end of capacitor C8 is connected to pin 5 of the main control chip U1, and its other end is connected to the rectifier module sequentially through resistors R8, R9, R5, R6, and R7. One end of capacitor C9 is connected to pin 5 of the main control chip U1, and its other end is connected to the common terminal of resistors R8 and R9. Capacitor C10 is connected in parallel with resistor R9, and the common terminal of resistors R9 and R5 is connected to pin 6 of the main control chip U1. Specifically, one end of resistor R7 is connected to the common terminal of differential mode inductor L1 and capacitor C2. Capacitor C10, resistors R5, R6, R7, and R9 form a feedback resistor voltage divider, and the output voltage (i.e., the load output voltage) is fed back to pin 6 of the main control chip U1.

[0028] By using current sampling modules and voltage sampling modules, dual closed-loop control of the inner current loop and outer voltage loop is achieved, thereby enabling the power factor to reach above 0.95.

[0029] like Figure 1 As shown, the source-driven buck power factor correction circuit also includes a diode D8 and a resistor R1; one end of the diode D8 is connected to the gate of the power switch Q1, and the other end is connected to pin 8 of the main control chip U1; the resistor R1 is connected in parallel with the diode D8.

[0030] like Figure 1As shown, the source-driven buck power factor correction circuit also includes capacitors C5, C6, and C7, and resistors R3 and R4; one end of capacitor C5 is connected to pin 7 of the main control chip U1, and the other end is grounded; one end of capacitor C6 is connected to pin 2 of the main control chip U1, and the other end is grounded; one end of capacitor C7 is connected to pin 4 of the main control chip U1, and the other end is grounded; resistor R3 is connected in parallel with capacitor C7; one end of resistor R4 is connected to pin 4 of the main control chip U1, and the other end is connected to pin 7 of the main control chip U1.

[0031] The above embodiments are only for illustrating the technical concept and features of this utility model. Their purpose is to enable those skilled in the art to understand the content of this utility model and implement it. They should not be used to limit the protection scope of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be covered within the protection scope of this utility model.

Claims

1. A source driven buck power factor correction circuit, characterized by: The system includes a main control chip U1, a power switch Q1, a rectifier module, a source drive module, a current sampling module, and a voltage sampling module. One end of the rectifier module is connected to a current input interface, and the other end is connected to a load output interface. The gate of the power switch Q1 is connected to the main control chip U1, and its drain is connected to both the rectifier module and the load output interface via the source drive module. The source of the power switch Q1 is connected to the main control chip U1 via the current sampling module, and the main control chip U1 is connected to the rectifier module via the voltage sampling module.

2. The source-driven buck power factor correction circuit of claim 1, wherein: The source drive module includes an inductor L2 and a diode D7; one end of the inductor L2 is connected to one end of the diode D7, and the other end is connected to the load output interface; the other end of the diode D7 is connected to the rectifier module, and the common terminal of the inductor L2 and the diode D7 is connected to the drain of the power switch Q1.

3. The source-driven buck power factor correction circuit of claim 1, wherein: The rectifier module includes a differential mode inductor L1, a rectifier bridge, and capacitors C1, C2, and C3. The differential mode inductor L1, the rectifier bridge, and capacitor C2 are connected in sequence to form a circuit. The rectifier bridge is connected to the current input interface. The common terminal of the differential mode inductor L1 and capacitor C2 is connected to the load output interface. Both ends of capacitor C3 are connected to the load output interface. One end of capacitor C1 is connected to the common terminal of the differential mode inductor L1 and the rectifier bridge, and the other end is connected to the common terminal of the rectifier bridge and capacitor C2.

4. The source-driven buck power factor correction circuit of claim 3, wherein: The rectifier bridge includes diodes D1, D2, D3, D4, D5, and D6; one end of diode D1 is connected to differential mode inductor L1, and its other end is connected to capacitor C2 through diode D4; one end of diode D2 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D5; one end of diode D3 is connected to the common terminal of differential mode inductor L1 and diode D1, and its other end is connected to the common terminal of diode D4 and capacitor C2 through diode D6; the common terminals of diodes D1 and D4, D2 and D5, and D3 and D6 are respectively connected to the current input interface.

5. The source-driven buck power factor correction circuit according to claim 3, characterized in that: The rectifier module also includes capacitor C4, which is connected in parallel with capacitor C3.

6. The source-driven buck power factor correction circuit according to claim 1, characterized in that: The current sampling module includes a capacitor C11 and resistors R2, R10, and R11. One end of the capacitor C11 is connected to pin 3 of the main control chip U1, and the other end is connected to the source of the power switch Q1 through resistors R11, R10, and R2 in sequence. The common terminal of resistors R10 and R11 is connected to pin 3 of the main control chip U1.

7. The source-driven buck power factor correction circuit according to claim 1, characterized in that: The voltage sampling module includes capacitors C8, C9, and C10, and resistors R5, R6, R7, R8, and R9. One end of capacitor C8 is connected to pin 5 of the main control chip U1, and its other end is connected to the rectifier module through resistors R8, R9, R5, R6, and R7 in sequence. One end of capacitor C9 is connected to pin 5 of the main control chip U1, and its other end is connected to the common terminal of resistors R8 and R9. Capacitor C10 is connected in parallel with resistor R9, and the common terminal of resistors R9 and R5 is connected to pin 6 of the main control chip U1.

8. The source-driven buck power factor correction circuit according to claim 1, characterized in that: It also includes a diode D8 and a resistor R1; one end of the diode D8 is connected to the gate of the power switch Q1, and the other end is connected to pin 8 of the main control chip U1; the resistor R1 is connected in parallel with the diode D8.

9. The source-driven buck power factor correction circuit according to claim 1, characterized in that: It also includes capacitors C5, C6, and C7, and resistors R3 and R4; one end of capacitor C5 is connected to pin 7 of the main control chip U1, and the other end is grounded; one end of capacitor C6 is connected to pin 2 of the main control chip U1, and the other end is grounded; one end of capacitor C7 is connected to pin 4 of the main control chip U1, and the other end is grounded; resistor R3 is connected in parallel with capacitor C7; one end of resistor R4 is connected to pin 4 of the main control chip U1, and the other end is connected to pin 7 of the main control chip U1.

10. The source-driven buck power factor correction circuit according to claim 3, characterized in that: The capacitor C3 is a ceramic capacitor.

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