An improved negative voltage conversion circuit

Abstract

This invention discloses an improved negative voltage conversion circuit, including a Schmitt trigger NAND gate integrated circuit U1D and an NPN transistor Q1 and a PNP transistor Q2 that are alternately turned on under the control of the Schmitt trigger NAND gate integrated circuit U1D. The Schmitt trigger NAND gate integrated circuit U1D is connected to an RC network. A resistor R2 is connected to the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D, and the other end of the resistor R2 is connected to the base of the NPN transistor Q1 and the PNP transistor Q2. The collector of the NPN transistor Q1 is connected to the input positive voltage power supply VCC. The emitters of both the NPN transistor Q1 and the PNP transistor Q2 are connected to a capacitor C1. The collector of the PNP transistor Q2 is connected to the ground terminal GND1. A conversion circuit for realizing a negative output voltage is connected between the capacitor C1 and the ground terminal GND1. This invention not only provides adjustable output negative voltage but also features a simple circuit, low cost, and high reliability.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to an improved negative voltage conversion circuit. Background Technology

[0002] In UPS modules, many chips require both positive and negative voltage to function properly. However, the internal switching power supply of the module only provides positive voltage. Requiring negative voltage often necessitates more complex circuitry. Currently, to achieve negative voltage, a separate winding of the switching power supply transformer is often used to output negative voltage. However, this circuit still requires a voltage regulator chip to stabilize the output negative voltage. The transformer winding process is complex, involving numerous circuit components, making it prone to damage. Furthermore, this method has limited applicability; for chips with different supply voltages, the transformer parameters must be modified or a different power supply module must be used. This limits the application scenarios and makes cost control difficult. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an improved negative voltage conversion circuit to solve the problems mentioned in the background art.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows.

[0005] An improved negative voltage conversion circuit includes a Schmitt trigger NAND gate integrated circuit U1D and an NPN transistor Q1 and a PNP transistor Q2 that are alternately turned on under the control of the Schmitt trigger NAND gate integrated circuit U1D. The Schmitt trigger NAND gate integrated circuit U1D is connected to an RC network. A resistor R2 is connected to the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D. The other end of the resistor R2 is connected to the base of the NPN transistor Q1 and the PNP transistor Q2. The collector of the NPN transistor Q1 is connected to the input positive voltage power supply VCC. The emitters of both the NPN transistor Q1 and the PNP transistor Q2 are connected to a capacitor C1. The collector of the PNP transistor Q2 is connected to the base ground terminal GND1. A conversion circuit for realizing the output negative voltage is connected between the capacitor C1 and the base ground terminal GND1.

[0006] Preferably, the Schmitt trigger NAND gate integrated circuit U1D is a NAND gate unit in the CD4093 chip.

[0007] Preferably, the ground pin 7 of the Schmitt trigger NAND gate integrated circuit U1D is connected to a common ground terminal GND, and the power supply pin 14 of the Schmitt trigger NAND gate integrated circuit U1D is connected to the input positive voltage power supply VCC.

[0008] Preferably, the RC network includes a resistor R1 and a capacitor C4; one end of the resistor R1 is connected between the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D and the resistor R2, the other end of the resistor R1 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to the base ground terminal GND1; the input pins 12 and 13 of the Schmitt trigger NAND gate integrated circuit U1D are connected between the resistor R1 and the capacitor C4.

[0009] Preferably, the conversion circuit includes a clamping diode D2 connected between capacitor C1 and the base ground terminal GND1, a capacitor C2 connected in parallel with the clamping diode D2, a capacitor C3 connected in parallel with the capacitor C2, and a clamping diode D1 connected between capacitor C2 and the clamping diode D2 and connected to capacitor C1.

[0010] The technological advancements achieved by this utility model are as follows, due to the adoption of the above technical solutions.

[0011] This invention, through a Schmitt trigger AND gate integrated circuit U1D, resistor R2, RC network, NPN transistor Q1, PNP transistor Q2, and conversion circuit, can not only complete the conversion from positive input voltage to negative output voltage, but also make the output negative voltage adjustable. The circuit is simple, low-cost, and highly reliable. At the same time, it can effectively filter out signal noise, ensure output stability, and provide flexible and adjustable output voltage, making it suitable for a variety of products. Attached Figure Description

[0012] Figure 1 This is the circuit diagram of this utility model; Figure 2 This is the energy circuit diagram of the NPN transistor of this invention when it is turned on; Figure 3 This is the energy circuit diagram of the PNP transistor of this invention when it is turned on. Detailed Implementation

[0013] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0014] An improved negative voltage conversion circuit, combined with Figure 1As shown, the circuit includes a Schmitt trigger NAND gate integrated circuit U1D, an NPN transistor Q1, and a PNP transistor Q2. The NPN transistor Q1 and the PNP transistor Q2 conduct alternately under the control of the Schmitt trigger NAND gate integrated circuit U1D. The Schmitt trigger NAND gate integrated circuit U1D is connected to an RC network. A resistor R2 is connected to pin 11 of the Schmitt trigger NAND gate integrated circuit U1D, and the other end of resistor R2 is connected to the base of both the NPN transistor Q1 and the PNP transistor Q2. The collector of the NPN transistor Q1 is connected to the positive input voltage power supply VCC. The emitters of both the NPN transistor Q1 and the PNP transistor Q2 are connected to a capacitor C1, which is used for storing and discharging charge. The collector of the PNP transistor Q2 is connected to the ground terminal GND1. A switching circuit is connected between capacitor C1 and the ground terminal GND1 to achieve a negative output voltage.

[0015] The Schmitt trigger NAND gate integrated circuit U1D is the NAND gate unit in the CD4093 chip. The ground pin 7 of the Schmitt trigger NAND gate integrated circuit U1D is connected to the common ground terminal GND, and the power supply pin 14 of the Schmitt trigger NAND gate integrated circuit U1D is connected to the input positive voltage power supply VCC.

[0016] The RC network includes resistor R1 and capacitor C4. One end of resistor R1 is connected between output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D and resistor R2. The other end of resistor R1 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to the ground terminal GND1. Input pins 12 and 13 of the Schmitt trigger NAND gate integrated circuit U1D are connected between resistor R1 and capacitor C4.

[0017] The switching circuit includes clamping diodes D1 and D2, capacitors C2 and C3. Clamping diode D2 is connected between capacitor C1 and the base ground terminal GND1, clamping diode D2 to clamp the voltage across capacitor C1. Capacitor C2 is connected in parallel with clamping diode D2, and capacitor C2 is used for storing and discharging charge. Capacitor C3 is connected in parallel with capacitor C2, and capacitor C3 is used for storing and discharging charge. Clamping diode D1 is connected between capacitor C2 and clamping diode D2 and is connected to capacitor C1, clamping diode D1 to clamp the voltage across capacitor C1. Specifically, the anode of clamping diode D1 is connected to the cathode of capacitor C1, the cathode of clamping diode D1 is connected to capacitors C2 and C3, the cathode of clamping diode D2 is connected to the anode of capacitor C1, and the anode of clamping diode D2 is connected to the base ground terminal GND1.

[0018] This invention has two working states: either NPN transistor Q1 is turned on, or PNP transistor Q2 is turned on, and the output negative voltage can power the chip.

[0019] like Figure 2 As shown, when the input positive voltage power supply VCC is initially powered on, the input pins 12 and 13 of the Schmitt trigger NAND gate integrated circuit U1D are low, and the output pin 11 is high. At this time, the NPN transistor Q1 is turned on and begins to charge the capacitor C1. The energy circuit is: input positive voltage power supply VCC → NPN transistor Q1 → capacitor C1 → clamping diode D2 → ground terminal GND1. When the capacitor C1 is fully charged, the clamping diode D2 acts as a clamping diode, so that the voltage across the capacitor C1 is the output voltage minus the voltage drop of the clamping diode D2.

[0020] like Figure 3 As shown, when the output pin 11 is high, the voltage at this point discharges to the base ground terminal GND1 through resistor R1 and capacitor C4. When the voltage discharge is 0V, PNP transistor Q2 turns on. Since capacitor C1 has been charged in the previous stage, the left side of capacitor C1 is positive and the right side is negative. The energy flow path is capacitor C1+ → PNP transistor Q2 → capacitors C2 and C3 → clamping diode D1 → capacitor C1-. At this time, since the voltage on the upper side of capacitors C2 and C3 is negative, the output negative voltage is related to the discharge time of capacitor C1. The discharge of capacitor C1 is related to the time it takes for resistor R1 and capacitor C4 connected in series with the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D to discharge to the base ground terminal GND1. Therefore, the output negative voltage value can be adjusted by adjusting the values ​​of resistor R1 and capacitor C4.

Claims

1. An improved negative voltage conversion circuit, characterized in that: The system includes a Schmitt trigger NAND gate integrated circuit U1D and an NPN transistor Q1 and a PNP transistor Q2 that are alternately turned on under the control of the Schmitt trigger NAND gate integrated circuit U1D. The Schmitt trigger NAND gate integrated circuit U1D is connected to an RC network. A resistor R2 is connected to the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D. The other end of the resistor R2 is connected to the base of the NPN transistor Q1 and the PNP transistor Q2. The collector of the NPN transistor Q1 is connected to the positive input voltage power supply VCC. The emitters of both the NPN transistor Q1 and the PNP transistor Q2 are connected to a capacitor C1. The collector of the PNP transistor Q2 is connected to the base ground terminal GND1. A conversion circuit for realizing a negative output voltage is connected between the capacitor C1 and the base ground terminal GND1.

2. The improved negative voltage conversion circuit according to claim 1, characterized in that: The Schmitt trigger NAND gate integrated circuit U1D is the NAND gate unit in the CD4093 chip.

3. The improved negative voltage conversion circuit according to claim 1, characterized in that: The ground pin 7 of the Schmitt trigger NAND gate integrated circuit U1D is connected to a common ground terminal GND, and the power supply pin 14 of the Schmitt trigger NAND gate integrated circuit U1D is connected to the input positive voltage power supply VCC.

4. The improved negative voltage conversion circuit according to claim 1, characterized in that: The RC network includes a resistor R1 and a capacitor C4; one end of the resistor R1 is connected between the output pin 11 of the Schmitt trigger NAND gate integrated circuit U1D and the resistor R2, and the other end of the resistor R1 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to the base ground terminal GND1; the input pins 12 and 13 of the Schmitt trigger NAND gate integrated circuit U1D are connected between the resistor R1 and the capacitor C4.

5. An improved negative voltage conversion circuit according to claim 1, characterized in that: The switching circuit includes a clamping diode D2 connected between capacitor C1 and the base ground terminal GND1, a capacitor C2 connected in parallel with the clamping diode D2, a capacitor C3 connected in parallel with the capacitor C2, and a clamping diode D1 connected between capacitor C2 and the clamping diode D2 and connected to capacitor C1.

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