A high-performance frequency conversion module for receivers

Abstract

This utility model relates to the field of receiver frequency conversion technology, specifically to a high-performance receiver frequency conversion module, comprising a receiving antenna, a low-noise amplifier, a frequency conversion module, and a baseband processor connected in sequence. The frequency conversion module includes two mixers, two decimation filter banks, two couplers, two variable attenuators, two detectors, two analog-to-digital converter chips, and a control chip. The couplers are used to couple sampled signals, the detectors are used to extract analog amplitudes, the analog-to-digital converter chips are used to convert the extracted analog amplitudes into digital signals, and the control chip controls the variable attenuators based on the transmitted digital signals to ensure that the output signal amplitudes of the two orthogonal signal channels are the same. This utility model can dynamically eliminate the amplitude imbalance problem of the two orthogonal channels, control the consistency error of the output amplitude of the two channels, significantly reduce the demodulation error of the baseband processor, and improve the signal reception accuracy and long-term stability of the receiver.

Description

Technical Field

[0001] This utility model relates to the field of receiver frequency conversion technology, and more specifically, to a high-performance frequency conversion module for receivers. Background Technology

[0002] As a core device in fields such as communication, radar, and navigation, the receiver's core function is to receive external high-frequency signals and convert them into baseband signals for subsequent processing. The frequency conversion module is the key link in realizing the conversion of high-frequency signals to baseband signals, and its performance directly determines the receiver's signal processing accuracy, anti-interference ability, and long-term stability.

[0003] The utility model patent with announcement number CN221613019U discloses a miniaturized radar signal device, including: a signal source, a radio frequency front-end module, a baseband processing module, and a data processing module; the radio frequency front-end module includes: a signal transmitting module and a signal receiving module, the signal transmitting module includes: a mixer, a phase shifter, a power amplifier, and a transmitting antenna; the signal receiving module includes: a receiving antenna, a low-noise amplifier, and a mixer.

[0004] Although this utility model integrates and optimizes functional modules within the smallest possible size, it relies solely on matching hardware parameters in the early stages to ensure the consistency of the forward circuit. However, over long-term use, performance degradation can easily occur due to component aging and changes in environmental temperature and humidity. Utility Model Content

[0005] The purpose of this invention is to provide a high-performance frequency conversion module for a receiver to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: A high-performance frequency conversion module for a receiver includes a receiving antenna, a low-noise amplifier, a frequency conversion module, and a baseband processor, which are electrically connected in sequence. The frequency conversion module includes two mixers, two decimation filter banks, two couplers, two variable attenuators, two detectors, two analog-to-digital converter chips, and a control chip. The input terminals of both mixers are electrically connected to the output terminal of the low-noise amplifier. The two mixers, two decimation filter banks, two couplers, and two variable attenuators constitute two orthogonal signal channels. The mixers and decimation filter banks in each orthogonal channel... The coupler and the variable attenuator are electrically connected in sequence. The output terminals of the two variable attenuators are electrically connected to different input terminals of the baseband processor. Each positive signal channel corresponds to one detector and one analog-to-digital converter chip. The coupled signal output terminal of the coupler is electrically connected to the corresponding input terminal of the detector. The output terminal of the detector is electrically connected to the corresponding input terminal of the analog-to-digital converter chip. The output terminals of the two analog-to-digital converter chips are electrically connected to different input terminals of the control chip. The different output terminals of the control chip are electrically connected to the control terminals of the two variable attenuators. The coupler is used to couple the sampled signal, the detector is used to extract the analog amplitude, the analog-to-digital converter chip is used to convert the extracted analog amplitude into a digital signal, and the control chip controls the variable attenuator based on the transmitted digital signal to make the output signal amplitudes of the two orthogonal signal channels the same.

[0007] Preferably, the frequency conversion module further includes a numerically controlled oscillator and a phase shifter. The numerically controlled oscillator is used to generate two local oscillator signals, and the phase shifter is used to shift the phase of one local oscillator signal. The two orthogonal local oscillator signals are respectively input into the two mixers.

[0008] In this setup, the numerically controlled oscillator outputs a local oscillator signal with high frequency accuracy and stability, effectively avoiding mixing signal errors caused by local oscillator frequency drift and providing a stable frequency reference for the conversion from high-frequency to intermediate-frequency signals. The phase shifter precisely shifts the phase of one local oscillator signal, ensuring that the local oscillator signals input to the two mixers form a strictly orthogonal relationship. This design reduces subsequent amplitude imbalance problems caused by phase deviation at the source of high-frequency signal conversion, making the signal conversion process of the mixer more stable and reducing noise interference in the mixed signal. This lays a foundation for better signal quality in subsequent filtering and amplitude calibration stages using decimation filter banks.

[0009] Preferably, the coupler includes a coupling sampling chip U1, and the coupling sampling chip U1 is of model PDC-20-3+; The input terminal of the coupling sampling chip U1 is connected to the output terminal of the corresponding decimation filter group, and the output terminal of the coupling sampling chip U1 is connected to the input terminal of the corresponding variable attenuator.

[0010] Preferably, the detector includes a power supply VCC, a detector chip U2, resistors R1 and R2, capacitors C1, C2 and C3, and the detector chip U2 is model AD8310. The first terminal of capacitor C1 is grounded, and the second terminal of capacitor C1 is connected to pin 1 of detector chip U2. The first terminal of resistor R1 is grounded, and the second terminal of resistor R1 is connected to the coupled signal output terminal of coupling sampling chip U1. The first terminal of capacitor C2 is connected to the second terminal of resistor R1, and the second terminal of capacitor C2 is connected to pin 8 of detector chip U2. The first terminal of capacitor C3 is connected to pin 5 of detector chip U2, and the second terminal of capacitor C3 is grounded. The first terminal of resistor R2 is connected to both pin 7 of detector chip U2 and the first terminal of capacitor C3. The second terminal of resistor R2 is connected to power supply VCC. Pin 4 of detector chip U2 is connected to the input terminal of the analog-to-digital converter chip.

[0011] Preferably, the control chip has an analog signal output port, and the control chip controls the attenuation of the two variable attenuators through different analog signal output ports.

[0012] These three settings, through the coordinated action of the coupler, variable attenuator, detector, analog-to-digital converter chip, and control chip, ensure that the signal amplitude output from the two variable attenuators to the baseband processor remains consistent, thereby reducing the demodulation error of the baseband processor.

[0013] Compared with the prior art, the beneficial effects of this utility model are: This invention, by setting up a real-time calibration loop consisting of a coupler, detector, analog-to-digital converter chip, control chip, and variable attenuator, can dynamically eliminate the amplitude imbalance problem between the two positive channels. Compared with the passive compensation of existing fixed attenuators, this mechanism can adapt to signal fluctuations, device aging, and environmental changes, control the output amplitude consistency error of the two channels, significantly reduce the demodulation error of the baseband processor, and improve the signal reception accuracy and long-term stability of the receiver. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall structure of the utility model; Figure 2 This is a schematic diagram of the structure of the frequency converter module in the utility model. Figure 3 This is one of the partial structural schematic diagrams of a frequency converter module in a utility model. Figure 4 This is the second partial structural schematic diagram of the frequency converter module in the utility model. Figure 5 This is a circuit diagram of the coupler in the utility model. Figure 6 This is the circuit schematic diagram of the detector in the utility model. In the picture: 100. Receiving antenna; 200. Low-noise amplifier; 300. Variable frequency drive module; 301. Mixer; 302. Digitally controlled oscillator; 303. Phase shifter; 304. Decimation filter bank; 305. Coupler; 306. Variable attenuator; 307. Detector; 308. Analog-to-digital converter chip; 309. Control chip; 400. Baseband processor. Detailed Implementation

[0015] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Please see Figures 1-6 The present invention provides the following technical solution: A high-performance frequency conversion module for a receiver includes a receiving antenna 100, a low-noise amplifier 200, a frequency conversion module 300, and a baseband processor 400, which are electrically connected in sequence. The frequency conversion module 300 includes two mixers 301, two decimation filter banks 304, two couplers 305, two variable attenuators 306, two detectors 307, two analog-to-digital converter chips 308, and a control chip 309. The input terminals of the two mixers 301 are electrically connected to the output terminals of the low-noise amplifier 200. The two mixers 301, two decimation filter banks 304, two couplers 305, and two variable attenuators 306 constitute two orthogonal signal channels. The mixer in each orthogonal channel... 301, decimation filter bank 304, coupler 305, and variable attenuator 306 are electrically connected in sequence. The output terminals of the two variable attenuators 306 are electrically connected to different input terminals of the baseband processor 400. Each positive signal channel corresponds to a detector 307 and an analog-to-digital converter chip 308. The coupled signal output terminal of the coupler 305 is electrically connected to the corresponding input terminal of the detector 307. The output terminal of the detector 307 is electrically connected to the corresponding input terminal of the analog-to-digital converter chip 308. The output terminals of the two analog-to-digital converter chips 308 are electrically connected to different input terminals of the control chip 309. The different output terminals of the control chip 309 are electrically connected to the control terminals of the two variable attenuators 306. Coupler 305 is used to couple the sampled signal, detector 307 is used to extract the analog amplitude, analog-to-digital converter chip 308 is used to convert the extracted analog amplitude into a digital signal, and control chip 309 controls variable attenuator 306 based on the transmitted digital signal to make the output signal amplitudes of the two orthogonal signal channels the same. Through the dynamic calibration loop of coupler 305, detector 307, analog-to-digital converter chip 308, control chip 309 and variable attenuator 306, the amplitude imbalance of the two orthogonal signal channels caused by device aging, temperature and humidity changes and signal fluctuations can be eliminated in real time. Compared with the traditional method that only relies on the matching of hardware parameters in the early stage, it has stronger adaptability.

[0016] In this embodiment, please refer to Figure 1 The frequency conversion module 300 also includes a numerically controlled oscillator 302 and a phase shifter 303. The numerically controlled oscillator 302 is used to generate two local oscillator signals, and the phase shifter 303 is used to shift the phase of one local oscillator signal. The two orthogonal local oscillator signals are respectively input into two mixers 301. The numerically controlled oscillator 302 can output local oscillator signals with high frequency accuracy and strong stability, avoiding mixing errors caused by local oscillator frequency drift. The phase shifter 303 precisely controls the phase shift angle to ensure that the two local oscillator signals are strictly orthogonal, reducing the subsequent amplitude imbalance problem caused by phase deviation from the source of signal frequency conversion. The orthogonal local oscillator signals provide stable phase support for the mixer 301 to convert high-frequency signals into intermediate-frequency signals, making the mixing process of the two orthogonal signal channels more synchronized, reducing noise interference of the mixed signal, and laying a good foundation for subsequent decimation filtering and amplitude calibration.

[0017] In this embodiment, please refer to Figures 1-6 Coupler 305 includes a coupling sampling chip U1, the model of which is PDC-20-3+; The input terminal of the coupling sampling chip U1 is connected to the output terminal of the corresponding decimation filter group 304, and the output terminal of the coupling sampling chip U1 is connected to the input terminal of the corresponding variable attenuator 306. The coupling coefficient of this chip is stable, and the amplitude characteristics of the sampled signal are highly consistent with those of the main signal, providing a reliable signal source for the detector 307 to extract accurate analog amplitude information and avoiding inaccurate subsequent calibration results due to sampling deviation.

[0018] Specifically, detector 307 includes power supply VCC, detector chip U2, resistor R1, resistor R2, capacitor C1, capacitor C2 and capacitor C3, and detector chip U2 is model AD8310. The first terminal of capacitor C1 is grounded, and the second terminal of capacitor C1 is connected to pin 1 of detector chip U2. The first terminal of resistor R1 is grounded, and the second terminal of resistor R1 is connected to the coupled signal output terminal of coupling sampling chip U1. The first terminal of capacitor C2 is connected to the second terminal of resistor R1, and the second terminal of capacitor C2 is connected to pin 8 of detector chip U2. The first terminal of capacitor C3 is connected to pin 5 of detector chip U2, and the second terminal of capacitor C3 is grounded. The first terminal of resistor R2 is connected to both pin 7 of detector chip U2 and the first terminal of capacitor C3, and the second terminal of resistor R2 is connected to power supply VCC. Pin 4 of detector chip U2 is connected to the input terminal of analog-to-digital converter chip 308. Detector chip U2 has a wide dynamic range and high sensitivity, which can accurately extract the analog amplitude information of the coupled signal. Even when faced with weak coupled signals, it can stably output amplitude data, avoiding calibration deviations caused by insufficient detection accuracy.

[0019] Furthermore, the control chip 309 has an analog signal output port. The control chip 309 controls the attenuation of the two variable attenuators 306 through different analog signal output ports. The analog signal output port can realize continuous adjustment of the attenuation. Compared with the digital adjustment method, it can more precisely match the amplitude difference between the two channels and avoid residual amplitude consistency error caused by excessive adjustment interval. The transmission of analog control signal and the change of attenuation of variable attenuator 306 have no digital signal conversion delay. It can respond to the amplitude fluctuation of the two channels in real time, quickly complete calibration, ensure that the amplitude imbalance problem during signal transmission is corrected in time, and reduce the impact on the demodulation process of baseband processor 400.

[0020] Finally, it should be noted that all electronic components involved in this utility model are general standard parts or components known to those skilled in the art. Their structures and principles can be learned by those skilled in the art through technical manuals or conventional experimental methods, and their detailed connection methods are all technologies known in the art.

[0021] In use, the high-performance frequency conversion module of this utility model receives external high-frequency signals through the receiving antenna 100 and transmits them to the low-noise amplifier 200. The low-noise amplifier 200 amplifies the high-frequency signals with low noise and then inputs them to the two mixers 301 of the frequency conversion module 300. At the same time, the digitally controlled oscillator 302 generates two local oscillator signals. The phase shifter 303 shifts the phase of one of the local oscillator signals by 90 degrees, forming two orthogonal local oscillator signals, which are then input to the two mixers 301 respectively. The mixers 301 mix the amplified high-frequency signals with the orthogonal local oscillator signals to convert them into intermediate frequency signals. After the intermediate frequency signals are filtered out by the decimation filter bank 304, they are input to the coupler 305. The coupler 305 couples the sampled intermediate frequency signals and transmits them to the detector 307. The detector 307 extracts the analog amplitude of the sampled signals, and the analog-to-digital converter chip 308 converts the analog amplitude into a digital signal and transmits it to the control chip 309. The control chip 309 receives digital signals transmitted from two analog-to-digital converter chips 308 in real time through its different input terminals. These two digital signals correspond to the signal amplitude information of two orthogonal signal channels, respectively. The control chip 309 has a built-in data processing algorithm that compares the received two digital amplitude signals in real time. First, it calculates the difference between the two amplitudes. The control chip 309 sets an amplitude consistency threshold, which is preset according to the receiver's demodulation accuracy requirements. It then determines whether the difference is within the threshold range. If the difference is within the threshold range, it means that the output amplitude of the two channels has met the consistency requirements, and the control chip 309 does not output an adjustment signal at this time. If the difference exceeds the threshold range, it indicates an amplitude imbalance. The control chip 309 then proceeds to the next step of control signal generation. Based on the amplitude difference, the control chip 309 generates and outputs targeted analog control signals to the corresponding variable attenuator 306 through its different analog signal output ports. The amplitude of the analog control signal is linearly related to the attenuation of the variable attenuator 306, ensuring the precision of the attenuation adjustment and avoiding over-adjustment that could lead to a new amplitude imbalance. This ensures that the signal amplitudes of the two channels output to the baseband processor 400 are consistent, and the baseband processor 400 finally completes the signal demodulation and subsequent processing.

[0022] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A high-performance frequency conversion module for a receiver, comprising a receiving antenna (100), a low-noise amplifier (200), a frequency conversion module (300), and a baseband processor (400) connected in sequence, characterized in that: The frequency conversion module (300) includes two mixers (301), two decimation filter banks (304), two couplers (305), two variable attenuators (306), two detectors (307), two analog-to-digital converter chips (308), and a control chip (309). The input terminals of the two mixers (301) are electrically connected to the output terminal of the low-noise amplifier (200). The two mixers (301), the two decimation filter banks (304), the two couplers (305), and the two variable attenuators (306) constitute two orthogonal signal channels. The mixers (301), the decimation filter banks (304), the couplers (305), and the variable attenuators in each orthogonal channel are... The devices (306) are electrically connected in sequence. The output terminals of the two variable attenuators (306) are respectively electrically connected to different input terminals of the baseband processor (400). Each positive traffic channel corresponds to one detector (307) and one analog-to-digital converter (308). The coupling signal output terminal of the coupler (305) is electrically connected to the corresponding input terminal of the detector (307). The output terminal of the detector (307) is electrically connected to the corresponding input terminal of the analog-to-digital converter (308). The output terminals of the two analog-to-digital converters (308) are respectively electrically connected to different input terminals of the control chip (309). The different output terminals of the control chip (309) are respectively electrically connected to the control terminals of the two variable attenuators (306). The coupler (305) is used to couple the sampled signal, the detector (307) is used to extract the analog amplitude, the analog-to-digital converter (308) is used to convert the extracted analog amplitude into a digital signal, and the control chip (309) controls the variable attenuator (306) based on the transmitted digital signal to make the output signal amplitudes of the two orthogonal signal channels the same.

2. The high-performance frequency conversion module for a receiver according to claim 1, characterized in that: The frequency conversion module (300) also includes a numerically controlled oscillator (302) and a phase shifter (303). The numerically controlled oscillator (302) is used to generate two local oscillator signals, and the phase shifter (303) is used to shift the phase of one local oscillator signal. The two orthogonal local oscillator signals are respectively input into the two mixers (301).

3. The high-performance frequency conversion module for a receiver according to claim 1, characterized in that: The coupler (305) includes a coupling sampling chip U1, the model of which is PDC-20-3+; The input terminal of the coupling sampling chip U1 is connected to the output terminal of the corresponding decimation filter group (304), and the output terminal of the coupling sampling chip U1 is connected to the input terminal of the corresponding variable attenuator (306).

4. The high-performance frequency conversion module for a receiver according to claim 3, characterized in that: The detector (307) includes a power supply VCC, a detector chip U2, resistors R1 and R2, capacitors C1, C2 and C3, and the detector chip U2 is model AD8310. The first terminal of capacitor C1 is grounded, and the second terminal of capacitor C1 is connected to pin 1 of detector chip U2. The first terminal of resistor R1 is grounded, and the second terminal of resistor R1 is connected to the coupled signal output terminal of coupling sampling chip U1. The first terminal of capacitor C2 is connected to the second terminal of resistor R1, and the second terminal of capacitor C2 is connected to pin 8 of detector chip U2. The first terminal of capacitor C3 is connected to pin 5 of detector chip U2, and the second terminal of capacitor C3 is grounded. The first terminal of resistor R2 is connected to both pin 7 of detector chip U2 and the first terminal of capacitor C3. The second terminal of resistor R2 is connected to power supply VCC. Pin 4 of detector chip U2 is connected to the input terminal of the analog-to-digital converter chip (308).

5. The high-performance frequency conversion module for a receiver according to claim 1, characterized in that: The control chip (309) has an analog signal output port, and the control chip (309) controls the attenuation of the two variable attenuators (306) through different analog signal output ports.

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